DE3673437D1 - Verfahren zum herstellen eines halbleiterbauelements mit einem graben. - Google Patents

Verfahren zum herstellen eines halbleiterbauelements mit einem graben.

Info

Publication number
DE3673437D1
DE3673437D1 DE8686102225T DE3673437T DE3673437D1 DE 3673437 D1 DE3673437 D1 DE 3673437D1 DE 8686102225 T DE8686102225 T DE 8686102225T DE 3673437 T DE3673437 T DE 3673437T DE 3673437 D1 DE3673437 D1 DE 3673437D1
Authority
DE
Germany
Prior art keywords
trench
producing
semiconductor component
semiconductor
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686102225T
Other languages
English (en)
Inventor
Shin-Ichi C O Patent Divi Taka
Jiro C O Patent Divisi Ohshima
Masahiro C O Patent Divisi Abe
Masaharu C O Patent Div Aoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3673437D1 publication Critical patent/DE3673437D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/80—Heterojunction BJTs
    • H10D10/821—Vertical heterojunction BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
DE8686102225T 1985-02-20 1986-02-20 Verfahren zum herstellen eines halbleiterbauelements mit einem graben. Expired - Lifetime DE3673437D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60030576A JPS61191043A (ja) 1985-02-20 1985-02-20 半導体装置

Publications (1)

Publication Number Publication Date
DE3673437D1 true DE3673437D1 (de) 1990-09-20

Family

ID=12307673

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686102225T Expired - Lifetime DE3673437D1 (de) 1985-02-20 1986-02-20 Verfahren zum herstellen eines halbleiterbauelements mit einem graben.

Country Status (5)

Country Link
US (1) US4717682A (de)
EP (1) EP0193116B1 (de)
JP (1) JPS61191043A (de)
KR (1) KR900001245B1 (de)
DE (1) DE3673437D1 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3320944C2 (de) * 1982-06-21 1997-03-27 Young Eng Glättvorrichtung für Bahnkanten
US4929996A (en) * 1988-06-29 1990-05-29 Texas Instruments Incorporated Trench bipolar transistor
US5188971A (en) * 1988-12-28 1993-02-23 Synergy Semiconductor Corporation Process for making a self-aligned bipolar sinker structure
US5213994A (en) * 1989-05-30 1993-05-25 Motorola, Inc. Method of making high voltage semiconductor device
KR940006696B1 (ko) * 1991-01-16 1994-07-25 금성일렉트론 주식회사 반도체 소자의 격리막 형성방법
US5250837A (en) * 1991-05-17 1993-10-05 Delco Electronics Corporation Method for dielectrically isolating integrated circuits using doped oxide sidewalls
US5358884A (en) * 1992-09-11 1994-10-25 Micron Technology, Inc. Dual purpose collector contact and isolation scheme for advanced bicmos processes
US5275965A (en) * 1992-11-25 1994-01-04 Micron Semiconductor, Inc. Trench isolation using gated sidewalls
JP2914117B2 (ja) * 1993-08-28 1999-06-28 日本電気株式会社 半導体装置の製造方法
US5387540A (en) * 1993-09-30 1995-02-07 Motorola Inc. Method of forming trench isolation structure in an integrated circuit
US5856700A (en) * 1996-05-08 1999-01-05 Harris Corporation Semiconductor device with doped semiconductor and dielectric trench sidewall layers
US5933717A (en) * 1997-03-04 1999-08-03 Advanced Micro Devices, Inc. Vertical transistor interconnect structure and fabrication method thereof
US6069384A (en) * 1997-03-04 2000-05-30 Advanced Micro Devices, Inc. Integrated circuit including vertical transistors with spacer gates having selected gate widths
US6097076A (en) 1997-03-25 2000-08-01 Micron Technology, Inc. Self-aligned isolation trench
SE513471C2 (sv) * 1997-11-17 2000-09-18 Ericsson Telefon Ab L M Halvledarkomponent och tillverkningsförfarande för halvledarkomponent
US6153934A (en) * 1998-07-30 2000-11-28 International Business Machines Corporation Buried butted contact and method for fabricating
US20060076629A1 (en) * 2004-10-07 2006-04-13 Hamza Yilmaz Semiconductor devices with isolation and sinker regions containing trenches filled with conductive material
GB0507157D0 (en) * 2005-04-08 2005-05-18 Ami Semiconductor Belgium Bvba Double trench for isolation of semiconductor devices
US7982284B2 (en) * 2006-06-28 2011-07-19 Infineon Technologies Ag Semiconductor component including an isolation structure and a contact to the substrate
US7691734B2 (en) * 2007-03-01 2010-04-06 International Business Machines Corporation Deep trench based far subcollector reachthrough

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3947299A (en) * 1971-05-22 1976-03-30 U.S. Philips Corporation Method of manufacturing semiconductor devices
US4140558A (en) * 1978-03-02 1979-02-20 Bell Telephone Laboratories, Incorporated Isolation of integrated circuits utilizing selective etching and diffusion
US4322883A (en) * 1980-07-08 1982-04-06 International Business Machines Corporation Self-aligned metal process for integrated injection logic integrated circuits
US4488162A (en) * 1980-07-08 1984-12-11 International Business Machines Corporation Self-aligned metal field effect transistor integrated circuits using polycrystalline silicon gate electrodes
JPS5734331A (en) * 1980-08-11 1982-02-24 Toshiba Corp Manufacture of semiconductor device
DE3168688D1 (en) * 1980-11-06 1985-03-14 Toshiba Kk Method for manufacturing a semiconductor device
FR2498812A1 (fr) * 1981-01-27 1982-07-30 Thomson Csf Structure de transistors dans un circuit integre et son procede de fabrication
US4508579A (en) * 1981-03-30 1985-04-02 International Business Machines Corporation Lateral device structures using self-aligned fabrication techniques
JPS59220952A (ja) * 1983-05-31 1984-12-12 Toshiba Corp 半導体装置の製造方法
US4507853A (en) * 1982-08-23 1985-04-02 Texas Instruments Incorporated Metallization process for integrated circuits
JPS5992548A (ja) * 1982-11-18 1984-05-28 Toshiba Corp 半導体装置及びその製造方法
US4589193A (en) * 1984-06-29 1986-05-20 International Business Machines Corporation Metal silicide channel stoppers for integrated circuits and method for making the same
US4549927A (en) * 1984-06-29 1985-10-29 International Business Machines Corporation Method of selectively exposing the sidewalls of a trench and its use to the forming of a metal silicide substrate contact for dielectric filled deep trench isolated devices

Also Published As

Publication number Publication date
EP0193116B1 (de) 1990-08-16
KR860006832A (ko) 1986-09-15
US4717682A (en) 1988-01-05
KR900001245B1 (ko) 1990-03-05
EP0193116A3 (en) 1987-08-19
EP0193116A2 (de) 1986-09-03
JPS61191043A (ja) 1986-08-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee