JPS5771175A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5771175A JPS5771175A JP14799880A JP14799880A JPS5771175A JP S5771175 A JPS5771175 A JP S5771175A JP 14799880 A JP14799880 A JP 14799880A JP 14799880 A JP14799880 A JP 14799880A JP S5771175 A JPS5771175 A JP S5771175A
- Authority
- JP
- Japan
- Prior art keywords
- film
- region
- electrode
- substrate
- grown
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Abstract
PURPOSE:To increase the reliability of wiring by reducing a step difference in the surface of a substrate and to obtain a fine pattern as well by a method wherein an interlayer insulating film is composed by using a semiconductor amorphous material in a semiconductor device and a part of the film is made as a conductor to provide a contact region. CONSTITUTION:A channel stopper region 2 is formed around an Si substrate 1 and the upper part of the region 2 is covered with a thick field oxide film 3 to form a thin gate oxide film 4 at the central part of the substrate 1 surrounded by the film 3 and a gate electrode 5 consisting of polycrystalline Si is provided on the film 4. Next, the electrode 5 is used as a mask and source and drain regions 6 are formed in self alignment manner by diffusion or ion implantation, and the electrde 5 is made low in resistance and an amorphous Si film 71 is grown on the whole surface by using silane tatra fluoride. Then, the surface of the film 71 is covered with an Si3N4 film 72 to perforate an opening by corresponding to the region 6 and the electrode 5 and low resistance contact regions 73 connected to the region 6 and the elctrode 5 are grown in the film 71 by implanting impurity ions and each Al electrode 9 is deposited on the surface of a region 73.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14799880A JPS5771175A (en) | 1980-10-22 | 1980-10-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14799880A JPS5771175A (en) | 1980-10-22 | 1980-10-22 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5771175A true JPS5771175A (en) | 1982-05-01 |
Family
ID=15442820
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14799880A Pending JPS5771175A (en) | 1980-10-22 | 1980-10-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5771175A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0193117A2 (en) * | 1985-02-20 | 1986-09-03 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
| US4725877A (en) * | 1986-04-11 | 1988-02-16 | American Telephone And Telegraph Company, At&T Bell Laboratories | Metallized semiconductor device including an interface layer |
-
1980
- 1980-10-22 JP JP14799880A patent/JPS5771175A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0193117A2 (en) * | 1985-02-20 | 1986-09-03 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
| US4725877A (en) * | 1986-04-11 | 1988-02-16 | American Telephone And Telegraph Company, At&T Bell Laboratories | Metallized semiconductor device including an interface layer |
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