CN107665829B - 晶圆混合键合中提高金属引线制程安全性的方法 - Google Patents

晶圆混合键合中提高金属引线制程安全性的方法 Download PDF

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CN107665829B
CN107665829B CN201710732727.2A CN201710732727A CN107665829B CN 107665829 B CN107665829 B CN 107665829B CN 201710732727 A CN201710732727 A CN 201710732727A CN 107665829 B CN107665829 B CN 107665829B
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metal
layer
silicon nitride
metal lead
nonmetal
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CN107665829A (zh
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严孟
朱继锋
胡思平
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Priority to CN201880005485.XA priority patent/CN110121766B/zh
Priority to PCT/CN2018/098508 priority patent/WO2019037584A1/en
Priority to TW107127561A priority patent/TWI691022B/zh
Priority to US16/126,935 priority patent/US10763158B2/en
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Priority to US17/009,452 priority patent/US11322392B2/en
Priority to US17/703,602 priority patent/US11670543B2/en
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Abstract

本发明公开了一种晶圆混合键合中提高金属引线制程安全性的方法，属于半导体领域。所述方法包括：提供衬底；在衬底的上表面形成非金属层，并在非金属层中形成金属导体；在含有金属导体的非金属层的上表面形成含有两层氮化硅层和两层氧化硅层交错层叠的介电层；对介电层进行平坦化工艺处理；在平坦化工艺处理后的介电层上，以对氮化硅层和氧化硅层预设的刻蚀速率比进行刻蚀形成金属引线沟槽，至非金属层中的金属导体的上表面部分裸露；对金属引线沟槽进行金属填充得到金属引线。本发明中的技术方案，提高了晶圆混合键合中金属引线制程的安全性和良率。

Description

晶圆混合键合中提高金属引线制程安全性的方法
技术领域
本发明涉及半导体领域，尤其涉及一种晶圆混合键合中提高金属引线制程安全性的方法。
背景技术
随着人们对电子产品的要求向小型化、多功能化、环保化等多方向的发展，各企业努力将电子系统做的越来越小，集成越来越高，功能越来越多。由此也产生了许多新技术、新材料和新设计，三维集成就是其中的典型代表。而晶圆混合键合技术(Hybrid Bonding)是三维集成中的关键技术之一，在晶圆混合键合技术中，首选需要形成金属引线将金属层引出到晶圆表面，但由于晶圆在键合前需要进行平坦化处理，而平坦化处理会使得金属层之上的介电层膜厚均一性较差；因此在制作金属引线制作时，往往需要刻蚀膜厚均一性较差的介电层，目前在刻蚀过程中，利用氮化硅作为金属的阻挡层，并根据刻蚀程式对氧化硅和氮化硅的高选择比来解决这一问题。然而该方式并不完善，当介电层膜厚均一性差异过大时，对于膜厚过高的地方金属引线则不能连通金属层，会导致该区域芯片电性能失败，而对于膜厚过低的地方金属层会遭受到刻蚀过程中电离气体的长时间轰击，会对电性能及可靠性等产生影响，从而降低良率。
发明内容
为解决现有技术的不足，本发明提供一种晶圆混合键合中提高金属引线制程安全性的方法，包括：
提供衬底；
在所述衬底的上表面形成非金属层，所述非金属层覆盖所述衬底的上表面，并在所述非金属层中形成金属导体；
在含有所述金属导体的非金属层的上表面形成含有两层氮化硅层和两层氧化硅层交错层叠的介电层，所述介电层覆盖所述非金属层的上表面；
对所述介电层进行平坦化工艺处理；
在平坦化工艺处理后的介电层上，以对所述氮化硅层和所述氧化硅层预设的刻蚀速率比进行刻蚀形成金属引线沟槽，至所述非金属层中的金属导体的上表面部分裸露；
对所述金属引线沟槽进行金属填充得到金属引线。
可选地，根据化学气相沉积的方法，在所述衬底的上表面形成非金属层；
可选地，根据化学气相沉积的方法，在所述非金属层的上表面形成含有两层氮化硅层和两层氧化硅层交错层叠的介质层。
可选地，所述在所述非金属层中形成金属导体，具体包括：在所述非金属层中刻蚀出预设电路图案沟槽，在所述预设电路图案沟槽中填充金属至超过所述非金属层的上表面，并去除所述非金属层上表面的金属形成金属导体，所述金属导体的上表面与所述非金属层的上表面齐平。
可选地，所述在含有所述金属导体的非金属层的上表面形成含有两层氮化硅层和两层氧化硅层交错层叠的介质层，具体包括：
在含有所述金属导体的非金属层的上表面形成第一氮化硅层，所述第一氮化硅层覆盖所述非金属层的上表面；
在所述第一氮化硅层的上表面形成第一氧化硅层，所述第一氧化硅层覆盖所述第一氮化硅层的上表面；
在所述第一氧化硅层的上表面形成第二氮化硅层，所述第二氮化硅层覆盖所述第一氧化硅层的上表面；
在所述第二氮化硅层的上表面形成第二氧化硅层，所述第二氧化硅层覆盖所述第二氮化硅层的上表面。
可选地，刻蚀形成的金属引线沟槽的宽度小于所述金属导体的宽度。
可选地，所述金属导体为铜；
所述对所述金属引线沟槽进行金属填充得到金属引线，具体为：对所述金属引线沟槽填充铜得到金属引线。
可选地，所述对所述金属引线沟槽进行金属填充得到金属引线之前，还包括：清洗所述金属引线沟槽。
可选地，所述对所述金属引线沟槽进行金属填充形成金属引线，具体包括：对所述金属引线沟槽进行金属填充至超过所述介电层的上表面，并去除所述介电层上表面的金属形成金属引线，所述金属引线的上表面与所述介电层的上表面齐平。
本发明的优点在于：
本发明中，通过多添加一层氮化硅层，并结合对氮化硅层和氧化硅层不同的刻蚀速率比，缩小了介电层膜厚的差异，从而提高晶圆混合键合中金属引线制程的安全性和良率。
附图说明
通过阅读下文优选实施方式的详细描述，各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的，而并不认为是对本发明的限制。而且在整个附图中，用相同的参考符号表示相同的部件。在附图中：
附图1为现有技术中金属引线制程的理想状态示意图；
附图2为现有技术中金属引线制程中刻蚀的膜厚变化示意图；
附图3为本发明提供的一种晶圆混合键合中提高金属引线制程安全性的方法流程图；
附图4为本发明提供的待混合晶圆的结构示意图；
附图5为本发明提供的金属导体的形成过程示意图；
附图6为本发明提供的金属引线制程中刻蚀的膜厚变化示意图；
附图7为本发明提供的金属填充形成金属引线的过程示意图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
为更清晰的体现本发明中技术方案的优点，现对现有技术中晶圆混合键合中制作金属引线方法的缺陷进行进一步说明。如图1所示，设定刻蚀两个金属引线沟槽100和200，理想的金属引线制程是将各金属引线与金属层中对应的金属导体相连通，但由于介电层膜厚差异过大，使得制作出理想的金属引线100需要刻蚀的膜厚相对于制作出理想的金属引线200需要刻蚀的膜厚要低。进一步地，对于现有技术中制作金属引线100和金属引线200时，刻蚀膜厚的变化过程，用以下数据进行示意说明，如图2所示，包括两个过程：
为便于说明，设定刻蚀两个金属引线沟槽100和金属引线沟槽200时，需要刻蚀氧化硅层的最薄膜厚8000A(图中C点)和最厚膜厚12000A(图中D点)，需要刻蚀的氮化硅层的膜厚为1000A；
过程a：以氧化硅的刻蚀速率为5A/s，氮化硅的刻蚀速率为1A/s，即两者的刻蚀速率比为5:1，对金属引线沟槽100和金属引线沟槽200同时开始刻蚀；
当金属引线沟槽100刻蚀到C点时，金属引线沟槽200刻蚀到M点，此时MD之间的膜厚为12000A-8000A＝4000A，刻蚀完MD需要的时间为4000A/(5A/s)＝800s，此时间内，由于金属引线沟槽100刻蚀到C点时并未停止，而是接下来以1A/s的速率刻蚀氮化硅，则刻蚀的膜厚CN为(800s)*(1A/s)＝800A，即：此时金属引线沟槽100和金属引线沟槽200在氮化硅层的膜厚差为800A，并进入过程b；
过程b：对于金属引线沟槽100和金属引线沟槽200，均以1A/s的速率刻蚀氮化硅层，至金属层中的金属导体的上表面部分显露。
经由上述过程a和过程b可以得知，在将氧化硅层全部刻蚀完时，在氮化硅层金属引线沟槽100和金属引线沟槽200的膜厚差为800A，对于金属引线沟槽100而言，当其将氮化硅层全部刻蚀完至对应的金属层中的金属导体的上表面部分显露时，如果此时停止刻蚀，则金属引线沟槽200刻蚀至点W处，不能连通金属层中对应的金属导体；如果此时继续刻蚀至金属引线沟槽200对应的金属层中的金属导体的上表面部分显露时，则金属引线沟槽100对应的金属导体会因电离气体的长时间轰击而电性能降低，从而降低良率。
为解决上述现有技术中的缺陷，本发明提供一种晶圆混合键合中提高金属引线制程安全性的方法，如图3和图4所示，包括：
提供衬底；
在衬底的上表面形成非金属层，非金属层覆盖衬底的上表面，并在非金属层中形成金属导体；
在含有金属导体的非金属层的上表面形成含有两层氮化硅层和两层氧化硅层交错层叠的介电层，介电层覆盖非金属层的上表面；
对介电层进行平坦化工艺处理；
在平坦化工艺处理后的介电层上，以对氮化硅层和氧化硅层预设的刻蚀速率比进行刻蚀形成金属引线沟槽，至非金属层中的金属导体的上表面部分裸露；
对金属引线沟槽进行金属填充得到金属引线。
优选地，在本实施例中，提供的衬底为硅衬底。
根据本发明的实施方式，根据化学气相沉积的方法，在衬底的上表面形成非金属层；
根据本发明的实施方式，根据化学气相沉积的方法，在非金属层的上表面形成含有两层氮化硅层和两层氧化硅层交错层叠的介质层。
根据本发明的实施方式，在非金属层中形成金属导体，具体包括：在非金属层中刻蚀出预设电路图案沟槽，在预设电路图案沟槽中填充金属至超过非金属层的上表面，并去除非金属层上表面的金属形成金属导体，且金属导体的上表面与非金属层的上表面齐平；
更加具体地，如图5所示，在非金属层中形成金属导体，具体包括：采用干法刻蚀在非金属层中刻蚀出预设电路图案沟槽，根据物理气象沉积的方法，在所述预设电路图案沟槽中填充金属，并采用化学机械研磨的方式去掉多余的金属形成金属导体，且金属导体的上表面与非金属层的上表面齐平。
根据本发明的实施方式，在含有金属导体的非金属层的上表面形成含有两层氮化硅层和两层氧化硅层交错层叠的介质层，具体包括：
在含有金属导体的非金属层的上表面形成第一氮化硅层，第一氮化硅层覆盖非金属层的上表面；
在第一氮化硅层的上表面形成第一氧化硅层，第一氧化硅层覆盖第一氮化硅层的上表面；
在第一氧化硅层的上表面形成第二氮化硅层，第二氮化硅层覆盖第一氧化硅层的上表面；
在第二氮化硅层的上表面形成第二氧化硅层，第二氧化硅层覆盖第二氮化硅层的上表面。
在本实施例中，对第一氮化硅层、第一氧化硅层、第二氮化硅层、第二氧化硅层的厚度均不作限定，依据具体需求自行设定。
进一步地，在本实施例中，正是由于两层氮化硅层的设计，并结合氮化硅层与氧化硅层不同的刻蚀速率比，来实现缩小膜厚差异，具体地，如图6所示，用以下数据进行示意说明，其包含四个过程：
为便于说明，仍设定刻蚀两个金属引线沟槽100和200，对应地，需要刻蚀第二氧化硅层的最薄膜厚8000A(图中C点)和最厚膜厚12000A(图中D点)，需要刻蚀的第一氧化硅层、第一氮化硅层、第二氮化硅层的膜厚均为1000A；
过程一：以氧化硅的刻蚀速率为5A/s，氮化硅的刻蚀速率为1A/s，即两者的刻蚀速率比为5:1，对金属引线沟槽100和金属引线沟槽200同时开始刻蚀；
当金属引线沟槽100刻蚀到C点时，金属引线沟槽200刻蚀到M点，此时MD之间的膜厚为12000A-8000A＝4000A，刻蚀完MD需要的时间为4000A/(5A/s)＝800s，此时间内，由于金属引线沟槽100刻蚀到C点时并未停止，而是接下来以1A/s的速率刻蚀氮化硅，则刻蚀的膜厚CN为(800s)*(1A/s)＝800A，即：此时金属引线沟槽100和金属引线沟槽200在第二氮化硅层的膜厚差为800A，并进入过程二；
过程二：以氧化硅的刻蚀速率和氮化硅的刻蚀速率均为1A/s继续进行刻蚀；
当金属引线沟槽100继续刻蚀至F点，即刻蚀膜厚NF＝NE+EF＝200A+1000A＝1200A时，金属引线沟槽200继续刻蚀至H点，且刻蚀长度DH＝DK+KH＝1000A+200A＝1200A，此时进入过程三；
过程三：以氧化硅的刻蚀速率为5A/s，氮化硅的刻蚀速率为1A/s，即两者的刻蚀速率比为5:1继续进行刻蚀；
当金属引线沟槽200继续刻蚀至L点，即开始进入第一氮化硅层，其刻蚀膜厚为HL＝KL-KH＝1000A-200A＝800A时，用时为(800A)/(5A/s)＝160s，此时间内，金属引线沟槽100继续刻蚀至P点，且刻蚀膜厚FP为(1A/s)*(160s)＝160A，至此金属引线沟槽100和200均在第一氮化硅层，且膜厚差为160A，相对于在第二氮化硅层的膜厚差大大减小；且接下来进入过程四；
过程四：对于金属引线沟槽100和金属引线沟槽200，均以1A/s的速率刻蚀第一氮化硅层，至金属层中的金属导体的上表面部分显露；
以上过程中，过程一和过程四即为在现有技术中的刻蚀过程a和过程b，可见，本发明中的方法，相对于现有技术而言，通过增加一层氮化硅层，使得在第一氧化硅层以上全部刻蚀完时，金属引线沟槽100和金属引线沟槽200在第一氮化硅层的膜厚差由800A降低至160A，大大降低了膜厚差，进而提高了金属引线制程的安全性和良率。
根据本发明的实施方式，对介电层进行平坦化工艺处理，具体为：利用化学机械研磨工艺(Chemical Mechanical Polishing，简称CMP)对介电层进行平坦化工艺处理。
进一步地，根据本发明的实施方式，刻蚀形成的金属引线沟槽的宽度小于金属导体的宽度。
在本实施例中，金属引线沟槽的数量(即金属引线的数量)为大于2的整数；但在本实施例中，对于金属引线沟槽的宽度(即金属引线的宽度)、以及金属引线沟槽的数量均不作具体限定，依据实际需求而定。
根据本发明的实施方式，金属导体为铜；
对应地，对金属引线沟槽进行金属填充得到金属引线，具体为：对金属引线沟槽填充铜得到金属引线。
根据本发明的实施方式，对金属引线沟槽进行金属填充形成金属引线，具体包括：对金属引线沟槽进行金属填充至超过介电层的上表面，并去除介电层上表面的金属形成金属引线，且金属引线的上表面与介电层的上表面齐平；
更加具体地，如图7所示，对金属引线沟槽进行金属填充形成金属引线，具体包括：根据物理气相沉积的方法，对金属引线沟槽进行金属填充至超过介电层的上表面，并采用化学机械研磨的方式去掉介电层上表面多余的金属形成金属引线，且金属引线的上表面与介电层的上表面齐平。
根据本发明的实施方式，对金属引线沟槽进行金属填充得到金属引线之前，还包括：清洗金属引线沟槽。
更进一步地，在本实施例中，对于待混合键合的两个晶圆均按照上述方法制作金属引线完成后，即可进行混合键合操作得到键合晶圆。
以上所述，仅为本发明较佳的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (7)

1.一种晶圆混合键合中提高金属引线制程安全性的方法，其特征在于，包括：
提供衬底；
在所述衬底的上表面形成非金属层，所述非金属层覆盖所述衬底的上表面，并在所述非金属层中形成金属导体；
在含有所述金属导体的非金属层的上表面形成含有两层氮化硅层和两层氧化硅层交错层叠的介电层，所述介电层覆盖所述非金属层的上表面；
对所述介电层进行平坦化工艺处理；
在平坦化工艺处理后的介电层上，以对所述氮化硅层和所述氧化硅层预设的刻蚀速率比进行刻蚀形成金属引线沟槽，至所述非金属层中的金属导体的上表面部分裸露，所述金属引线沟槽的宽度小于所述金属导体的宽度；
对所述金属引线沟槽进行金属填充得到金属引线。
2.根据权利要求1所述的方法，其特征在于，
根据化学气相沉积的方法，在所述衬底的上表面形成非金属层；
根据所述化学气相沉积的方法，在所述非金属层的上表面形成含有两层氮化硅层和两层氧化硅层交错层叠的介质层。
3.根据权利要求1所述的方法，其特征在于，所述在所述非金属层中形成金属导体，具体包括：在所述非金属层中刻蚀出预设电路图案沟槽，在所述预设电路图案沟槽中填充金属至超过所述非金属层的上表面，并去除所述非金属层上表面的金属形成金属导体，所述金属导体的上表面与所述非金属层的上表面齐平。
4.根据权利要求1所述的方法，其特征在于，所述在含有所述金属导体的非金属层的上表面形成含有两层氮化硅层和两层氧化硅层交错层叠的介质层，具体包括：
在含有所述金属导体的非金属层的上表面形成第一氮化硅层，所述第一氮化硅层覆盖所述非金属层的上表面；
在所述第一氮化硅层的上表面形成第一氧化硅层，所述第一氧化硅层覆盖所述第一氮化硅层的上表面；
在所述第一氧化硅层的上表面形成第二氮化硅层，所述第二氮化硅层覆盖所述第一氧化硅层的上表面；
在所述第二氮化硅层的上表面形成第二氧化硅层，所述第二氧化硅层覆盖所述第二氮化硅层的上表面。
5.根据权利要求1所述的方法，其特征在于，
所述金属导体为铜；
所述对所述金属引线沟槽进行金属填充得到金属引线，具体为：对所述金属引线沟槽填充铜得到金属引线。
6.根据权利要求1所述的方法，其特征在于，所述对所述金属引线沟槽进行金属填充得到金属引线之前，还包括：清洗所述金属引线沟槽。
7.根据权利要求1所述的方法，其特征在于，所述对所述金属引线沟槽进行金属填充形成金属引线，具体包括：对所述金属引线沟槽进行金属填充至超过所述介电层的上表面，并去除所述介电层上表面的金属形成金属引线，所述金属引线的上表面与所述介电层的上表面齐平。
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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10276377B2 (en) * 2016-05-20 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Method for patterning interconnects
CN107665829B (zh) 2017-08-24 2019-12-17 长江存储科技有限责任公司 晶圆混合键合中提高金属引线制程安全性的方法
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US11749645B2 (en) 2018-06-13 2023-09-05 Adeia Semiconductor Bonding Technologies Inc. TSV as pad
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
CN109686657B (zh) * 2018-11-29 2021-04-13 长江存储科技有限责任公司 晶圆间键合结构的形成方法、晶圆的键合方法
CN113488505B (zh) 2019-04-30 2022-09-30 长江存储科技有限责任公司 具有三维相变存储器的三维存储设备
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101770865A (zh) * 2008-12-30 2010-07-07 中芯国际集成电路制造(上海)有限公司 电容器
CN102024786A (zh) * 2009-09-09 2011-04-20 中芯国际集成电路制造(上海)有限公司 用于互连工艺中的半导体器件及其制造方法
CN105679654A (zh) * 2016-01-27 2016-06-15 武汉新芯集成电路制造有限公司 一种用于混合式键合工艺的晶圆预处理工艺

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4594769A (en) * 1984-06-15 1986-06-17 Signetics Corporation Method of forming insulator of selectively varying thickness on patterned conductive layer
US6244811B1 (en) 1999-06-29 2001-06-12 Lam Research Corporation Atmospheric wafer transfer module with nest for wafer transport robot
US7311852B2 (en) * 2001-03-30 2007-12-25 Lam Research Corporation Method of plasma etching low-k dielectric materials
US20030190829A1 (en) * 2002-04-05 2003-10-09 Brennan Kenneth D. Dual damascene barrier structures and preferential etching method
JP4034115B2 (ja) * 2002-05-14 2008-01-16 富士通株式会社 半導体装置の製造方法
JP4370789B2 (ja) * 2002-07-12 2009-11-25 東京エレクトロン株式会社 プラズマ処理装置及び可変インピーダンス手段の校正方法
JP2004079901A (ja) * 2002-08-21 2004-03-11 Nec Electronics Corp 半導体装置及びその製造方法
JP3762732B2 (ja) * 2002-09-27 2006-04-05 三洋電機株式会社 半導体装置の製造方法
JP2005277375A (ja) * 2004-02-27 2005-10-06 Nec Electronics Corp 半導体装置の製造方法
US7138717B2 (en) 2004-12-01 2006-11-21 International Business Machines Corporation HDP-based ILD capping layer
JP4641817B2 (ja) * 2005-02-09 2011-03-02 株式会社神戸製鋼所 半導体装置用積層基板の製造方法及び半導体装置
JP4927343B2 (ja) * 2005-03-18 2012-05-09 ルネサスエレクトロニクス株式会社 半導体チップおよびその製造方法
US20070082479A1 (en) * 2005-10-06 2007-04-12 Applied Materials, Inc. Chemical mechanical polishing techniques for integrated circuit fabrication
JP4533304B2 (ja) * 2005-11-29 2010-09-01 富士通セミコンダクター株式会社 半導体装置の製造方法
KR100888202B1 (ko) * 2006-09-28 2009-03-12 주식회사 하이닉스반도체 반도체 소자 제조방법
JP2009016400A (ja) * 2007-06-29 2009-01-22 Toshiba Corp 積層配線構造体及びその製造方法並びに半導体装置及びその製造方法
US7704869B2 (en) * 2007-09-11 2010-04-27 International Business Machines Corporation Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias
JP2013077805A (ja) * 2011-09-16 2013-04-25 Hitachi Kokusai Electric Inc 半導体装置の製造方法、基板処理方法、基板処理装置およびプログラム
US8846474B2 (en) * 2012-08-20 2014-09-30 Tokyo Electron Limited Dual workfunction semiconductor devices and methods for forming thereof
CN103730349B (zh) * 2012-10-10 2016-08-03 中芯国际集成电路制造(上海)有限公司 一种形成接触孔的方法
US8895453B2 (en) * 2013-04-12 2014-11-25 Infineon Technologies Ag Semiconductor device with an insulation layer having a varying thickness
CN103199058B (zh) * 2013-04-19 2015-04-08 中微半导体设备(上海)有限公司 一种通孔的刻蚀方法
US9054164B1 (en) * 2013-12-23 2015-06-09 Intel Corporation Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches
JP6327295B2 (ja) 2015-08-12 2018-05-23 セントラル硝子株式会社 ドライエッチング方法
US9570463B1 (en) * 2015-10-15 2017-02-14 Sandisk Technologies Llc Multilevel memory stack structure with joint electrode having a collar portion and methods for manufacturing the same
CN105552035B (zh) * 2016-01-08 2019-01-11 武汉华星光电技术有限公司 低温多晶硅tft阵列基板的制作方法及其结构
CN106356365A (zh) * 2016-10-10 2017-01-25 武汉新芯集成电路制造有限公司 半导体器件及其制备方法
CN107665829B (zh) * 2017-08-24 2019-12-17 长江存储科技有限责任公司 晶圆混合键合中提高金属引线制程安全性的方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101770865A (zh) * 2008-12-30 2010-07-07 中芯国际集成电路制造(上海)有限公司 电容器
CN102024786A (zh) * 2009-09-09 2011-04-20 中芯国际集成电路制造(上海)有限公司 用于互连工艺中的半导体器件及其制造方法
CN105679654A (zh) * 2016-01-27 2016-06-15 武汉新芯集成电路制造有限公司 一种用于混合式键合工艺的晶圆预处理工艺

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