US6660564B2 - Wafer-level through-wafer packaging process for MEMS and MEMS package produced thereby - Google Patents

Wafer-level through-wafer packaging process for MEMS and MEMS package produced thereby Download PDF

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US6660564B2
US6660564B2 US10/057,368 US5736802A US6660564B2 US 6660564 B2 US6660564 B2 US 6660564B2 US 5736802 A US5736802 A US 5736802A US 6660564 B2 US6660564 B2 US 6660564B2
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metal
substrate
bonding
functional element
connectors
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US20030143775A1 (en
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Frederick T. Brady
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Sony Corp
Sony Electronics Inc
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032Packages or encapsulation
    • B81B7/007Interconnections between the MEMS and external electrical signals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container

Definitions

  • the present invention relates to a wafer-level packaging process for MEMS applications, and more specifically, to a method for putting electrical feed-throughs through an SOI wafer.
  • MEMS microelectromechanical systems
  • the functional element such as a circuit, sensor or actuator
  • the functional elements are flexible structures operable within a hermetically sealed cavity.
  • the challenge in packaging MEMS is achieving the electrical connection without opening the cavity to the environment, and to do this with a simple process that results in a small overall footprint and outline.
  • the MEMS should be fabricated to form a functional element within a hermetically sealed cavity in the semiconductor wafer having an overall structure of small dimension both laterally and vertically.
  • Past and current attempts to achieve such MEMS include die-level hermetic packaging, but this method produces a device with a large package size at a high cost.
  • Another example is a buried feed-through, but this is a relatively complex process.
  • Still another example is first bonding, then sealing open areas with high temperature LPCVD films, but high temperature processing is not compatible with many metals present on the wafers.
  • the present invention provides a wafer-level packaging process for MEMS applications in which a SOI (silicon-on-insulator) wafer is bonded to a MEMS wafer and the electrical feed-throughs are achieved through the SOI wafer.
  • the process of the present invention is a simple procedure involving no high temperatures and results in a small, thin device with functional elements hermetically sealed therein.
  • the method includes providing a first substrate having the functional element thereon connected to at least one metal lead, and providing a second SOI substrate having a recessed cavity in a silicon portion thereof with metal connectors formed in the recessed cavity. The non-recessed surfaces of the second SOI substrate are bonded to the first substrate to form a hermetically sealed cavity.
  • the metal leads are bonded to respective metal connectors.
  • the recessed cavity Prior to bonding, the recessed cavity has a depth that is greater than the thickness of the functional element and less than the combined thickness of the metal leads and their respective metal connectors.
  • silicon from the second SOI substrate is removed to expose the buried oxide portion of the second SOI substrate.
  • Metal pads are then formed through the second SOI substrate to the metal connectors within the cavity, such as by etching vias in the substrate and depositing the metal pads within the vias. Wire bond pads are thereby connected to the functional element without opening the cavity to the environment. Electrical signals may then be fed through the SOI wafer to the metal connectors, metal leads and the functional element.
  • an oxide layer is grown on the SOI wafer both on the surface to be bonded to the first substrate and within the recessed cavity to provide electrical isolation between electrical connectors.
  • a passivation layer is applied over the buried oxide layer of the SOI substrate and over the metal pads.
  • FIGS. 1-9 schematically depict an embodiment of the method of the present invention for packaging a MEMS device, wherein:
  • FIG. 1 depicts the starting first substrate
  • FIG. 2 depicts formation of a functional element and metal leads on the first substrate
  • FIG. 3 depicts the starting second SOI substrate
  • FIG. 4 depicts the formation of a recessed cavity in a silicon portion of the second SOI substrate
  • FIG. 5 depicts the formation of the metal connectors within the recessed cavity
  • FIG. 6 depicts the bonding of the first substrate to the second SOI substrate and the bonding of the metal connectors to the metal leads;
  • FIG. 7 depicts the removal of the second silicon portion of the SOI substrate to expose the buried oxide layer
  • FIG. 8 depicts the formation of vias through the SOI wafer to expose the metal connectors within the recessed cavity
  • FIG. 9 depicts the formation of the metal pads within the vias for electrical connection to the functional element hermetically sealed within the cavity, and depicts the completed MEMS package produced by the method of FIGS. 1-9.
  • FIGS. 4A-9A depict an embodiment similar to FIGS. 4-9, but including the formation of an oxide layer on a surface of the silicon portion and within the recessed cavity before the metal connectors are formed, and FIG. 9A further depicts the resulting completed MEMS package.
  • FIGS. 10 and 10A depict embodiments of the present invention including a passivation layer.
  • FIGS. 11 and 11A depict embodiments of the present invention including a single wire bond pad connecting a hermetically sealed functional element to a metal lead in another cavity.
  • FIG. 12 is a flow chart for methods of the present invention.
  • the method of the present invention uses an SOI wafer as wafer-level packaging material, and puts electrical feed-throughs through the SOI wafer.
  • the processing is simple, no high temperature steps are required, and the resulting die is small and thin, and does not require complex packaging to achieve cavity hermeticity.
  • FIGS. 1-9 schematically depict the method by which a MEMS device is packaged according to the present invention.
  • a first substrate 10 is provided.
  • This wafer or substrate 10 may be any silicon or non-silicon wafer, such as a Pyrex glass wafer.
  • the functional element 12 is formed on the surface 11 of the first substrate 10 .
  • the term “functional element” refers to the microelectromechanical device, which may for example be a circuit, sensor or actuator.
  • the method for forming the functional element 12 on the first substrate 10 may be by any method known to one skilled in the art. Once formed, the functional element 12 will have a thickness t 1 .
  • At least two metal leads 14 are formed on the surface 11 of the first substrate 10 , at least one of those metal leads 14 being connected to the functional element 12 . In one embodiment of the present invention, shown in FIG. 2, two metal leads 14 are formed and connected to the functional element 12 .
  • a typical semiconductor device includes a plurality of functional elements 12 , each having electrical connections in and out of the functional element 12 .
  • the metal leads 14 generally comprise a soft metal, for example aluminum, gold, aluminum alloys, or gold alloys. When formed, the metal leads 14 have a thickness t 2 .
  • a second substrate 20 is provided, which is a SOI wafer.
  • SOI wafer refers to a silicon-on-insulator in which a thin oxide layer 22 is buried within the silicon substrate 24 .
  • SOI substrate 20 comprises a first silicon portion 24 a , a second silicon portion 24 b , and a silicon oxide layer 22 therebetween. SOI wafers are well known in the art of semiconductor devices.
  • a recessed cavity 26 is formed in the first silicon portion 24 a of the second SOI substrate 20 .
  • Any known method for material removal may be used in the method of the present invention to form the recessed cavity 26 .
  • the recessed cavity 26 may be formed by reactive ion etching (RIE), which may use for example a dry plasma of SF 6 .
  • RIE reactive ion etching
  • wet chemical etching may be used, for example using KOH.
  • the recessed cavity 26 is etched to a depth d greater than the thickness t 1 of the functional element 12 formed on the first substrate 10 .
  • FIG. 1 depicted in FIG.
  • an oxide layer 28 is grown on the non-recessed surface 25 of the first silicon portion 24 a and within the recessed cavity 26 .
  • This oxide layer 28 may be grown by any method known to those skilled in the art, such as by thermal oxidation.
  • the oxide layer 28 provides electrical isolation between the electrical connectors.
  • the device is shown without the oxide layer 28
  • FIGS. 5A-9A the device is shown with the oxide layer 28 .
  • metal connectors 30 are formed in the recessed cavity 26 .
  • the metal connectors 30 are each positioned to correspond to a respective metal lead 14 formed on the first substrate 10 .
  • the metal connectors 30 may comprise a soft metal, such as aluminum, gold or an alloy of aluminum or gold.
  • the metal connectors 30 comprise the same metal as the metal leads 14 .
  • the metal connectors 30 have a thickness t 3 . Referring back to FIGS. 4 and 4A, the depth d of the recessed cavity 26 should be less than the combined thickness t 2 +t 3 of the metal leads 14 and metal connectors 30 .
  • the metal connectors 30 may be formed by any method known to those skilled in the art of semiconductor device fabrication.
  • FIG. 6 depicts the bonding of the second SOI substrate 20 to the first substrate 10 .
  • the non-recessed surface 25 of the SOI substrate 20 is bonded to the surface 11 of the first substrate 10 .
  • the metal leads 14 on the first substrate 10 are generally or partially aligned with the metal connectors 30 formed within the recessed cavity 26 of the second SOI substrate 20 . Because the depth d of the recessed cavity 26 is less than the combined thicknesses t 2 and t 3 of the metal leads 14 and metal connectors 30 , a metal lead 14 and respective metal connector 30 are fused together such that the resulting combined thickness is equal to the depth d of the recessed cavity 26 .
  • the recessed cavity 26 is hermetically sealed from the environment.
  • a space 32 remains within the sealed recessed cavity 26 above the functional element 12 by virtue of the depth d of the recessed cavity 26 being greater than the thickness t 1 of the functional element 12 .
  • the functional element 12 is thus enclosed in the hermetically sealed cavity 26 and movable therein.
  • the oxide layer 28 formed on the non-recessed surface 25 of the second SOI substrate 20 is bonded to the first substrate 10 .
  • the same effect of a hermetically sealed cavity 26 is achieved in this embodiment.
  • the bonding of the substrates 10 , 20 may be by room temperature fusion bonding or anodic bonding.
  • room temperature fusion bonding which is advantageously used when the first substrate 10 is a silicon-base substrate
  • the wafers 10 , 20 are cleaned and then bonded together by applying a pressure in the range of about 800-1400 pounds.
  • the bonded wafers are then cured at room temperature, for example, for a period of a few days. If it is desirable to accelerate the curing of the wafer bond, a low temperature annealing may be utilized, wherein the temperature is less than a temperature that would negatively effect the metal portions of the device, for example around 200° C.
  • the bonding may be anodic bonding, which may be advantageously used where the first substrate 10 is a Pyrex glass or other glass substrate.
  • Anodic bonding generally comprises applying an electrical bias in the range of about 100-1000 V, for example about 800 V to the wafers 10 , 20 in contact while applying a temperature in the range of about 300-500° C.
  • the second silicon portion 24 b of the second SOI substrate 20 not bonded to the first substrate 10 is removed to expose the buried oxide layer 22 .
  • the silicon may be removed by any method known to those skilled in the art, such as the RIE and wet etch methods discussed above with respect to formation of the recessed cavity 26 .
  • vias 34 are formed through the second SOI substrate 20 to expose the metal connectors 30 within the recessed cavity 26 .
  • the formation of the vias 34 will allow for electrical connections to be made through the SOI substrate 20 to the metal connectors 30 and metal leads 14 , and thus to the functional element 12 sealed within the cavity 26 , but does not break the hermetic seal and expose the functional element 12 to the environment.
  • the vias 34 may be etched by any method known to those skilled in the art.
  • the etching of the vias 34 may include a two-step process in which one method is used to etch through the oxide layer 22 of the SOI substrate 20 , and a second method is used to etch through the silicon portion 24 a of the SOI substrate 20 .
  • an HF-containing solution may be used to etch the oxide layer 22
  • the wet chemical etching or RIE methods discussed above may be used to etch through the Si layer 24 a.
  • FIGS. 9 and 9A depict the patterning of metal pads 36 for forming electrical connections with the functional element 12 .
  • the wire bond pads 36 are formed within the vias 34 on the metal connectors 30 and extend over a portion of the oxide layer 22 of the second SOI substrate 20 .
  • the formation of the metal pads 36 may be by any method known to those skilled in the art, and generally includes CVD and PVD methods.
  • the metal pads 36 may be aluminum with a barrier/adhesion liner or may be gold with an adhesion liner.
  • the metal pads may be Al/Ti/TiN or Au/Cr.
  • the MEMS package 40 ′ may include a passivation layer 42 formed over a portion of the wire bond metal pads 36 and over the exposed oxide portion 22 of the second SOI substrate 20 .
  • vias 44 are formed above at least a portion of the wire bond metal pads 36 .
  • the passivation layer 42 provides additional contamination control for the device 40 ′.
  • the final passivation layer 42 is a plasma nitride, and may be formed by blanket PECVD using silane and ammonia.
  • the via or pad openings 44 over the metal pads 36 may be formed by any material removal process known to those skilled in the art.
  • FIGS. 11 and 11A depict yet another embodiment of a method and resulting MEMS package 40 ′′ of the present invention.
  • the functional element 12 and one metal lead 14 a and metal connector 30 a are enclosed within one recessed cavity 26 a
  • a second recessed cavity 26 b is formed in the second SOI substrate 20 for a second metal lead 14 b and metal connector 30 b .
  • Vias 34 are formed through oxide layer 22 and silicon portion 24 a to each of the metal connectors 30 a , 30 b .
  • a wire bond pad 36 is formed in the vias 34 in the active SOI substrate 20 and over oxide layer 22 thereby using the top 23 of the oxide 22 as a temporary passage for the metal line.
  • FIG. 12 provides a flow chart for an exemplary embodiment of the method of the present invention.
  • the first step is to provide the first substrate.
  • the next step is to form the functional element or elements and the metal leads on the first substrate.
  • the first step is to provide a second SOI substrate having a first silicon layer, a second silicon layer, and a buried oxide layer therebetween.
  • the second step is to then etch a recess in the first silicon layer to form the recessed cavity.
  • the third step is to pattern the metal connectors within that recessed cavity.
  • An optional fourth step may include growing an oxide layer on the first silicon layer and within the recessed cavity.
  • the two substrates may then be bonded together by generally matching the position of the metal leads to the position of the metal connectors and bonding them together as well as bonding the non-recessed surface of the first silicon layer to the first substrate.
  • the second silicon layer of the SOI substrate is then removed to expose the buried oxide layer. Vias are then etched through the oxide layer and the first silicon layer to expose the metal connectors.
  • Metal pads are then patterned within the vias and at least partially over the oxide layer.
  • a final passivation layer may be formed over the metal pads and oxide layer to provide additional contamination resistance.

Abstract

A wafer-level packaging process for MEMS applications, and a MEMS package produced thereby, in which a SOI wafer is bonded to a MEMS wafer and the electrical feed-throughs are made through the SOI wafer. The method includes providing a first substrate having the functional element thereon connected to at least one metal lead, and providing a second SOI substrate having a recessed cavity in a silicon portion thereof with metal connectors formed in the recessed cavity. The non-recessed surfaces of the SOI substrate are bonded to the first substrate to form a hermetically sealed cavity. Within the cavity, the metal leads are bonded to respective metal connectors. Prior to bonding, the recessed cavity has a depth that is greater than the thickness of the functional element and less than the combined thickness of the metal leads and their respective metal connectors. After bonding, silicon from the SOI substrate is removed to expose the buried oxide portion of the SOI substrate. Metal pads are then formed through the SOI substrate to the metal connectors within the cavity. Wire bond pads are thereby connected to the functional element without opening the cavity to the environment. Electrical signals may then be fed through the SOI wafer to the metal connectors, metal leads and the functional element.

Description

FIELD OF THE INVENTION
The present invention relates to a wafer-level packaging process for MEMS applications, and more specifically, to a method for putting electrical feed-throughs through an SOI wafer.
BACKGROUND OF THE INVENTION
In microelectromechanical systems (MEMS), the functional element, such as a circuit, sensor or actuator, must often be separated from the environment, yet electrical signals must be sent to and received from the functional element. The functional elements are flexible structures operable within a hermetically sealed cavity. The challenge in packaging MEMS is achieving the electrical connection without opening the cavity to the environment, and to do this with a simple process that results in a small overall footprint and outline. In other words, the MEMS should be fabricated to form a functional element within a hermetically sealed cavity in the semiconductor wafer having an overall structure of small dimension both laterally and vertically.
Past and current attempts to achieve such MEMS include die-level hermetic packaging, but this method produces a device with a large package size at a high cost. Another example is a buried feed-through, but this is a relatively complex process. Still another example is first bonding, then sealing open areas with high temperature LPCVD films, but high temperature processing is not compatible with many metals present on the wafers.
A need thus exists in the semiconductor industry for a method for wafer-level packaging for MEMS applications that allow small footprints, small chip outlines, low-temperature processing, hermetic sealing, and low cost.
SUMMARY OF THE INVENTION
The present invention provides a wafer-level packaging process for MEMS applications in which a SOI (silicon-on-insulator) wafer is bonded to a MEMS wafer and the electrical feed-throughs are achieved through the SOI wafer. The process of the present invention is a simple procedure involving no high temperatures and results in a small, thin device with functional elements hermetically sealed therein. To this end, the method includes providing a first substrate having the functional element thereon connected to at least one metal lead, and providing a second SOI substrate having a recessed cavity in a silicon portion thereof with metal connectors formed in the recessed cavity. The non-recessed surfaces of the second SOI substrate are bonded to the first substrate to form a hermetically sealed cavity. Within the cavity, the metal leads are bonded to respective metal connectors. Prior to bonding, the recessed cavity has a depth that is greater than the thickness of the functional element and less than the combined thickness of the metal leads and their respective metal connectors. After bonding, silicon from the second SOI substrate is removed to expose the buried oxide portion of the second SOI substrate. Metal pads are then formed through the second SOI substrate to the metal connectors within the cavity, such as by etching vias in the substrate and depositing the metal pads within the vias. Wire bond pads are thereby connected to the functional element without opening the cavity to the environment. Electrical signals may then be fed through the SOI wafer to the metal connectors, metal leads and the functional element. In one embodiment of the method of the present invention, an oxide layer is grown on the SOI wafer both on the surface to be bonded to the first substrate and within the recessed cavity to provide electrical isolation between electrical connectors. In yet another embodiment of the method of the present invention, a passivation layer is applied over the buried oxide layer of the SOI substrate and over the metal pads.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with a general description of the invention given above, and the detailed description given below, serve to explain the invention.
FIGS. 1-9 schematically depict an embodiment of the method of the present invention for packaging a MEMS device, wherein:
FIG. 1 depicts the starting first substrate;
FIG. 2 depicts formation of a functional element and metal leads on the first substrate;
FIG. 3 depicts the starting second SOI substrate;
FIG. 4 depicts the formation of a recessed cavity in a silicon portion of the second SOI substrate;
FIG. 5 depicts the formation of the metal connectors within the recessed cavity;
FIG. 6 depicts the bonding of the first substrate to the second SOI substrate and the bonding of the metal connectors to the metal leads;
FIG. 7 depicts the removal of the second silicon portion of the SOI substrate to expose the buried oxide layer;
FIG. 8 depicts the formation of vias through the SOI wafer to expose the metal connectors within the recessed cavity; and
FIG. 9 depicts the formation of the metal pads within the vias for electrical connection to the functional element hermetically sealed within the cavity, and depicts the completed MEMS package produced by the method of FIGS. 1-9.
FIGS. 4A-9A depict an embodiment similar to FIGS. 4-9, but including the formation of an oxide layer on a surface of the silicon portion and within the recessed cavity before the metal connectors are formed, and FIG. 9A further depicts the resulting completed MEMS package.
FIGS. 10 and 10A depict embodiments of the present invention including a passivation layer.
FIGS. 11 and 11A depict embodiments of the present invention including a single wire bond pad connecting a hermetically sealed functional element to a metal lead in another cavity.
FIG. 12 is a flow chart for methods of the present invention.
DETAILED DESCRIPTION
The method of the present invention uses an SOI wafer as wafer-level packaging material, and puts electrical feed-throughs through the SOI wafer. The processing is simple, no high temperature steps are required, and the resulting die is small and thin, and does not require complex packaging to achieve cavity hermeticity. The method will be described with reference to FIGS. 1-9, which schematically depict the method by which a MEMS device is packaged according to the present invention. As depicted in FIG. 1, a first substrate 10 is provided. This wafer or substrate 10 may be any silicon or non-silicon wafer, such as a Pyrex glass wafer. As depicted in FIG. 2, the functional element 12 is formed on the surface 11 of the first substrate 10. The term “functional element” refers to the microelectromechanical device, which may for example be a circuit, sensor or actuator. The method for forming the functional element 12 on the first substrate 10 may be by any method known to one skilled in the art. Once formed, the functional element 12 will have a thickness t1. At least two metal leads 14 are formed on the surface 11 of the first substrate 10, at least one of those metal leads 14 being connected to the functional element 12. In one embodiment of the present invention, shown in FIG. 2, two metal leads 14 are formed and connected to the functional element 12. It should be understood by those skilled in the art that a typical semiconductor device includes a plurality of functional elements 12, each having electrical connections in and out of the functional element 12. The metal leads 14 generally comprise a soft metal, for example aluminum, gold, aluminum alloys, or gold alloys. When formed, the metal leads 14 have a thickness t2.
As depicted in FIG. 3, a second substrate 20 is provided, which is a SOI wafer. SOI wafer refers to a silicon-on-insulator in which a thin oxide layer 22 is buried within the silicon substrate 24. To state another way, SOI substrate 20 comprises a first silicon portion 24 a, a second silicon portion 24 b, and a silicon oxide layer 22 therebetween. SOI wafers are well known in the art of semiconductor devices.
As depicted in FIG. 4, a recessed cavity 26 is formed in the first silicon portion 24 a of the second SOI substrate 20. Any known method for material removal may be used in the method of the present invention to form the recessed cavity 26. For example, the recessed cavity 26 may be formed by reactive ion etching (RIE), which may use for example a dry plasma of SF6. By way of further example, wet chemical etching may be used, for example using KOH. The recessed cavity 26 is etched to a depth d greater than the thickness t1 of the functional element 12 formed on the first substrate 10. In another embodiment of the present invention, depicted in FIG. 4A, an oxide layer 28 is grown on the non-recessed surface 25 of the first silicon portion 24 a and within the recessed cavity 26. This oxide layer 28 may be grown by any method known to those skilled in the art, such as by thermal oxidation. The oxide layer 28 provides electrical isolation between the electrical connectors. In remaining FIGS. 5-9, the device is shown without the oxide layer 28, and in FIGS. 5A-9A, the device is shown with the oxide layer 28.
As shown in FIGS. 5 and 5A, metal connectors 30 are formed in the recessed cavity 26. The metal connectors 30 are each positioned to correspond to a respective metal lead 14 formed on the first substrate 10. As with the metal leads 14, the metal connectors 30 may comprise a soft metal, such as aluminum, gold or an alloy of aluminum or gold. Advantageously, the metal connectors 30 comprise the same metal as the metal leads 14. When formed, the metal connectors 30 have a thickness t3. Referring back to FIGS. 4 and 4A, the depth d of the recessed cavity 26 should be less than the combined thickness t2+t3 of the metal leads 14 and metal connectors 30. The metal connectors 30 may be formed by any method known to those skilled in the art of semiconductor device fabrication.
FIG. 6 depicts the bonding of the second SOI substrate 20 to the first substrate 10. The non-recessed surface 25 of the SOI substrate 20 is bonded to the surface 11 of the first substrate 10. The metal leads 14 on the first substrate 10 are generally or partially aligned with the metal connectors 30 formed within the recessed cavity 26 of the second SOI substrate 20. Because the depth d of the recessed cavity 26 is less than the combined thicknesses t2 and t3 of the metal leads 14 and metal connectors 30, a metal lead 14 and respective metal connector 30 are fused together such that the resulting combined thickness is equal to the depth d of the recessed cavity 26. By virtue of the bonding of the non-recessed surface 25 of the second SOI substrate 20 to the first substrate 10, the recessed cavity 26 is hermetically sealed from the environment. A space 32 remains within the sealed recessed cavity 26 above the functional element 12 by virtue of the depth d of the recessed cavity 26 being greater than the thickness t1 of the functional element 12. The functional element 12 is thus enclosed in the hermetically sealed cavity 26 and movable therein. In the embodiment depicted in FIG. 6A, the oxide layer 28 formed on the non-recessed surface 25 of the second SOI substrate 20 is bonded to the first substrate 10. The same effect of a hermetically sealed cavity 26 is achieved in this embodiment.
In exemplary embodiments of the present invention, the bonding of the substrates 10, 20 may be by room temperature fusion bonding or anodic bonding. In room temperature fusion bonding, which is advantageously used when the first substrate 10 is a silicon-base substrate, the wafers 10, 20 are cleaned and then bonded together by applying a pressure in the range of about 800-1400 pounds. The bonded wafers are then cured at room temperature, for example, for a period of a few days. If it is desirable to accelerate the curing of the wafer bond, a low temperature annealing may be utilized, wherein the temperature is less than a temperature that would negatively effect the metal portions of the device, for example around 200° C. Alternatively, the bonding may be anodic bonding, which may be advantageously used where the first substrate 10 is a Pyrex glass or other glass substrate. Anodic bonding generally comprises applying an electrical bias in the range of about 100-1000 V, for example about 800 V to the wafers 10, 20 in contact while applying a temperature in the range of about 300-500° C.
As shown in FIGS. 7 and 7A, the second silicon portion 24 b of the second SOI substrate 20 not bonded to the first substrate 10 is removed to expose the buried oxide layer 22. The silicon may be removed by any method known to those skilled in the art, such as the RIE and wet etch methods discussed above with respect to formation of the recessed cavity 26.
As shown in FIGS. 8 and 8A, vias 34 are formed through the second SOI substrate 20 to expose the metal connectors 30 within the recessed cavity 26. The formation of the vias 34 will allow for electrical connections to be made through the SOI substrate 20 to the metal connectors 30 and metal leads 14, and thus to the functional element 12 sealed within the cavity 26, but does not break the hermetic seal and expose the functional element 12 to the environment. The vias 34 may be etched by any method known to those skilled in the art. For example, the etching of the vias 34 may include a two-step process in which one method is used to etch through the oxide layer 22 of the SOI substrate 20, and a second method is used to etch through the silicon portion 24 a of the SOI substrate 20. By way of further example, an HF-containing solution may be used to etch the oxide layer 22, and the wet chemical etching or RIE methods discussed above may be used to etch through the Si layer 24 a.
FIGS. 9 and 9A depict the patterning of metal pads 36 for forming electrical connections with the functional element 12. The wire bond pads 36 are formed within the vias 34 on the metal connectors 30 and extend over a portion of the oxide layer 22 of the second SOI substrate 20. The formation of the metal pads 36 may be by any method known to those skilled in the art, and generally includes CVD and PVD methods. By way of further example, the metal pads 36 may be aluminum with a barrier/adhesion liner or may be gold with an adhesion liner. For example, the metal pads may be Al/Ti/TiN or Au/Cr.
There is thus formed a complete MEMS package 40 in which electrical connections are made by the metal pads 36, through the metal connectors 30, through the metal leads 14 to the functional element 12, and vice versa. No complex processing nor high temperatures were required in the above-described process. Moreover, the functional element 12 is electrically connected while being hermetically sealed within the package 40.
Another embodiment of a method and resulting MEMS package 40′ of the present invention is depicted in FIGS. 10 and 10A. The MEMS package 40′ may include a passivation layer 42 formed over a portion of the wire bond metal pads 36 and over the exposed oxide portion 22 of the second SOI substrate 20. In this embodiment, vias 44 are formed above at least a portion of the wire bond metal pads 36. The passivation layer 42 provides additional contamination control for the device 40′. By way of example, the final passivation layer 42 is a plasma nitride, and may be formed by blanket PECVD using silane and ammonia. The via or pad openings 44 over the metal pads 36 may be formed by any material removal process known to those skilled in the art.
FIGS. 11 and 11A depict yet another embodiment of a method and resulting MEMS package 40″ of the present invention. In this embodiment, the functional element 12 and one metal lead 14 a and metal connector 30 a are enclosed within one recessed cavity 26 a, and a second recessed cavity 26 b is formed in the second SOI substrate 20 for a second metal lead 14 b and metal connector 30 b. Vias 34 are formed through oxide layer 22 and silicon portion 24 a to each of the metal connectors 30 a, 30 b. A wire bond pad 36 is formed in the vias 34 in the active SOI substrate 20 and over oxide layer 22 thereby using the top 23 of the oxide 22 as a temporary passage for the metal line.
FIG. 12 provides a flow chart for an exemplary embodiment of the method of the present invention. To form the non-active substrate, the first step is to provide the first substrate. The next step is to form the functional element or elements and the metal leads on the first substrate. To form the active substrate, the first step is to provide a second SOI substrate having a first silicon layer, a second silicon layer, and a buried oxide layer therebetween. The second step is to then etch a recess in the first silicon layer to form the recessed cavity. The third step is to pattern the metal connectors within that recessed cavity. An optional fourth step may include growing an oxide layer on the first silicon layer and within the recessed cavity. Having formed the first substrate with a functional element and metal leads thereon, and having formed a second SOI substrate having at least one recessed cavity in a silicon portion thereof with metal connectors therein, the two substrates may then be bonded together by generally matching the position of the metal leads to the position of the metal connectors and bonding them together as well as bonding the non-recessed surface of the first silicon layer to the first substrate. Next, the second silicon layer of the SOI substrate is then removed to expose the buried oxide layer. Vias are then etched through the oxide layer and the first silicon layer to expose the metal connectors. Metal pads are then patterned within the vias and at least partially over the oxide layer. Optionally, a final passivation layer may be formed over the metal pads and oxide layer to provide additional contamination resistance. There is thus provided a packaging method for MEMS that allows for a small footprint, small chip outline, low temperature processing, hermetic sealing of the functional element and at a low cost compared to prior techniques. temperature processing, hermetic sealing of the functional element and at a low cost compared to prior techniques.
While the present invention has been illustrated by the description of an embodiment thereof, and while the embodiment has been described in considerable detail, it is not intended to restrict or in any way limit the scope of the appended claims to such detail. Additional advantages and modifications will readily appear to those skilled in the art. The invention in its broader aspects is therefore not limited to the specific details, representative apparatus and method and illustrative examples shown and described. Accordingly, departures may be made from such details without departing from the scope or spirit of applicant's general inventive concept.

Claims (36)

What is claimed is:
1. A method for packaging a MEMS device comprising:
providing a first substrate having a functional element and metal leads thereon and a second SOI substrate having at least one recessed cavity in a first silicon portion thereof with metal connectors therein;
bonding a surface of the first substrate to a non-recessed surface of the first silicon portion of the second SOI substrate and bonding the metal leads of the first substrate to respective metal connectors of the second SOI substrate to enclose and seal the functional element of the first substrate within the recessed cavity of the second SOI substrate; and
forming metal pads on each of the metal connectors of the second SOI substrate through the second SOI substrate for feeding electrical signals to and from the functional element of the first substrate sealed in the cavity of the second SOI substrate through the metal leads, the connectors and the pads.
2. The method of claim 1 wherein the recessed cavity is provided with a depth greater than the thickness of the functional element and less than the combined thickness of the metal leads and the respective metal connectors prior to bonding.
3. The method of claim 1 wherein the second SOI substrate comprises the first silicon portion, a second silicon portion, and an intermediate oxide layer buried between the first silicon portion and second silicon portion, and the method further comprises, after bonding, removing the second silicon portion leaving the oxide layer exposed.
4. The method of claim 3 further comprising, after forming, depositing a passivation layer on the exposed oxide layer and metal pads.
5. The method of claim 4 wherein depositing the passivation layer includes plasma enhanced chemical vapor deposition with a nitrogen-containing reactant to deposit a nitride passivation layer.
6. The method of claim 1 wherein bonding comprises room temperature fusion bonding.
7. The method of claim 6 wherein the fusion bonding includes applying a pressure in the range of about 800-1400 pounds.
8. The method of claim 6 wherein the first substrate is a silicon base wafer.
9. The method of claim 1 wherein bonding comprises anodic bonding.
10. The method of claim 9 wherein the anodic bonding comprises applying an electrical bias in the range of about 100-1000 V and a temperature in the range of about 300-500° C.
11. The method of claim 9 wherein the first substrate is a Pyrex glass base wafer.
12. The method of claim 1 wherein the metal leads and the metal connectors each comprise a metal selected from the group consisting of: aluminum, gold, aluminum alloys and gold alloys.
13. The method of claim 12 wherein the metal leads and connectors comprise the same metal.
14. The method of claim 1 wherein the forming metal pads comprises depositing aluminum on a titanium/titanium nitride liner.
15. The method of claim 1 wherein the forming metal pads comprises depositing gold on a chromium liner.
16. The method of claim 1 wherein the second SOI substrate comprises a plurality of recessed cavities each having at least one metal connector therein, the functional element being enclosed and sealed within one of the plurality of cavities, and the metal pads on each of the metal connectors connecting over the second SOI substrate.
17. The method of claim 16 further comprising forming a plurality of functional elements, each enclosed and sealed within one of the plurality of cavities.
18. The method of claim 1 further comprising, before bonding, growing an oxide on the non-recessed surface and in the recessed cavity of the first silicon portion, and thereafter bonding the surface of the first substrate to the oxide on the non-recessed surface of the first silicon portion.
19. The method of claim 1 wherein the functional element is connected to two metal leads within the recessed cavity.
20. A method for packaging a MEMS device comprising:
providing a first substrate and a second substrate, the second substrate comprising an SOI wafer having a first silicon portion, a second silicon portion and an oxide portion therebetween;
forming a functional element on a surface of the first substrate;
forming at least two metal leads on the surface of the first substrate, wherein at least one of the metal leads connects to the functional element;
etching at least one recessed cavity in the first silicon portion of the second substrate;
forming at least two metal connectors in the at least one recessed cavity for connecting to a respective metal lead on the surface of the first substrate wherein the recessed cavity is etched to a depth greater than the thickness of the functional element and less than the combined thickness of the metal connectors and respective metal leads;
bonding the surface of the first substrate to a non-recessed surface of the first silicon portion and bonding each metal connector to the respective metal lead thereby sealing the functional element in the at least one recessed cavity;
removing the second silicon portion of the second substrate thereby exposing the oxide portion;
etching a via through the oxide portion and the first silicon portion over each metal connector to expose at least a portion of each metal connector; and
forming a metal pad on the exposed portion of each metal connector in the via.
21. The method of claim 20 further comprising, after forming the metal pads, depositing a passivation layer on the exposed oxide portion and metal pads.
22. The method of claim 21 wherein depositing the passivation layer includes plasma enhanced chemical vapor deposition with a nitrogen-containing reactant to deposit a nitride passivation layer.
23. The method of claim 20 wherein bonding comprises room temperature fusion bonding.
24. The method of claim 23 wherein the fusion bonding includes applying a pressure in the range of about 800-1400 pounds.
25. The method of claim 23 wherein the first substrate is a silicon base wafer.
26. The method of claim 20 wherein bonding comprises anodic bonding.
27. The method of claim 26 wherein the anodic bonding comprises applying an electrical bias in the range of about 100-1000 V and a temperature in the range of about 300-500° C.
28. The method of claim 26 wherein the first substrate is a Pyrex glass base wafer.
29. The method of claim 20 wherein the metal leads and the metal connectors each comprise a metal selected from the group consisting of: aluminum, gold, aluminum alloys and gold alloys.
30. The method of claim 29 wherein the metal leads and connectors comprise the same metal.
31. The method of claim 20 wherein the forming metal pads comprises depositing aluminum on a titanium/titanium nitride liner.
32. The method of claim 20 wherein the forming metal pads comprises depositing gold on a chromium liner.
33. The method of claim 20 wherein the SOI wafer comprises a plurality of recessed cavities in the first silicon portion, each having at least one metal connector therein for bonding to a respective metal lead, the functional element and connected metal lead bonded to the respective metal connector being enclosed and sealed within one of the plurality of cavities, and the metal pads on each of the metal connectors connecting over the oxide portion of the SOI wafer to electrically connect the functional element within one cavity to the metal lead in another cavity.
34. The method of claim 33 further comprising forming a plurality of functional elements, each enclosed and sealed within one of the plurality of cavities.
35. The method of claim 20 further comprising, before bonding, growing an oxide on the non-recessed surface and in the recessed cavity of the first silicon portion, and thereafter bonding the surface of the first substrate to the oxide on the non-recessed surface of the first silicon portion.
36. The method of claim 20 wherein the functional element is connected to each of the at least two metal leads.
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Cited By (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030071283A1 (en) * 2001-10-17 2003-04-17 Hymite A/S Semiconductor structure with one or more through-holes
US20040058476A1 (en) * 2002-09-25 2004-03-25 Ziptronix Wafer bonding hermetic encapsulation
US20040251524A1 (en) * 2003-06-13 2004-12-16 Snyder Tanya Jegeris Wafer bonding using reactive foils for massively parallel micro-electromechanical systems packaging
US20050081958A1 (en) * 2002-10-22 2005-04-21 Sumitomo Mitsubishi Silicon Corporation Pasted soi substrate, process for producing the same and semiconductor device
US20050110157A1 (en) * 2003-09-15 2005-05-26 Rohm And Haas Electronic Materials, L.L.C. Device package and method for the fabrication and testing thereof
US20050161795A1 (en) * 2003-02-07 2005-07-28 Ziptronix Room temperature metal direct bonding
US20050170656A1 (en) * 2003-10-20 2005-08-04 Nasiri Steven S. Vertical integration of a MEMS structure with electronics in a hermetically sealed cavity
US20050166677A1 (en) * 2004-02-02 2005-08-04 Nasiri Steven S. Vertically integrated MEMS structure with electronics in a hermetically sealed cavity
US20050184304A1 (en) * 2004-02-25 2005-08-25 Gupta Pavan O. Large cavity wafer-level package for MEMS
US20050241135A1 (en) * 2004-04-28 2005-11-03 Matthias Heschel Techniques for providing a structure with through-holes that may be used in a sub-assembly for micro components
US20060001114A1 (en) * 2004-06-30 2006-01-05 Jen-Yi Chen Apparatus and method of wafer level package
US20060016547A1 (en) * 2004-07-22 2006-01-26 Chien-Hua Chen System and method for transferring structured material to a substrate
US20060055048A1 (en) * 2004-09-13 2006-03-16 General Electric Company Method of wet etching vias and articles formed thereby
US20060192272A1 (en) * 2005-02-25 2006-08-31 Rogier Receveur Wafer level hermetically sealed MEMS device
US7109635B1 (en) 2003-06-11 2006-09-19 Sawtek, Inc. Wafer level packaging of materials with different coefficients of thermal expansion
US20060211233A1 (en) * 2005-03-21 2006-09-21 Skyworks Solutions, Inc. Method for fabricating a wafer level package having through wafer vias for external package connectivity and related structure
US20060208326A1 (en) * 2005-03-18 2006-09-21 Nasiri Steven S Method of fabrication of ai/ge bonding in a wafer packaging environment and a product produced therefrom
US20060216846A1 (en) * 2005-03-23 2006-09-28 Hideo Oi Method of forming a microelectronic device
US20060223299A1 (en) * 2005-03-29 2006-10-05 Wen-Heng Hu Fabricating process of an electrically conductive structure on a circuit board
US20060228831A1 (en) * 2005-03-29 2006-10-12 Nasiri Steven S Method and system of releasing a MEMS structure
US20060237810A1 (en) * 2005-04-21 2006-10-26 Kirby Sand Bonding interface for micro-device packaging
KR100643769B1 (en) 2005-07-15 2006-11-10 삼성전자주식회사 Preparation method for a cap wafer using a soi wafer, fabricating mathod for a semiconductor chip using the cap wafer and the semiconductor chip fabricated by the same method
US7230512B1 (en) 2003-08-19 2007-06-12 Triquint, Inc. Wafer-level surface acoustic wave filter package with temperature-compensating characteristics
US20070243662A1 (en) * 2006-03-17 2007-10-18 Johnson Donald W Packaging of MEMS devices
US20080003761A1 (en) * 2005-04-01 2008-01-03 Skyworks Solutions, Inc. Method for fabricating a wafer level package with device wafer and passive component integration
US20080102556A1 (en) * 2006-11-01 2008-05-01 Han-Choon Lee Method of manufacturing complementary metal oxide semiconductor image sensor
US20080217708A1 (en) * 2007-03-09 2008-09-11 Skyworks Solutions, Inc. Integrated passive cap in a system-in-package
US20090075431A1 (en) * 2006-08-02 2009-03-19 Skyworks Solutions, Inc. Wafer level package with cavities for active devices
US20090079059A1 (en) * 2007-09-24 2009-03-26 Research Triangle Institute Integrated semiconductor substrate structure using incompatible processes
WO2009111874A1 (en) * 2008-03-11 2009-09-17 The Royal Institution For The Advancement Of Learning/ Mcgiil University Low-temperature wafer level processing for mems devices
US20100187665A1 (en) * 2009-01-26 2010-07-29 Sixis, Inc. Integral metal structure with conductive post portions
US20100200540A1 (en) * 2007-09-25 2010-08-12 Sixis, Inc. Large substrate structural vias
US20100229651A1 (en) * 2009-03-16 2010-09-16 Kavlico Corporation Cointegrated mems sensor and method
US20100244161A1 (en) * 2007-11-30 2010-09-30 Skyworks Solutions, Inc. Wafer level packaging using flip chip mounting
US20100283144A1 (en) * 2007-12-26 2010-11-11 Steve Xin Liang In-situ cavity circuit package
US20100306993A1 (en) * 2007-11-20 2010-12-09 Board Of Regents, The University Of Texas System Method and Apparatus for Detethering Mesoscale, Microscale, and Nanoscale Components and Devices
US20100311209A1 (en) * 2009-06-05 2010-12-09 Jiangsu Lexvu Electronics Co., Ltd. Method o encapsulating a wafer level microdevice
US8347717B2 (en) 2009-09-11 2013-01-08 Invensense, Inc. Extension-mode angular velocity sensor
CN103199055A (en) * 2012-01-06 2013-07-10 台湾积体电路制造股份有限公司 Packages and method of forming the same
US8546240B2 (en) 2011-11-11 2013-10-01 International Business Machines Corporation Methods of manufacturing integrated semiconductor devices with single crystalline beam
US8567246B2 (en) 2010-10-12 2013-10-29 Invensense, Inc. Integrated MEMS device and method of use
US8629036B2 (en) 2011-11-11 2014-01-14 International Business Machines Corporation Integrated semiconductor devices with amorphous silicon beam, methods of manufacture and design structure
US8860409B2 (en) 2011-01-11 2014-10-14 Invensense, Inc. Micromachined resonant magnetic field sensors
US8896324B2 (en) 2003-09-16 2014-11-25 Cardiomems, Inc. System, apparatus, and method for in-vivo assessment of relative position of an implant
US8947081B2 (en) 2011-01-11 2015-02-03 Invensense, Inc. Micromachined resonant magnetic field sensors
US9052445B2 (en) 2011-10-19 2015-06-09 Cisco Technology, Inc. Molded glass lid for wafer level packaging of opto-electronic assemblies
US9078563B2 (en) 2005-06-21 2015-07-14 St. Jude Medical Luxembourg Holdings II S.à.r.l. Method of manufacturing implantable wireless sensor for in vivo pressure measurement
US9097524B2 (en) 2009-09-11 2015-08-04 Invensense, Inc. MEMS device with improved spring system
US9105751B2 (en) 2011-11-11 2015-08-11 International Business Machines Corporation Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure
US9212051B1 (en) 2011-08-04 2015-12-15 Western Digital (Fremont), Llc Systems and methods for forming MEMS assemblies incorporating getters
US9265428B2 (en) 2003-09-16 2016-02-23 St. Jude Medical Luxembourg Holdings Ii S.A.R.L. (“Sjm Lux Ii”) Implantable wireless sensor
US9664750B2 (en) 2011-01-11 2017-05-30 Invensense, Inc. In-plane sensing Lorentz force magnetometer
US9716033B2 (en) 2005-08-11 2017-07-25 Ziptronix, Inc. 3D IC method and device
US9754922B2 (en) 2015-02-11 2017-09-05 Invensense, Inc. 3D integration using Al—Ge eutectic bond interconnect
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US10192850B1 (en) 2016-09-19 2019-01-29 Sitime Corporation Bonding process with inhibited oxide formation
US10319654B1 (en) 2017-12-01 2019-06-11 Cubic Corporation Integrated chip scale packages
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11244920B2 (en) 2018-12-18 2022-02-08 Invensas Bonding Technologies, Inc. Method and structures for low temperature device bonding
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
US11515279B2 (en) 2018-04-11 2022-11-29 Adeia Semiconductor Bonding Technologies Inc. Low temperature bonded structures
US11710718B2 (en) 2015-07-10 2023-07-25 Adeia Semiconductor Technologies Llc Structures and methods for low temperature bonding using nanoparticles
US11728313B2 (en) 2018-06-13 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Offset pads over TSV
US11735523B2 (en) 2020-05-19 2023-08-22 Adeia Semiconductor Bonding Technologies Inc. Laterally unconfined structure
US11804377B2 (en) 2018-04-05 2023-10-31 Adeia Semiconductor Bonding Technologies, Inc. Method for preparing a surface for direct-bonding
US11894326B2 (en) 2017-03-17 2024-02-06 Adeia Semiconductor Bonding Technologies Inc. Multi-metal contact structure
US11908739B2 (en) 2017-06-05 2024-02-20 Adeia Semiconductor Technologies Llc Flat metal features for microelectronics applications
US11929347B2 (en) 2022-01-19 2024-03-12 Adeia Semiconductor Technologies Llc Mixed exposure for large die

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030057544A1 (en) * 2001-09-13 2003-03-27 Nathan Richard J. Integrated assembly protocol
US20030059976A1 (en) * 2001-09-24 2003-03-27 Nathan Richard J. Integrated package and methods for making same
US20030153119A1 (en) * 2002-02-14 2003-08-14 Nathan Richard J. Integrated circuit package and method for fabrication
US7045459B2 (en) * 2002-02-19 2006-05-16 Northrop Grumman Corporation Thin film encapsulation of MEMS devices
KR100594716B1 (en) * 2004-07-27 2006-06-30 삼성전자주식회사 Cap wafer comprising cavity, semiconductor chip comprising the cap wafer, and method thereof
AU2005304912A1 (en) 2004-11-04 2006-05-18 Smith & Nephew, Inc. Cycle and load measurement device
US7662653B2 (en) * 2005-02-10 2010-02-16 Cardiomems, Inc. Method of manufacturing a hermetic chamber with electrical feedthroughs
US7647836B2 (en) * 2005-02-10 2010-01-19 Cardiomems, Inc. Hermetic chamber with electrical feedthroughs
US7527997B2 (en) * 2005-04-08 2009-05-05 The Research Foundation Of State University Of New York MEMS structure with anodically bonded silicon-on-insulator substrate
US7337671B2 (en) 2005-06-03 2008-03-04 Georgia Tech Research Corp. Capacitive microaccelerometers and fabrication methods
US7160751B2 (en) * 2005-06-13 2007-01-09 Delphi Technologies, Inc. Method of making a SOI silicon structure
US7588992B2 (en) * 2005-06-14 2009-09-15 Intel Corporation Integrated thin-film capacitor with etch-stop layer, process of making same, and packages containing same
US7621036B2 (en) * 2005-06-21 2009-11-24 Cardiomems, Inc. Method of manufacturing implantable wireless sensor for in vivo pressure measurement
US20060289976A1 (en) * 2005-06-23 2006-12-28 Intel Corporation Pre-patterned thin film capacitor and method for embedding same in a package substrate
KR100629498B1 (en) 2005-07-15 2006-09-28 삼성전자주식회사 The micro package, multi-stack micro package and the method of manufacturing thereof
US8217473B2 (en) * 2005-07-29 2012-07-10 Hewlett-Packard Development Company, L.P. Micro electro-mechanical system packaging and interconnect
CN103637840A (en) 2005-08-23 2014-03-19 史密夫和内修有限公司 Telemetric orthopaedic implant
KR100692520B1 (en) 2005-10-19 2007-03-09 삼성전자주식회사 Wafer level packaging cap and fablication method thereof
KR100662848B1 (en) * 2005-12-20 2007-01-02 삼성전자주식회사 Inductor integrated chip and fabrication method thereof
KR100785014B1 (en) * 2006-04-14 2007-12-12 삼성전자주식회사 Micro-electro mechanical system device using silicon on insulator wafer and method of manufacturing the same
US7578189B1 (en) 2006-05-10 2009-08-25 Qualtre, Inc. Three-axis accelerometers
US7425465B2 (en) * 2006-05-15 2008-09-16 Fujifilm Diamatix, Inc. Method of fabricating a multi-post structures on a substrate
EP2275793A1 (en) * 2006-05-23 2011-01-19 Sensirion Holding AG A pressure sensor having a chamber and a method for fabricating the same
EP1860418A1 (en) * 2006-05-23 2007-11-28 Sensirion AG A method for fabricating a pressure sensor using SOI wafers
US7767484B2 (en) * 2006-05-31 2010-08-03 Georgia Tech Research Corporation Method for sealing and backside releasing of microelectromechanical systems
WO2008057055A1 (en) * 2006-11-10 2008-05-15 Agency For Science, Technology And Research A micromechanical structure and a method of fabricating a micromechanical structure
US9445720B2 (en) 2007-02-23 2016-09-20 Smith & Nephew, Inc. Processing sensed accelerometer data for determination of bone healing
AU2008296209B2 (en) 2007-09-06 2014-05-29 Smith & Nephew, Inc. System and method for communicating with a telemetric implant
CA2712893C (en) * 2008-02-01 2017-02-28 Smith & Nephew, Inc. System and method for communicating with an implant
WO2009130681A2 (en) * 2008-04-23 2009-10-29 Nxp B.V. Semiconductor device and method of manufacturing a semiconductor device
EP2159558A1 (en) * 2008-08-28 2010-03-03 Sensirion AG A method for manufacturing an integrated pressure sensor
US7955885B1 (en) * 2009-01-09 2011-06-07 Integrated Device Technology, Inc. Methods of forming packaged micro-electromechanical devices
WO2010088531A2 (en) 2009-01-29 2010-08-05 Smith & Nephew, Inc. Low temperature encapsulate welding
DE102009036033B4 (en) 2009-08-04 2012-11-15 Austriamicrosystems Ag Through-hole for semiconductor wafers and manufacturing process
US20140306327A1 (en) 2013-04-13 2014-10-16 Infineon Technologies Ag Semiconductor device and method of manufacturing thereof
EP3019442A4 (en) 2013-07-08 2017-01-25 Motion Engine Inc. Mems device and method of manufacturing
WO2015042700A1 (en) 2013-09-24 2015-04-02 Motion Engine Inc. Mems components and method of wafer-level manufacturing thereof
WO2015013827A1 (en) 2013-08-02 2015-02-05 Motion Engine Inc. Mems motion sensor for sub-resonance angular rate sensing
US10464836B2 (en) 2013-10-10 2019-11-05 Medtronic, Inc. Hermetic conductive feedthroughs for a semiconductor wafer
EP2871456B1 (en) 2013-11-06 2018-10-10 Invensense, Inc. Pressure sensor and method for manufacturing a pressure sensor
EP2871455B1 (en) 2013-11-06 2020-03-04 Invensense, Inc. Pressure sensor
WO2015103688A1 (en) 2014-01-09 2015-07-16 Motion Engine Inc. Integrated mems system
JP6331551B2 (en) * 2014-03-25 2018-05-30 セイコーエプソン株式会社 MEMS device
US20170030788A1 (en) 2014-04-10 2017-02-02 Motion Engine Inc. Mems pressure sensor
US11674803B2 (en) 2014-06-02 2023-06-13 Motion Engine, Inc. Multi-mass MEMS motion sensor
CA3004760A1 (en) 2014-12-09 2016-06-16 Motion Engine Inc. 3d mems magnetometer and associated methods
US10407299B2 (en) 2015-01-15 2019-09-10 Motion Engine Inc. 3D MEMS device with hermetic cavity
EP3076146B1 (en) 2015-04-02 2020-05-06 Invensense, Inc. Pressure sensor
US11225409B2 (en) 2018-09-17 2022-01-18 Invensense, Inc. Sensor with integrated heater
CN113785178A (en) 2019-05-17 2021-12-10 应美盛股份有限公司 Pressure sensor with improved gas tightness
US11180366B2 (en) 2020-03-23 2021-11-23 General Electric Company Methods for forming a MEMS device layer on an active device layer and devices formed thereby

Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5278368A (en) * 1991-06-24 1994-01-11 Matsushita Elec. Works, Ltd Electrostatic relay
US5929498A (en) 1997-07-18 1999-07-27 Kavlico Corporation Fusion-bond electrical feed-through
US6124636A (en) * 1998-01-26 2000-09-26 Nec Corporation MMIC package
US6326682B1 (en) * 1998-12-21 2001-12-04 Kulite Semiconductor Products Hermetically sealed transducer and methods for producing the same
US6369931B1 (en) * 1997-12-22 2002-04-09 Robert Bosch Gmbh Method for manufacturing a micromechanical device
US6436853B2 (en) * 1998-12-03 2002-08-20 University Of Michigan Microstructures
US6448109B1 (en) * 2000-11-15 2002-09-10 Analog Devices, Inc. Wafer level method of capping multiple MEMS elements
US6452238B1 (en) * 1999-10-04 2002-09-17 Texas Instruments Incorporated MEMS wafer level package
US6469909B2 (en) * 2001-01-09 2002-10-22 3M Innovative Properties Company MEMS package with flexible circuit interconnect
US6486425B2 (en) * 1998-11-26 2002-11-26 Omron Corporation Electrostatic microrelay
US6503831B2 (en) * 1997-10-14 2003-01-07 Patterning Technologies Limited Method of forming an electronic device
US6506620B1 (en) * 2000-11-27 2003-01-14 Microscan Systems Incorporated Process for manufacturing micromechanical and microoptomechanical structures with backside metalization
US6519075B2 (en) * 2000-11-03 2003-02-11 Agere Systems Inc. Packaged MEMS device and method for making the same
US6528869B1 (en) * 2001-04-06 2003-03-04 Amkor Technology, Inc. Semiconductor package with molded substrate and recessed input/output terminals
US6528351B1 (en) * 2001-09-24 2003-03-04 Jigsaw Tek, Inc. Integrated package and methods for making same
US6548895B1 (en) * 2001-02-21 2003-04-15 Sandia Corporation Packaging of electro-microfluidic devices
US6555417B2 (en) * 2000-12-05 2003-04-29 Analog Devices, Inc. Method and device for protecting micro electromechanical system structures during dicing of a wafer
US6590267B1 (en) * 2000-09-14 2003-07-08 Mcnc Microelectromechanical flexible membrane electrostatic valve device and related fabrication methods

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6780672B2 (en) * 2000-01-31 2004-08-24 Lockheed Martin Corporation Micro eletro-mechanical component and system architecture
US6384473B1 (en) * 2000-05-16 2002-05-07 Sandia Corporation Microelectronic device package with an integral window
US6661084B1 (en) * 2000-05-16 2003-12-09 Sandia Corporation Single level microelectronic device package with an integral window
US6569754B2 (en) * 2000-08-24 2003-05-27 The Regents Of The University Of Michigan Method for making a module including a microplatform
US6574026B2 (en) * 2000-12-07 2003-06-03 Agere Systems Inc. Magnetically-packaged optical MEMs device
US6773962B2 (en) * 2001-03-15 2004-08-10 General Electric Company Microelectromechanical system device packaging method
US6771859B2 (en) * 2001-07-24 2004-08-03 3M Innovative Properties Company Self-aligning optical micro-mechanical device package
US6624003B1 (en) * 2002-02-06 2003-09-23 Teravicta Technologies, Inc. Integrated MEMS device and package

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5278368A (en) * 1991-06-24 1994-01-11 Matsushita Elec. Works, Ltd Electrostatic relay
US5929498A (en) 1997-07-18 1999-07-27 Kavlico Corporation Fusion-bond electrical feed-through
US6503831B2 (en) * 1997-10-14 2003-01-07 Patterning Technologies Limited Method of forming an electronic device
US6369931B1 (en) * 1997-12-22 2002-04-09 Robert Bosch Gmbh Method for manufacturing a micromechanical device
US6124636A (en) * 1998-01-26 2000-09-26 Nec Corporation MMIC package
US6486425B2 (en) * 1998-11-26 2002-11-26 Omron Corporation Electrostatic microrelay
US6436853B2 (en) * 1998-12-03 2002-08-20 University Of Michigan Microstructures
US6326682B1 (en) * 1998-12-21 2001-12-04 Kulite Semiconductor Products Hermetically sealed transducer and methods for producing the same
US6452238B1 (en) * 1999-10-04 2002-09-17 Texas Instruments Incorporated MEMS wafer level package
US6590267B1 (en) * 2000-09-14 2003-07-08 Mcnc Microelectromechanical flexible membrane electrostatic valve device and related fabrication methods
US6519075B2 (en) * 2000-11-03 2003-02-11 Agere Systems Inc. Packaged MEMS device and method for making the same
US6448109B1 (en) * 2000-11-15 2002-09-10 Analog Devices, Inc. Wafer level method of capping multiple MEMS elements
US6506620B1 (en) * 2000-11-27 2003-01-14 Microscan Systems Incorporated Process for manufacturing micromechanical and microoptomechanical structures with backside metalization
US6555417B2 (en) * 2000-12-05 2003-04-29 Analog Devices, Inc. Method and device for protecting micro electromechanical system structures during dicing of a wafer
US6469909B2 (en) * 2001-01-09 2002-10-22 3M Innovative Properties Company MEMS package with flexible circuit interconnect
US6548895B1 (en) * 2001-02-21 2003-04-15 Sandia Corporation Packaging of electro-microfluidic devices
US6528869B1 (en) * 2001-04-06 2003-03-04 Amkor Technology, Inc. Semiconductor package with molded substrate and recessed input/output terminals
US6528351B1 (en) * 2001-09-24 2003-03-04 Jigsaw Tek, Inc. Integrated package and methods for making same

Cited By (170)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050059204A1 (en) * 2001-10-17 2005-03-17 Hymite A/S, A Kgs, Lyngby, Denmark Corporation Semiconductor structure with one or more through-holes
US7081412B2 (en) 2001-10-17 2006-07-25 Hymite A/S Double-sided etching technique for semiconductor structure with through-holes
US6818464B2 (en) 2001-10-17 2004-11-16 Hymite A/S Double-sided etching technique for providing a semiconductor structure with through-holes, and a feed-through metalization process for sealing the through-holes
US7057274B2 (en) 2001-10-17 2006-06-06 Hymite A/S Semiconductor structures having through-holes sealed with feed-through metalization
US20030071283A1 (en) * 2001-10-17 2003-04-17 Hymite A/S Semiconductor structure with one or more through-holes
US20040266038A1 (en) * 2001-10-17 2004-12-30 Hymite A/S, A Kgs. Lyngby, Denmark Corporation Semiconductor structures having through-holes sealed with feed-through metalization
US20050009246A1 (en) * 2002-09-25 2005-01-13 Ziptronix, Inc. Wafer bonding hermetic encapsulation
US7622324B2 (en) 2002-09-25 2009-11-24 Ziptronix Wafer bonding hermetic encapsulation
US20040058476A1 (en) * 2002-09-25 2004-03-25 Ziptronix Wafer bonding hermetic encapsulation
US6822326B2 (en) * 2002-09-25 2004-11-23 Ziptronix Wafer bonding hermetic encapsulation
US20050081958A1 (en) * 2002-10-22 2005-04-21 Sumitomo Mitsubishi Silicon Corporation Pasted soi substrate, process for producing the same and semiconductor device
US7253082B2 (en) * 2002-10-22 2007-08-07 Sumitomo Mitsubishi Silicon Corporation Pasted SOI substrate, process for producing the same and semiconductor device
US7842540B2 (en) 2003-02-07 2010-11-30 Ziptronix, Inc. Room temperature metal direct bonding
US20050161795A1 (en) * 2003-02-07 2005-07-28 Ziptronix Room temperature metal direct bonding
US8846450B2 (en) 2003-02-07 2014-09-30 Ziptronix, Inc. Room temperature metal direct bonding
US7602070B2 (en) 2003-02-07 2009-10-13 Ziptronix, Inc. Room temperature metal direct bonding
US9385024B2 (en) 2003-02-07 2016-07-05 Ziptronix, Inc. Room temperature metal direct bonding
US10141218B2 (en) 2003-02-07 2018-11-27 Invensas Bonding Technologies, Inc. Room temperature metal direct bonding
US20110041329A1 (en) * 2003-02-07 2011-02-24 Ziptronix, Inc. Room temperature metal direct bonding
US20070232023A1 (en) * 2003-02-07 2007-10-04 Ziptronix, Inc. Room temperature metal direct bonding
US8524533B2 (en) 2003-02-07 2013-09-03 Ziptronix, Inc. Room temperature metal direct bonding
US7635636B2 (en) 2003-06-11 2009-12-22 Triquint Semiconductor, Inc. Wafer level packaging of materials with different coefficients of thermal expansion
US7109635B1 (en) 2003-06-11 2006-09-19 Sawtek, Inc. Wafer level packaging of materials with different coefficients of thermal expansion
US20060263931A1 (en) * 2003-06-11 2006-11-23 Mcclure Michael T Wafer Level Packaging of Materials with Different Coefficents of Thermal Expansion
US20040251524A1 (en) * 2003-06-13 2004-12-16 Snyder Tanya Jegeris Wafer bonding using reactive foils for massively parallel micro-electromechanical systems packaging
US7176106B2 (en) * 2003-06-13 2007-02-13 Avago Technologies Fiber Ip (Singapore) Pte. Ltd. Wafer bonding using reactive foils for massively parallel micro-electromechanical systems packaging
US7230512B1 (en) 2003-08-19 2007-06-12 Triquint, Inc. Wafer-level surface acoustic wave filter package with temperature-compensating characteristics
US7449784B2 (en) 2003-09-15 2008-11-11 Nuvotronics, Llc Device package and methods for the fabrication and testing thereof
US20050111797A1 (en) * 2003-09-15 2005-05-26 Rohm And Haas Electronic Materials, L.L.C. Device package and methods for the fabrication and testing thereof
US7888793B2 (en) 2003-09-15 2011-02-15 Nuvotronics, Llc Device package and methods for the fabrication and testing thereof
US20050110157A1 (en) * 2003-09-15 2005-05-26 Rohm And Haas Electronic Materials, L.L.C. Device package and method for the fabrication and testing thereof
US7129163B2 (en) 2003-09-15 2006-10-31 Rohm And Haas Electronic Materials Llc Device package and method for the fabrication and testing thereof
US9817199B2 (en) 2003-09-15 2017-11-14 Nuvotronics, Inc Device package and methods for the fabrication and testing thereof
US20110079893A1 (en) * 2003-09-15 2011-04-07 Sherrer David W Device package and methods for the fabrication and testing thereof
US7329056B2 (en) 2003-09-15 2008-02-12 Rohm And Haas Electronic Materials Llc Device package and methods for the fabrication and testing thereof
US8703603B2 (en) 2003-09-15 2014-04-22 Nuvotronics, Llc Device package and methods for the fabrication and testing thereof
US9647420B2 (en) 2003-09-15 2017-05-09 Nuvotronics, Inc. Package and methods for the fabrication and testing thereof
US20070164419A1 (en) * 2003-09-15 2007-07-19 Rohm And Haas Electronic Materials Llc Device package and methods for the fabrication and testing thereof
US8993450B2 (en) 2003-09-15 2015-03-31 Nuvotronics, Llc Device package and methods for the fabrication and testing thereof
US9410799B2 (en) 2003-09-15 2016-08-09 Nuvotronics, Inc. Device package and methods for the fabrication and testing thereof
US9265428B2 (en) 2003-09-16 2016-02-23 St. Jude Medical Luxembourg Holdings Ii S.A.R.L. (“Sjm Lux Ii”) Implantable wireless sensor
US8896324B2 (en) 2003-09-16 2014-11-25 Cardiomems, Inc. System, apparatus, and method for in-vivo assessment of relative position of an implant
US7247246B2 (en) 2003-10-20 2007-07-24 Atmel Corporation Vertical integration of a MEMS structure with electronics in a hermetically sealed cavity
US20050170656A1 (en) * 2003-10-20 2005-08-04 Nasiri Steven S. Vertical integration of a MEMS structure with electronics in a hermetically sealed cavity
US20050166677A1 (en) * 2004-02-02 2005-08-04 Nasiri Steven S. Vertically integrated MEMS structure with electronics in a hermetically sealed cavity
US7104129B2 (en) 2004-02-02 2006-09-12 Invensense Inc. Vertically integrated MEMS structure with electronics in a hermetically sealed cavity
US20050184304A1 (en) * 2004-02-25 2005-08-25 Gupta Pavan O. Large cavity wafer-level package for MEMS
US7681306B2 (en) 2004-04-28 2010-03-23 Hymite A/S Method of forming an assembly to house one or more micro components
US20050241135A1 (en) * 2004-04-28 2005-11-03 Matthias Heschel Techniques for providing a structure with through-holes that may be used in a sub-assembly for micro components
US20060001114A1 (en) * 2004-06-30 2006-01-05 Jen-Yi Chen Apparatus and method of wafer level package
US20060016547A1 (en) * 2004-07-22 2006-01-26 Chien-Hua Chen System and method for transferring structured material to a substrate
US20070068620A1 (en) * 2004-07-22 2007-03-29 Chien-Hua Chen System and method for transferring structured material to a substrate
US7101789B2 (en) 2004-09-13 2006-09-05 General Electric Company Method of wet etching vias and articles formed thereby
US20060055048A1 (en) * 2004-09-13 2006-03-16 General Electric Company Method of wet etching vias and articles formed thereby
US7816745B2 (en) 2005-02-25 2010-10-19 Medtronic, Inc. Wafer level hermetically sealed MEMS device
US20110072646A1 (en) * 2005-02-25 2011-03-31 Medtronic, Inc. Wafer level hermetically sealed mems device
US20060192272A1 (en) * 2005-02-25 2006-08-31 Rogier Receveur Wafer level hermetically sealed MEMS device
US9751752B2 (en) 2005-03-18 2017-09-05 Invensense, Inc. Method of fabrication of Al/Ge bonding in a wafer packaging environment and a product produced therefrom
US9139428B2 (en) 2005-03-18 2015-09-22 Invensense, Inc. Method of fabrication of Al/Ge bonding in a wafer packaging environment and a product produced therefrom
US7442570B2 (en) 2005-03-18 2008-10-28 Invensence Inc. Method of fabrication of a AL/GE bonding in a wafer packaging environment and a product produced therefrom
US20060208326A1 (en) * 2005-03-18 2006-09-21 Nasiri Steven S Method of fabrication of ai/ge bonding in a wafer packaging environment and a product produced therefrom
US20080283990A1 (en) * 2005-03-18 2008-11-20 Invensense Inc. Method of fabrication of ai/ge bonding in a wafer packaging environment and a product produced therefrom
US8633049B2 (en) 2005-03-18 2014-01-21 Invensense, Inc. Method of fabrication of Al/GE bonding in a wafer packaging environment and a product produced therefrom
US8084332B2 (en) 2005-03-18 2011-12-27 Invensense, Inc. Method of fabrication of AI/GE bonding in a wafer packaging environment and a product produced therefrom
US20060211233A1 (en) * 2005-03-21 2006-09-21 Skyworks Solutions, Inc. Method for fabricating a wafer level package having through wafer vias for external package connectivity and related structure
US20080064142A1 (en) * 2005-03-21 2008-03-13 Skyworks Solutions, Inc. Method for fabricating a wafer level package having through wafer vias for external package connectivity
US7323355B2 (en) * 2005-03-23 2008-01-29 Freescale Semiconductor, Inc. Method of forming a microelectronic device
US20060216846A1 (en) * 2005-03-23 2006-09-28 Hideo Oi Method of forming a microelectronic device
US20060223299A1 (en) * 2005-03-29 2006-10-05 Wen-Heng Hu Fabricating process of an electrically conductive structure on a circuit board
US7250353B2 (en) * 2005-03-29 2007-07-31 Invensense, Inc. Method and system of releasing a MEMS structure
US20060228831A1 (en) * 2005-03-29 2006-10-12 Nasiri Steven S Method and system of releasing a MEMS structure
US20080003761A1 (en) * 2005-04-01 2008-01-03 Skyworks Solutions, Inc. Method for fabricating a wafer level package with device wafer and passive component integration
US7629201B2 (en) 2005-04-01 2009-12-08 Skyworks Solutions, Inc. Method for fabricating a wafer level package with device wafer and passive component integration
US20060237810A1 (en) * 2005-04-21 2006-10-26 Kirby Sand Bonding interface for micro-device packaging
US7611919B2 (en) * 2005-04-21 2009-11-03 Hewlett-Packard Development Company, L.P. Bonding interface for micro-device packaging
US9078563B2 (en) 2005-06-21 2015-07-14 St. Jude Medical Luxembourg Holdings II S.à.r.l. Method of manufacturing implantable wireless sensor for in vivo pressure measurement
KR100643769B1 (en) 2005-07-15 2006-11-10 삼성전자주식회사 Preparation method for a cap wafer using a soi wafer, fabricating mathod for a semiconductor chip using the cap wafer and the semiconductor chip fabricated by the same method
US11515202B2 (en) 2005-08-11 2022-11-29 Adeia Semiconductor Bonding Technologies Inc. 3D IC method and device
US9716033B2 (en) 2005-08-11 2017-07-25 Ziptronix, Inc. 3D IC method and device
US11289372B2 (en) 2005-08-11 2022-03-29 Invensas Bonding Technologies, Inc. 3D IC method and device
US11011418B2 (en) 2005-08-11 2021-05-18 Invensas Bonding Technologies, Inc. 3D IC method and device
US10147641B2 (en) 2005-08-11 2018-12-04 Invensas Bonding Technologies, Inc. 3D IC method and device
US20070243662A1 (en) * 2006-03-17 2007-10-18 Johnson Donald W Packaging of MEMS devices
US7635606B2 (en) 2006-08-02 2009-12-22 Skyworks Solutions, Inc. Wafer level package with cavities for active devices
US20090075431A1 (en) * 2006-08-02 2009-03-19 Skyworks Solutions, Inc. Wafer level package with cavities for active devices
US7964495B2 (en) * 2006-11-01 2011-06-21 Dongbu Hitek Co., Ltd. Method of manufacturing complementary metal oxide semiconductor image sensor
US20080102556A1 (en) * 2006-11-01 2008-05-01 Han-Choon Lee Method of manufacturing complementary metal oxide semiconductor image sensor
US20080217708A1 (en) * 2007-03-09 2008-09-11 Skyworks Solutions, Inc. Integrated passive cap in a system-in-package
US8222086B2 (en) 2007-09-24 2012-07-17 Research Triangle Institute Integrated semiconductor substrate structure using incompatible processes
US20090079058A1 (en) * 2007-09-24 2009-03-26 Research Triangle Institute Semiconductor substrate elastomeric stack
US7999388B2 (en) 2007-09-24 2011-08-16 Research Triangle Institute Preventing breakage of long metal signal conductors on semiconductor substrates
US8404585B2 (en) 2007-09-24 2013-03-26 Research Triangle Institute Preventing breakage of long metal signal conductors on semiconductor substrates
US20110183469A1 (en) * 2007-09-24 2011-07-28 Research Triangle Institute Integrated semiconductor substrate structure using incompatible processes
US7944041B2 (en) 2007-09-24 2011-05-17 Research Triangle Institute Integrated semiconductor substrate structure using incompatible processes
US7831874B2 (en) 2007-09-24 2010-11-09 Sixis, Inc. Local defect memories on semiconductor substrates in a stack computer
US7829994B2 (en) 2007-09-24 2010-11-09 Sixis, Inc. Semiconductor substrate elastomeric stack
US20090079084A1 (en) * 2007-09-24 2009-03-26 Research Triangle Institute Preventing breakage of long metal signal conductors on semiconductor substrates
US20090079059A1 (en) * 2007-09-24 2009-03-26 Research Triangle Institute Integrated semiconductor substrate structure using incompatible processes
US8008134B2 (en) 2007-09-25 2011-08-30 Research Triangle Institute Large substrate structural vias
US20100200540A1 (en) * 2007-09-25 2010-08-12 Sixis, Inc. Large substrate structural vias
US20100306993A1 (en) * 2007-11-20 2010-12-09 Board Of Regents, The University Of Texas System Method and Apparatus for Detethering Mesoscale, Microscale, and Nanoscale Components and Devices
US8739398B2 (en) * 2007-11-20 2014-06-03 Board Of Regents, The University Of Texas System Method and apparatus for detethering mesoscale, microscale, and nanoscale components and devices
US8809116B2 (en) 2007-11-30 2014-08-19 Skyworks Solutions, Inc. Method for wafer level packaging of electronic devices
US8324728B2 (en) 2007-11-30 2012-12-04 Skyworks Solutions, Inc. Wafer level packaging using flip chip mounting
US20100244161A1 (en) * 2007-11-30 2010-09-30 Skyworks Solutions, Inc. Wafer level packaging using flip chip mounting
US20100283144A1 (en) * 2007-12-26 2010-11-11 Steve Xin Liang In-situ cavity circuit package
US8900931B2 (en) 2007-12-26 2014-12-02 Skyworks Solutions, Inc. In-situ cavity integrated circuit package
US9153551B2 (en) 2007-12-26 2015-10-06 Skyworks Solutions, Inc. Integrated circuit package including in-situ formed cavity
WO2009111874A1 (en) * 2008-03-11 2009-09-17 The Royal Institution For The Advancement Of Learning/ Mcgiil University Low-temperature wafer level processing for mems devices
US9193583B2 (en) 2008-03-11 2015-11-24 The Royal Institution For The Advancement Of Learning/Mcgill University Low-temperature wafer level processing for MEMS devices
US20100187665A1 (en) * 2009-01-26 2010-07-29 Sixis, Inc. Integral metal structure with conductive post portions
US8129834B2 (en) 2009-01-26 2012-03-06 Research Triangle Institute Integral metal structure with conductive post portions
US8196475B2 (en) * 2009-03-16 2012-06-12 Kavlico Corporation Cointegrated MEMS sensor and method
US20100229651A1 (en) * 2009-03-16 2010-09-16 Kavlico Corporation Cointegrated mems sensor and method
US20100311209A1 (en) * 2009-06-05 2010-12-09 Jiangsu Lexvu Electronics Co., Ltd. Method o encapsulating a wafer level microdevice
US8043891B2 (en) 2009-06-05 2011-10-25 Shanghai Lexvu Opto Microelectronics Technology Co., Ltd. Method of encapsulating a wafer level microdevice
US10551193B2 (en) 2009-09-11 2020-02-04 Invensense, Inc. MEMS device with improved spring system
US9097524B2 (en) 2009-09-11 2015-08-04 Invensense, Inc. MEMS device with improved spring system
US9891053B2 (en) 2009-09-11 2018-02-13 Invensense, Inc. MEMS device with improved spring system
US9052194B2 (en) 2009-09-11 2015-06-09 Invensense, Inc. Extension-mode angular velocity sensor
US9683844B2 (en) 2009-09-11 2017-06-20 Invensense, Inc. Extension-mode angular velocity sensor
US8534127B2 (en) 2009-09-11 2013-09-17 Invensense, Inc. Extension-mode angular velocity sensor
US8347717B2 (en) 2009-09-11 2013-01-08 Invensense, Inc. Extension-mode angular velocity sensor
US8567246B2 (en) 2010-10-12 2013-10-29 Invensense, Inc. Integrated MEMS device and method of use
US8947081B2 (en) 2011-01-11 2015-02-03 Invensense, Inc. Micromachined resonant magnetic field sensors
US8860409B2 (en) 2011-01-11 2014-10-14 Invensense, Inc. Micromachined resonant magnetic field sensors
US9664750B2 (en) 2011-01-11 2017-05-30 Invensense, Inc. In-plane sensing Lorentz force magnetometer
US9212051B1 (en) 2011-08-04 2015-12-15 Western Digital (Fremont), Llc Systems and methods for forming MEMS assemblies incorporating getters
US9052445B2 (en) 2011-10-19 2015-06-09 Cisco Technology, Inc. Molded glass lid for wafer level packaging of opto-electronic assemblies
US9575266B2 (en) 2011-10-19 2017-02-21 Cisco Technology, Inc. Molded glass lid for wafer level packaging of opto-electronic assemblies
US8921201B2 (en) 2011-11-11 2014-12-30 International Business Machines Corporation Integrated semiconductor devices with amorphous silicon beam, methods of manufacture and design structure
US8546240B2 (en) 2011-11-11 2013-10-01 International Business Machines Corporation Methods of manufacturing integrated semiconductor devices with single crystalline beam
US9172025B2 (en) 2011-11-11 2015-10-27 Globalfoundries U.S. 2 Llc Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure
US9105751B2 (en) 2011-11-11 2015-08-11 International Business Machines Corporation Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure
US8629036B2 (en) 2011-11-11 2014-01-14 International Business Machines Corporation Integrated semiconductor devices with amorphous silicon beam, methods of manufacture and design structure
US9758365B2 (en) 2011-11-11 2017-09-12 Globalfoundries Inc. Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure
US9059396B2 (en) 2011-11-11 2015-06-16 International Business Machines Corporation Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure
US8871568B2 (en) * 2012-01-06 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Packages and method of forming the same
US20130175694A1 (en) * 2012-01-06 2013-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packages and Method of Forming the Same
CN103199055A (en) * 2012-01-06 2013-07-10 台湾积体电路制造股份有限公司 Packages and method of forming the same
CN103199055B (en) * 2012-01-06 2016-03-09 台湾积体电路制造股份有限公司 Packaging part and forming method thereof
US9754922B2 (en) 2015-02-11 2017-09-05 Invensense, Inc. 3D integration using Al—Ge eutectic bond interconnect
US10651151B2 (en) 2015-02-11 2020-05-12 Invensense, Inc. 3D integration using Al—Ge eutectic bond interconnect
US11710718B2 (en) 2015-07-10 2023-07-25 Adeia Semiconductor Technologies Llc Structures and methods for low temperature bonding using nanoparticles
US10262963B2 (en) 2015-08-25 2019-04-16 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US11830838B2 (en) 2015-08-25 2023-11-28 Adeia Semiconductor Bonding Technologies Inc. Conductive barrier direct hybrid bonding
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US11264345B2 (en) 2015-08-25 2022-03-01 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US10192850B1 (en) 2016-09-19 2019-01-29 Sitime Corporation Bonding process with inhibited oxide formation
US11869870B1 (en) 2016-09-19 2024-01-09 Sitime Corporation Bonding process with inhibited oxide formation
US10910341B1 (en) 2016-09-19 2021-02-02 Sitime Corporation Bonding process with inhibited oxide formation
US11488930B1 (en) 2016-09-19 2022-11-01 Sitime Corporation Bonding process with inhibited oxide formation
US10541224B1 (en) 2016-09-19 2020-01-21 Sitime Corporation Bonding process with inhibited oxide formation
US11894326B2 (en) 2017-03-17 2024-02-06 Adeia Semiconductor Bonding Technologies Inc. Multi-metal contact structure
US11908739B2 (en) 2017-06-05 2024-02-20 Adeia Semiconductor Technologies Llc Flat metal features for microelectronics applications
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11552041B2 (en) 2017-09-24 2023-01-10 Adeia Semiconductor Bonding Technologies Inc. Chemical mechanical polishing for hybrid bonding
US10319654B1 (en) 2017-12-01 2019-06-11 Cubic Corporation Integrated chip scale packages
US10553511B2 (en) 2017-12-01 2020-02-04 Cubic Corporation Integrated chip scale packages
US11804377B2 (en) 2018-04-05 2023-10-31 Adeia Semiconductor Bonding Technologies, Inc. Method for preparing a surface for direct-bonding
US11515279B2 (en) 2018-04-11 2022-11-29 Adeia Semiconductor Bonding Technologies Inc. Low temperature bonded structures
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
US11749645B2 (en) 2018-06-13 2023-09-05 Adeia Semiconductor Bonding Technologies Inc. TSV as pad
US11728313B2 (en) 2018-06-13 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Offset pads over TSV
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11756880B2 (en) 2018-10-22 2023-09-12 Adeia Semiconductor Bonding Technologies Inc. Interconnect structures
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11244920B2 (en) 2018-12-18 2022-02-08 Invensas Bonding Technologies, Inc. Method and structures for low temperature device bonding
US11735523B2 (en) 2020-05-19 2023-08-22 Adeia Semiconductor Bonding Technologies Inc. Laterally unconfined structure
US11929347B2 (en) 2022-01-19 2024-03-12 Adeia Semiconductor Technologies Llc Mixed exposure for large die

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