CN111108592A - 用于混合接合的化学机械抛光 - Google Patents
用于混合接合的化学机械抛光 Download PDFInfo
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- CN111108592A CN111108592A CN201880061619.XA CN201880061619A CN111108592A CN 111108592 A CN111108592 A CN 111108592A CN 201880061619 A CN201880061619 A CN 201880061619A CN 111108592 A CN111108592 A CN 111108592A
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Abstract
技术和方法的代表性具体实施包括用于混合接合的化学机械抛光。所公开的方法包括在基板上沉积和图案化电介质层以在电介质层中形成开口;在电介质层上方和开口的第一部分内沉积阻挡层;以及在阻挡层上方和开口的未被阻挡层占据的第二部分内沉积导电结构,导电结构的在开口的第二部分中的至少一部分耦接或接触基板内的电路。另外,对导电结构进行抛光以显露出阻挡层的沉积在电介质层上方而不是在开口的第二部分中的部分。此外,用选择性抛光对阻挡层进行抛光,以在电介质层上或电介质层处显露出接合表面。
Description
优先权要求和相关申请的交叉引用
本专利申请根据35 U.S.C.§119(e)(1)要求2018年9月17日提交的名称为“用于混合接合的化学机械抛光(CHEMICAL MECHANICAL POLISHING FOR HYBRID BONDING)”的美国临时申请号16/133,299和2018年9月13日提交的名称为“用于混合接合的化学机械抛光(CHEMICAL MECHANICAL POLISHING FOR HYBRID BONDING)”的美国临时申请号62/730,936以及2017年9月24日提交的名称为“用于混合接合的化学机械抛光(CHEMICAL MECHANICALPOLISHING FOR HYBRID BONDING)”的美国临时申请号62/562,449的权益,这些美国临时申请中的每一个均据此全文以引用方式并入。
技术领域
以下描述涉及集成电路(“IC”)的抛光。更具体地,以下描述涉及用于IC的混合接合的机械抛光。
背景技术
混合接合是用于接合微电子部件(诸如管芯和晶片)并形成电气连接的有用技术。一种混合接合技术是购自Xperi Corp.的附属公司Invensas Bonding Technologies,Inc.(以前称为Ziptronix,Inc.)的接合技术的“Direct Bond Interconnect”(参见例如美国专利号7,485,968,该美国专利全文以引用方式并入本文)。一般来讲,将两种电介质(各自定位在单独的基板上)放在一起,以在没有中介材料(诸如粘合剂)的情况下在低温或环境温度下形成接合部。
作为该接合方法的一部分或在该接合方法之后,导电结构(诸如铜垫、柱形件、穿过基板的通孔,或凸块)可散布在IC的电介质层内。可以将每个基板上的导电特征对准,以在两个基板之间提供电接口。
用于形成接合表面的常规技术可包括在基板(例如,有源半导体管芯等)上形成绝缘层(例如氧化物),所述接合表面用于形成混合接合。绝缘层可被图案化以形成开口,并且可在绝缘层上方和图案化的开口内形成阻挡层。另外,也可在开口中并且通常在绝缘层上方形成导电结构(例如Cu等)。然后可通过化学-机械平面化(CMP)方法去除导电结构的一部分,并且可通过CMP方法进一步去除覆盖绝缘层的阻挡层。这样,剩余的导电结构和绝缘层的表面可被准备成使得导电结构可与另一基板的导电结构形成电连接,并且绝缘层可与另一基板的绝缘层形成混合(即机械)接合。
然而,当使用此类常规技术时,可能发生氧化物圆化(rounding)和导电结构凹进(dishing)。氧化物圆化可导致每个基板的铜元件之间的氧化物接合中的间隙。另外,导电结构凹进可导致失败的铜接合。此类缺陷的原因可能是由于此类材料在CMP方法期间被不均匀地磨损,从而影响了接合表面的质量。因此,需要改善表面的平面化和导电结构凹进,这继而将改善混合接合技术的收率和可靠性。
附图说明
参考附图阐述了详细描述。在这些图中,参考标号的一个或多个最左边的数字标识首次出现参考标号的图。在不同图中使用相同的附图标记表示相似或相同的项目。
对于该讨论,图中所示的装置和系统被示出为具有多个部件。如本文所述,装置和/或系统的各种实施方式可以包括较少的部件并且仍然在本公开的范围内。另选地,装置和/或系统的其它实施方式可以包括附加部件或所描述部件的各种组合,并且仍然在本公开的范围内。
图1示出了氧化物圆化和导电结构凹进的轮廓视图。
图2示出了导致氧化物圆化和导电结构凹进的方法。
图3示出了显示出氧化物圆化和导电结构凹进的堆叠晶片的轮廓视图。
图4示出了根据一个实施方案的减少的氧化物圆化和减少的导电结构凹进的轮廓视图。
图5示出了根据一个实施方案的堆叠晶片的轮廓视图。
图6示出了根据一个实施方案的晶片的各层的轮廓视图。
图7示出了根据一个实施方案的用于化学机械抛光的方法。
图8A至图8D示出了根据示例性实施方案的基于金属密度的垫布局。
图9示出了根据一个实施方案的基于图案的垫布局。
图10A和图10B示出了根据一个实施方案的垫调节参数的结果。
图11是示出根据一个实施方案的抛光用于混合接合的各层的示例性方法的流程图。
发明内容
公开了用于混合接合的化学机械抛光的各种实施方案和技术。这些实施方案包括防止或去除在管芯上发现的电介质侵蚀(或圆化)和导电结构凹进的存在,从而导致更均匀且一致的平面接合表面的技术。
一种方法可包括在基板上沉积和图案化电介质层以在电介质层中形成开口;在电介质层上方和开口的一部分内沉积阻挡层;以及将导电结构沉积在阻挡层上方和开口的至少一部分内,该导电结构的至少一部分耦接或接触基板内的电路。另外,可对导电结构进行抛光以显露出阻挡层的沉积在电介质层上方而不是开口中的部分,使得导电结构在由阻挡层的沉积在电介质层上方而不是开口中的部分限定的平面下方不会凹陷超过第一预定量。此外,可利用选择性抛光对阻挡层进行抛光,以在电介质层上或电介质层处显露出接合表面,使得电介质层的邻近导电结构的表面不被圆化到超过第二预定量。另外,在制备导电结构的接合表面之后,可使导电结构凹陷不超过第三预定量。在提供多个导电结构的情况下,它们可具有相同或不同的尺寸并且可按一个或多个规则图案布置,每种布置可具有相同或相似尺寸的结构和/或相邻结构之间的相同或不同的节距。例如,导电结构可各自大于5微米,并且按某一图案以1.2或更大的节距布置。
在第一实施方案中,在开口的第二部分中的导电结构的至少一部分耦接到或接触基板内的电路。另外,该方法可包括将基板的接合表面与另一基板的接合表面接合。例如,通过使接合的结构在低于400℃的温度下退火,可在接合之后在基板的导电部分与另一基板之间形成电连接。另外,可使用不利用粘合剂的直接接合技术来接合基板的接合表面和另一基板的接合表面。此外,接合表面和导电结构的表面粗糙度可小于2nm均方根(RMS)或在另一实施方案中小于1nm RMS。另外,在一个实施方案中,电介质层的表面粗糙度可小于1nm RMS。
在第二实施方案中,对导电结构进行抛光可包括维持一致的导电结构去除率。另外,对导电结构进行抛光可通过反应性液体浆液来控制。
在第三实施方案中,对阻挡层进行抛光可包括去除开口外的任何过量阻挡层。另外,对阻挡层进行抛光可包括同时去除导电材料的至少一部分、阻挡层的至少一部分和电介质层的至少一部分。与对阻挡层进行抛光相关联的去除速率可控制导电结构的深度和电介质层的与阻挡层和/或导电结构相邻的部分的倾斜度。
在第四实施方案中,与对阻挡层进行抛光相关联的选择性可控制导电结构的深度和电介质层的倾斜度。例如,选择性可以是两种不同材料的去除速率的比率。导电结构对电介质层的选择性可为导电结构的去除速率除以电介质层的去除速率的比率。
在第五实施方案中,选择性可包括修改金属层参数,金属层参数包括阻挡金属的类型、阻挡金属的厚度或阻挡金属的侵蚀速率中的至少一者。例如,阻挡金属的类型可包括与Cabot EPOCH C8902铜浆液一起使用的钛,或与Dow ACuPLANETMLK393一起使用的钛或钽(或基于此类元素中的任一者的化合物)中的至少一种。可通过修改抛光消耗品来实现选择性,该抛光消耗品包括抛光垫、浆液类型、流量、浆液稀释度、抛光压力或调节盘(conditioning disc)类型中的至少一者。例如,抛光垫可包括SubaTM500或DOW IC1000TM型垫中的一者。另外,选择性可包括修改抛光参数,该抛光参数包括台板速度、晶片载具速度、浆液流量、向下力或垫调节类型中的至少一者。例如,增加浆液流量可使导电材料的凹进减少,或降低浆液流量可使导电材料的凹进增加。在一个实施方案中,此类浆液流量可在对200mm的导电结构进行抛光的情况下施加。
在第六实施方案中,一个或多个接合的结构可包括在该一个或多个接合的结构的正面和背面两者处均暴露的连续导电结构。在一个实施方案中,一个或多个接合的结构可包括接合的基板。另外,一个或多个接合的结构的正面和背面两者均可被平面化,使得对应于该一个或多个接合的结构的正面和背面中的每一个的表面不会凹陷超过预定量。
一些公开的过程可以使用方框流程图来示出,包括图形流程图和/或文本流程图。描述所公开的过程的顺序不旨在被解释为限制,并且可以以任何顺序组合任何数量的所描述的过程框以实现该过程或另选过程。另外,在不脱离本文描述的主题的实质和范围的情况下,可以从这些过程中删除某些单独框。此外,在不脱离本文描述的主题的范围的情况下,所公开的过程可以在任何合适的制造或加工设备或系统中连同任何硬件、软件、固件或它们的组合一起实现。
下面使用多个示例更详细地解释实施方式。尽管在此处和下文讨论了各种实施方式和示例,但是通过组合各个实施方式和示例的特征和元素,其它实施方式和示例也是可能的。
具体实施方式
概述
公开了用于混合接合的化学机械抛光(CMP)技术的各种实施方案。电介质层可包括电介质侵蚀(或电介质层的表面的圆化),并且导电结构可包括凹进,该电介质侵蚀和凹进都是由于CMP导致的,并且电介质侵蚀和凹进两者均可不利地影响接合。所公开的技术改善了电介质层的平面化和导电结构凹进的控制。
在各种实施方案中,使用本文所公开的技术可改善用于接合技术的堆叠方法,并且提高堆叠结构的可靠性和收率。要堆叠并在没有粘合剂的情况下使用表面至表面直接接合技术(诸如)和/或混合接合(诸如“Direct Bond Interconnect”)进行接合的管芯(其可易受电介质侵蚀和导电结构凹进影响(电介质侵蚀和导电结构凹进非常需要平坦度极其受控的界面))可尤其受益,所述和“Direct BondInterconnect”均可购自Xperi技术公司Invensas Bonding Technologies,Inc.(先前称为Ziptronix,Inc.)(参见例如美国专利号6,864,585和7,485,968,这两篇美国专利的全文以引用方式并入本文)。电介质层的表面的平面化可用于减少电介质侵蚀(和/或电介质层的圆化)。控制导电结构凹进可改善两个表面紧密接合以及确保导电结构在整个接合界面上正确接触的能力。
在制造用于混合接合的晶片时,可改善混合接合(包括收率和可靠性)的因素包括:1)使电介质层或基板的表面平面化;以及2)使导电结构凹进的量最小化。例如,混合接合可通过以下方式来改善:在后续接合操作之前形成具有最小的电介质侵蚀和感兴趣的导电结构的受控凹进(即,凹陷)的一个或多个平面电介质接合表面。
在一个实施方案中,镀覆的阻挡层和/或导电层可以均匀的方式施加。例如,镀覆的阻挡层或导电层的不均匀度可小于7%直至基板的边缘排除部(edge exclusion)。另外,优选的是将阻挡层或导电层的不均匀度限制为低于3%直至基板或晶片的边缘排除部。
如果所形成的导电层具有较差的均匀度,则对基板进行抛光可在感兴趣的导电结构中导致过多的凹进缺陷,因为在导电结构的一些部分中(去除过量的导电结构所需的)较长的抛光时间可导致在基板的已显露出阻挡层的其它部分中过度抛光。
例如,如果去除导电结构的在阻挡层上围绕基板中心的一部分的抛光时间为300秒,并且可能需要附加120秒来去除剩余导电结构的在基板周边附近的一部分,则该附加的120秒可被理解为过度抛光时间。120秒的过度抛光时间(或通过120/300*100计算的40%过度抛光时间)可用于去除基板周边附近的导电层。
这样,在基板中心处或围绕该基板中心(例如,在导电结构可位于的位置处)的预定量的凹陷可高于在基板(例如,晶片或面板)周边处或围绕该基板周边的第一预定量的凹陷。在一个实施方案中,第一预定量的凹陷可为在整个基板上均匀的,并且在去除阻挡层之前可小于60nm。在另一个实施方案中,在去除阻挡层之前,第一预定量的凹陷可小于40nm。该凹陷可从表面,诸如阻挡层的表面、接合表面或如由两个接合的表面之间的界面限定的接合平面测量。
相似地,对阻挡层或电介质层的过度抛光可增加在电介质层的在阻挡层附近的部分中对电介质层的电介质侵蚀。因此,在一个实施方案中,导电结构或阻挡层的过度抛光时间可小于30%的过度抛光时间。在一个实施方案中,导电结构或阻挡层的过度抛光时间可小于10%的过度抛光时间。例如,对导电结构进行抛光以显露出阻挡层所需的时间可为300秒,以包括10%的过度抛光时间。具体地,阻挡层的过度抛光可小于10%的过度抛光时间。
在一个实施方案中,抛光过程可用于控制导电结构中的凹陷并在导电结构中形成第二预定量的凹陷。另外,在一个实施方案中,在已经从电介质层的表面去除阻挡层之后,电介质层和开口(或镶嵌腔体)和阻挡层内的导电结构的去除速率可非常相似。
在另一个实施方案中,在1nm至10nm范围内的导电结构凹进可足以实现可接受的DBI接合表面。铜化学机械抛光(CMP)和阻挡金属CMP可用于实现电介质层的接合表面的平面化和/或使导电结构凹进的量最小化。例如,铜CMP和阻挡CMP步骤可各自通过调整消耗品(诸如垫、浆液等)和抛光参数来修改。这样,可调节电介质层、导电层/结构的部分(诸如铜)和阻挡金属的去除速率以满足整个CMP过程的要求,从而实现电介质层表面的平面化和/或最佳的导电结构凹进。在一个实施方案中,铜CMP和阻挡金属CMP可在包括电介质层的铜互连技术的情况下施加。
如前所述,导电结构中的第一预定量的凹陷是在对导电层进行抛光以使整个基板上的阻挡层暴露之后形成的。相似地,导电层中的第二预定量的凹陷部可在从基板或电介质层的表面去除阻挡层之后形成。阻挡层可通过CMP方法去除,并且在其它实施方案中,可通过(例如)反应离子蚀刻方法(RIE)或甚至湿蚀刻方法选择性地去除阻挡层。
然而,导电结构中的第二预定量的凹陷可为在整个基板或电介质层上均匀的,并且可以小于30nm。此外,第二预定量的凹陷可小于15nm。第二预定量的凹陷可小于第一预定量的凹陷。在一个实施方案中,在使合适的表面平面化之后,可清洁平面化的接合表面并准备用于接合操作。例如,接合表面准备步骤可包括将接合表面暴露于氧或氮等离子体(或两者)。在一个实施方案中,暴露可在空气中或在真空内发生。接合表面准备步骤可包括在导电结构中形成第三预定量的凹陷。在一些应用中,在阻挡去除步骤之后,可利用用于基板切割工艺的保护层来涂覆接合表面。在切割步骤之后,可通常通过湿式清洁技术从接合表面上去除保护层。保护层清洁步骤可包括将接合表面暴露于包含氧的等离子体物质。这些后续工艺步骤可修改感兴趣的导电结构中的凹陷,新凹陷是第三预定量的凹陷。第三预定量的凹陷或凹进可在1nm至20nm的范围内,并且优选地小于10nm。在一个实施方案中,第一预定量的凹陷可大于第三预定量的凹陷。
电介质层可包括具有硅的氧化物、氮化物或碳化物,金刚石,类金刚石碳(diamondlike carbon,DLC),低介电常数材料,玻璃,陶瓷材料,玻璃陶瓷,聚合物材料和/或它们的组合的一个或多个层。在一个实施方案中,电介质层可沉积在基板上,该基板包括晶片或管芯(诸如直接或间接带隙半导体材料)。附加地或另选地,接合表面可包括在电介质材料基板上形成的电介质层或具有嵌入的管芯或导电层的包装件。
在本说明书的上下文中,术语导电结构可指具有任何导电材料的层,并且导电结构凹进可指与感兴趣的一个或多个导电结构相关联的任何凹进。如本文所述,可首先在阻挡层上形成导电层,之后进行导致连续或不连续导电结构的去除工艺。此外,导电结构可包含诸如铜、镍、钴、金、锡等材料和/或基于此类元素的任何合金。
在一个实施方案中,接合的结构(包括层叠有电介质层和导电结构的基板)可包含不同的材料,其中基板、电介质层、阻挡层和/或导电结构中的每一者或任一者可包括不同的热膨胀系数或杨氏模量。因此,接合的结构可包含类似或不同的材料。此外,接合的结构中的一者可包括有源器件、无源器件(诸如电容器、电感器、电阻器等)、光学器件(例如,激激光器、发光二极管等)或机械器件和/或谐振腔中的一者,或它们的组合。
然而,在一个实施方案中,电介质层可被形成或修改为包括一个或多个开口,以便以均匀或变化的节距或甚至不均匀的放置容纳一个或多个具有类似或不同尺寸的导电结构(或垫)。例如,电介质层的接合表面可包括一个或多个腔或开口,导电垫可以在该一个或多个腔或开口中。导电垫的宽度可为沟槽宽度的大于50%。在一个实施方案中,垫的宽度可在2微米至200微米的范围内,并且一对垫的节距可在该垫的宽度的1倍至8倍的范围内变化。在另一个实施方案中,垫的宽度可在介于5um与50um之间的范围内,并且垫的节距可在垫的宽度的1.2倍至5倍的范围内变化。在一些实施方案中,感兴趣的垫或导电结构可电连接到下面或横向上的另一个导电层。
图1示出了微电子元件100的电介质侵蚀和导电结构凹进的轮廓视图。第一晶片102可包括基底层103(未按比例示出),诸如半导体,以及电介质层104的具有表示电介质侵蚀的弯曲表面的部分。在一个实施方案中,电介质层104可以是氧化物层,在这种情况下,电介质侵蚀也可称为氧化物圆化。另外,第一晶片102可包括导电结构106,该导电结构具有典型凹状弯曲的表面,该典型凹状弯曲的表面表示导电结构凹进。此外,可由于电介质层104的电介质侵蚀和导电结构106的导电结构凹进而产生将接合平面平分的凹陷部108。
图2示出了导电结构形成方法200。如步骤A处所示,电介质层104可包括形成在表面204上的一个或多个腔202(或开口)。腔的宽度可在介于0.3微米至超过50微米之间变化。腔的深度可在介于0.3微米至超过20微米的范围内,并且可为延伸穿过基板的导电通孔的一部分或延伸至该导电通孔。在一些实施方案中,腔可包括穿过基板的腔,诸如穿过基体部分103(未按比例示出)。在步骤B处,表面204可衬有层206,诸如阻挡层和/或晶种层。根据腔202的深度,层206(诸如阻挡层)的厚度可例如在介于1nm与100nm之间变化。在一个实施方案中,阻挡层206的厚度可介于3nm与50nm之间。另外,作为阻挡层的层206可由钽、钛、镍、钌、钴和钨等,它们的合金或化合物和/或衍生物构成。在一个实施方案中,层206可用作阻挡件,并且用作晶种层以形成导电结构106的层。
在步骤C处,导电结构106可形成在层206上方和/或内部。在形成导电层106之后,随后可诸如通过CMP去除材料的部分,以形成导电结构。此外,应当理解的是,尽管在步骤C-E处未明确示出层206,但层206仍可包括在导电结构106的下方和/或两侧。
在步骤D和E处,示出了去除材料的效应,该效应可包括基板104的表面的平面化、电介质侵蚀和导电结构凹进。步骤D和E处的示例提供了电介质侵蚀(或“圆化”)的两个示例性结果,该两个示例性结果可使用具有与电介质侵蚀的形状相关联的曲率半径的圆的一部分进行建模,以描述侵蚀的大小。例如,步骤D处的电介质侵蚀可由具有较小曲率半径208的圆表示,而步骤E处的电介质侵蚀可由具有较大曲率半径210的圆表示。曲率半径208和210的大小可描述在电介质104与导电结构106的交汇处的圆化(曲线表面)的陡峭程度(包括该方法的陡峭程度),以及由于侵蚀而在交汇处产生的间隙的大小。需注意的是,在该描述中,具有曲率半径208或210的圆用于对电介质104与导电结构106的交汇处(或介于电介质与导电结构之间的阻挡件)的侵蚀部分进行建模,并且可不一定表示电介质104的总体圆化。曲率半径208和210的大小可以是关于紧密接合的潜在问题的可能性的指示标识。曲率半径越小,则电介质侵蚀越小。因此,电介质层104的电介质侵蚀(或圆化)可防止与相对表面紧密接触。在另一种方法中,被侵蚀的电介质层的截断部与阻挡层之间相对于电介质表面的角度的余角的正切是电介质侵蚀的量度(电介质侵蚀角)。电介质侵蚀越小,则所述电介质侵蚀角的值就越小。对于不存在电介质侵蚀的理想情况,电介质侵蚀角的值为零,因此电介质侵蚀角的正切为0。可使用其它几何描述形容词来描述电介质侵蚀;一般来讲,优选的是电介质侵蚀角小于30度,并且优选地小于10度或甚至1度,其中电介质侵蚀角的正切接近于0。在一个实施方案中,电介质侵蚀(电介质侵蚀角的正切)小于5nm/微米,并且优选地小于1nm/微米。
步骤D还示出了导电结构可与电介质104齐平或相对于电介质104局部地凹陷(即,其中导电结构106的表面最靠近电介质104的表面)小于凹陷108的量。相比之下,步骤E示出使导电结构相对于电介质104局部地凸出(即,其中导电结构106的表面最靠近电介质104的表面),同时还相对于接合表面凹陷达凹陷108。
CMP期间去除的材料可包括导电层和结构106的部分、阻挡层(诸如层206)的部分,和/或电介质层104的表面的部分。在一个实施方案中,(电介质侵蚀208和/或210的)曲率半径越大,则在将电介质层104接合到另一个准备好的表面时发生缺陷的可能性就越大。因此,较小的曲率半径或较小的电介质侵蚀可指示相对的接合层或表面之间发生缺陷的可能性较小。
图3示出了堆叠的晶片102和306的轮廓视图300,其示出了过度的电介质侵蚀和导电结构凹进。如图所示,第一晶片102可包括基底层103(未按比例示出)、显示出电介质侵蚀的第一电介质层302,以及显示出导电结构凹进的第一导电结构304。另外,第二晶片306可包括第二电介质层308和第二导电结构310。当第一晶片102和第二晶片306堆叠时,可能在第一晶片102与第二晶片306之间产生间隙312。间隙312可由导电结构凹进和/或电介质侵蚀208和210引起。在一个实施方案中,间隙312可防止第一电介质层302与第二电介质层308之间的紧密表面至表面接合。在一个实施方案中,在较高温度下,可建立第一导电结构304与第二导电结构310之间的紧密接触,但是电介质308和302的接合表面之间连续、紧密的表面接触是不太可能的。
相比之下,图4示出了根据本文所述的一个或多个实施方案的具有减小的电介质侵蚀和减小的导电结构凹进的微电子部件400的轮廓视图。第一晶片102包括基底层103(未按比例示出)、具有对基底层103的直接或间接的最小电介质侵蚀的电介质层402,以及具有从平面或表面(诸如接合界面或平面接合电介质表面)的最小导电结构凹进或凹陷的导电结构404。由于使用了本文所公开的技术,因此凹陷406是最小的(尤其是与前述附图中所示的凹陷108相比)。在一个实施方案中,凹陷406可基本上不存在。例如,电介质层402的电介质侵蚀和导电结构404的导电结构凹进可能不存在,从而导致凹陷406不存在。在一个实施方案中,电介质层402的接合表面可表征为基本上平坦的,并且导电层中的凹陷优选地小于5nm。具有这些类型的表面特性的基板可在低于150℃的温度下接合。
在一些实施方案中,形成(例如,电镀)导电层可经由使用包括可用于确保无空隙填充的超填充添加剂的镀浴来实现。在其它实施方案中,导电层可通过各种方法的组合形成,该各种方法包括原子层沉积、化学镀、溅射、蒸镀、激光沉积等。另外,导电层可在介于室温与低于250℃之间进行热处理达预定量的时间。在一个实施方案中,在低于100℃的温度下对导电层进行热处理。导电层可形成在加晶种的表面(诸如层206,未示出)上方。另外,在一个实施方案中,可实现导电层在电介质层402的整个表面上的均匀涂覆,使得导电层的不均匀度小于7%直至电介质层402的边缘排除部。在另一个实施方案中,导电层的不均匀度可小于3%直至电介质层104的边缘排除部。
另外,导电层的厚度可在0.3-200um的范围内。在一个实施方案中,导电层的厚度可在0.3-20μm的范围内。导电层可形成为导电结构404,诸如双镶嵌结构、迹线、穿过基板的通孔(TSV)等。此外,任何不期望的材料(待去除的材料)可包括用于导电结构404的材料的不需要的部分、阻挡层的不需要的部分和/或电介质层402的不需要的部分。
基于(电介质层402的)电介质侵蚀的曲率半径,电介质402的表面与导电结构404(或与相邻层,诸如开口内的阻挡件)的交汇处可为导电结构404的深度的小于10%。在用于减小圆化侵蚀的示例中,导电结构404和阻挡层的抛光压力可在0.3psi至5psi的范围内变化,并且任何过度抛光时间可保持在低于30%以控制导电结构凹进和/或使电介质侵蚀(或圆化)最小化。此外,导电结构和阻挡层的抛光压力可在0.5psi至3psi的范围内变化,并且任何过度抛光时间可保持在低于10%以控制导电结构凹进和/或使电介质侵蚀最小化。
在一个实施方案中,电介质层402的开口(包括导电垫、沟槽和/或腔)可被配置为具有均匀、变化或不均匀的尺寸、节距和布局。在一个实施方案中,导电垫可为沟槽宽度的大于50%,该沟槽宽度还可包括任何阻挡层或其它导电或绝缘层。另外,导电垫的宽度可在2μm至200μm的范围内,并且一对垫的节距可在该垫的宽度的1.1倍至8倍的范围内变化。在另一个实施方案中,导电垫的宽度可在5μm至40μm的范围内,并且一对垫的节距可在该垫的宽度的1.2倍至5倍的范围内变化。另外,第一晶片102或管芯的特定区域内的导电结构的局部周期性可不同于第一基板102(例如晶片、面板或管芯)上的导电结构的单独分组的周期性。
图5示出了根据一个实施方案的堆叠的管芯、晶片等的轮廓视图。堆叠的部件可包括如图所示具有两个管芯的微电子组件500,但是可根据需要或按照给定设计的需求堆叠更多的管芯。如图所示,第一基板102可包括第一基底层103、第一电介质层502和第一导电结构504。另外,第二基板306可包括第二电介质层506和第二导电结构508。作为使用本文所公开的技术的结果,电介质侵蚀510和导电结构凹进512可被减小或甚至几乎消除。因此,电介质层502的表面可以可靠地与电介质层506的表面紧密接合,和/或导电结构508的表面可与导电结构504的表面紧密接合。
具体地,第一电介质层502和第二电介质层506的接合表面可以是平面的(如通过缺乏电介质侵蚀510所示)或接近平面的(不影响混合接合的最小量的电介质侵蚀)。另外,第一导电结构504和第二导电结构508的表面可以是平面的(如通过最小的或不存在导电结构凹进512所示)或接近平面的(不影响混合接合的最小量的导电结构凹进)。
在各种实施方案中,导电结构凹进或凹陷512可存在,并且可优选地以预定的最小量存在。例如,可预测到导电结构504和508在退火或操作期间的一些膨胀。因此,预定的最小量的凹进512或凹陷可为导电结构504和508中的一者或两者的膨胀提供空间,这可防止应力,包括在退火期间电介质层502和506的分层。此外,在接合的形式中,基板102和106中的至少一者上或中的至少一个导电结构可横跨由接合的电介质层限定的接合界面延伸,而另一个基板中的相应导电结构可在接合后保持一定程度的凹陷。然而,在接合期间或之后导电结构的组合膨胀将导致结构的接触。
另外,如图5所示,堆叠晶片可包括在接合的堆叠晶片(包括例如第一晶片102和第二晶片306)的多于一个表面上暴露的导电结构。可清洁此类堆叠晶片或基板的背部表面,并且在导电结构中具有预定量的凹陷(通常具有第三预定凹陷)的所述表面被准备好用于接合操作。在导电层中具有所需预定凹陷的另一个准备好的表面可接合到预接合基板102或306的经清洁且准备好的背面。在一个实施方案中,可使用本发明所公开的技术将底部基板与多个基板(2至100个)连续堆叠。将堆叠的基板在低于300℃、优选地低于200℃下热处理介于30分钟至180分钟之间的时间。热处理可在每次接合步骤之后施加,或者可在所有接合完成后施加一次以使整个堆叠同时退火。在一些应用中,需要较低的接合温度可导致更长的热处理时间来确保导电结构在接合界面上接触。在一些应用中,两个相对基板的接合表面被准备好用于接合操作,在其它情况下,在堆叠操作之前两个配对基板的接合表面中的仅一个被准备好。
如图5所示,导电结构504和508中的任一者或两者可为穿过基板的通孔(TSV),并且此类TSV可设置在具有不延伸穿过基板的其它导电结构(诸如迹线、接触垫)的基板上。
在各种具体实施中,铜抛光CMP可用于减少导电结构凹进。在实施铜抛光CMP之前,但在形成导电层之后,导电层的表面可具有阻挡金属(诸如存在于层206上)。该附加阻挡层还可通过在任何CMP开始之前用较硬的阻挡层填充铜层中的凹陷来确保平面性。
具体实施
从具有大致均匀的导电层表面的晶片开始(例如,图2C),铜和阻挡层CMP可具有以下特征:1.以均匀的导电材料去除速率和最小的过度抛光时间在导电层上执行第一抛光步骤,以形成具有如从阻挡层的顶表面测量的第一量的凹陷的导电结构;2.通过以下方式执行第二抛光步骤:施加高选择性阻挡浆液,以便以最小的过度抛光时间对阻挡金属进行抛光,从而形成具有如从电介质层的顶表面或从由电介质层的顶表面限定的接合平面测量的第二预定凹陷的导电结构。电介质具有最小的电介质侵蚀,使得电介质侵蚀角小于10度,并且优选地小于5度。还优选的是,第二预定凹陷小于第一预定凹陷。
在一个实施方案中,对于铜抛光,反应性液体浆液(例如Dow ACuPLANETMLK393铜浆液和Cabot EPOCH C8902铜浆液)可用于铜抛光。例如,使用反应性液体浆液Cabot EPOCHC8902浆液可与阻挡材料(例如TiN、TaN等)不利地反应,使得当下面的阻挡材料部分地暴露时(例如在晶片102的边缘处),铜抛光可显著减少。因此,在选择适当的导电层去除浆液时,应考虑阻挡层的性质。
阻挡金属抛光步骤(诸如用于层206的阻挡材料)可从晶片(诸如晶片102)的表面去除任何过量的阻挡金属,并且可用于控制铜DBI垫的最终凹进值。在一个实施方案中,阻挡金属抛光可用于校正铜抛光步骤后存在的任何不均匀性。然而,应当理解的是,如所指出的那样,铜抛光步骤的焦点是在整个基板上形成均匀或几乎均匀凹陷的导电结构,同时维持阻挡金属在整个基板上尽可能均匀。
阻挡金属抛光步骤可同时去除各种类型的材料,包括但不限于导电材料(诸如用于导电结构106的导电材料)、金属阻挡材料(诸如层206的阻挡材料)和固体电介质材料(诸如用于电介质层402中的氧化硅),以在导电结构中形成第二预定凹陷。阻挡金属抛光步骤的相对去除速率可控制导电结构404的表面上相对于电介质层402的表面的相对凹陷(诸如导电结构中的第二预定凹陷)和/或电介质倾斜度(诸如电介质侵蚀角)。
例如,导电结构404的表面的凹进变化的速率(如本文中由具有表示导电结构凹进的弯曲表面的导电结构404所示),以及电介质侵蚀的圆形化增加的速率(如在本文中例如由电介质侵蚀208和电介质侵蚀210所示,电介质侵蚀208可导致电介质侵蚀角的较小曲率半径或较浅斜率,电介质侵蚀210可导致较大的曲率半径),可由相应材料(诸如导电材料和/或电介质材料)的选择性来控制。此类选择性可包括两种不同材料的去除速率的比率。例如,导电材料(诸如铜)对电介质材料(诸如氧化物)的选择性可为导电材料的去除速率除以电介质材料的去除速率的比率。因此,控制选择性可影响导电结构的表面相对于电介质表面的相对深度(导电结构凹进),以及倾斜度(电介质侵蚀角)。
关于选择性,实现一组期望的形貌特征的一种方式可为调节选择性,使得该一组期望的特征可全部在特定的抛光时间间隔内实现。例如,这种同时优化可包括使用不同的选择性(诸如导电结构凹进(或凹陷)和电介质侵蚀(或圆化))构造感兴趣的特征的时间演变曲线图。此类曲线图可用于确定所施加的工艺是否在单个时间间隔内实现了期望的性能。该曲线图可允许对数据的可视化映射,使得可容易地发现进度和(性能的)缺陷,并且可确定应如何修改选择性(以实现期望的结果)。
可修改的与选择性相关的参数可包括晶片的金属层参数、抛光消耗品和/或抛光参数。可定制的阻挡金属层参数(诸如金属氮化物)包括阻挡金属类型、阻挡金属厚度和/或阻挡金属的侵蚀速率(例如,如在铜抛光期间)。可调节的抛光(使用CMP)消耗品包括一个或多个抛光垫、浆液类型(抛光浆液、浆液混合物)、浆液流量、浆液稀释度和/或调节盘类型。可调节的抛光参数(诸如主CMP工具参数)包括台板速度、晶片载具速度、浆液流量、施加到晶片上的向下力和/或垫调节参数。在各种实施方案中,可调节金属层参数、抛光消耗品和/或抛光参数以获得期望的结果,包括最小化或消除电介质侵蚀和导电结构凹进。
金属层参数
在一个实施方案中,阻挡金属的类型可影响阻挡金属对铜抛光的选择性。例如,钛(Ti)可能对Cabot EPOCH C8902铜浆液不具有良好选择性,而钽(钛)可对Cabot EPOCHC8902铜浆液具有良好选择性。另外,Dow ACuPLANETMLK393浆液可对作为阻挡材料的Ti、Ta及其氮化物均具有良好选择性。选择对铜抛光具有良好选择性的阻挡金属可有助于防止过度的阻挡金属侵蚀、不可恢复的导电结构凹进和电介质侵蚀。
另外,可使用阻挡金属的厚度来减少最终导电结构凹进。例如,如果铜抛光工艺导致较高水平的导电结构凹进(第一预定凹陷),则阻挡层可被制成较厚以有助于容纳额外的凹进,而不会增加最终结构的显著电介质侵蚀。在一个示例中,这可针对具有10um节距的直径为3-5μm的通孔的DBI图案,用厚度为至多80nm的Ti基阻挡金属来实现。在铜抛光步骤之后,导电结构中的第一预定凹陷是30-50nm,当与Dow LK393阻挡浆液结合使用时,较厚的Ti阻挡件可产生合适的DBI表面。另外,当铜抛光凹进(第一预定凹陷)是10-20nm时,可使用较薄的25nm Ta阻挡件来获得有利的结果。
抛光CMP消耗品
在CMP工艺期间,可使用一个或多个垫或子垫。此类一个或多个子垫可比主抛光垫软,并且在抛光操作期间,可利用磨料连续地修整抛光的表面以刷新该抛光表面,以防止该抛光表面变光滑(glazing)。在一个实施方案中,具有子垫的抛光垫可用于对导电结构进行抛光。因此,为了减少经抛光的导电结构(诸如导电结构406)中的缺陷,阻挡层抛光垫可比用于导电结构的抛光垫更硬。
为了实现更大的平面化,较硬的CMP垫可改善使基板平面化的能力。例如,SubaTM500型垫可用于阻挡抛光。另外,DOW IC1000TM型垫也可用于抛光出多种DBI图案,包括宽度在小于0.2微米至超过200微米的范围内并且节距在0.5至8之间变化的导电结构。
在一个实施方案中,为了控制导电结构404和阻挡层206中的凹进的预定量,可使用较硬的CMP垫来对导电结构404和阻挡层206两者进行抛光。在肖氏硬度D尺度上,垫的硬度计硬度可在介于45与90之间的范围内。在一个实施方案中,硬度计硬度可大于49。
然而,抛光浆液和浆液混合物能够被用来改善平面化。例如,各种材料的去除速率可能受阻挡浆液类型和混合物的影响。例如,用例如水或其它化学品稀释抛光浆液可降低电介质材料和阻挡金属的抛光速率,同时保持铜去除速率相对较高。因此,这种稀释可用于控制导电结构凹进,诸如当导电结构404的表面凸出到高于电介质层402的表面时(参见图6的示例)。
另外,铜去除速率可通过降低加入到浆液中的氧化剂(诸如过氧化氢(H2O2))的量来控制。例如,当使用Dow ACuPLANETMLK393阻挡浆液时,可通过减少加入到浆液中的H2O2来降低铜去除速率,而基本上不降低电介质层去除速率或阻挡金属去除速率。在一个实施方案中,导电结构去除速率的降低可降低到多达五(5)倍,而基本上不降低电介质层去除速率或阻挡金属速率。此外,可在抛光工艺期间将与浆液类型相容的调节盘施加到抛光垫的表面上,以维持导电层和阻挡层的可预测的均匀去除速率。
抛光参数
关于调节台板速度,较低的速度可通过降低的铜去除速率来增加凸起。另外,垫的较高速度可在抛光期间引起更大的加热,从而增大导电材料去除速率。电介质层402和阻挡材料206的去除速率可随着更高的工作台速度而增大。因此,晶片载具速度可设定为比工作台速度慢6-10转/分钟(RPM)。
浆液流动可另外用于控制去除率。例如,低浆液流量可用于降低氧化物抛光速率,同时维持导电材料去除速率。例如,可使用40ml/min流量的Dow ACuPLANETMLK393浆液来抛光在为直径2倍的节距上的直径为1-5um的铜特征的DBI表面。在一个实施方案中,经压花的SubaTM500垫上的40ml/min流量的Dow ACuPLANETMLk393浆液可达到3-10nm的稳态导电结构凹进。也可实现凹进和浆液流量的相反关系。例如,增加浆液流量可减少导电结构凹进,并且降低浆液流量可增加导电结构凹进。
相对于施加到晶片上的向下力,当使用LK393浆液时,随着向下力增大,所有材料的去除速率增大。在一个实施方案中,当铜本体层已被去除时,向下力可影响导电结构凹进。例如,更大的向下力可增加导电结构凹进(第一预定凹陷),这可能是由于与更大的向下力相关的增加的加热引起的。另外,晶片的水力刨削效应(hydroplaning effect)可用于控制导电结构凹进的量。
另外的示例性实施方案
图6示出了根据一个实施方案的晶片102的各层的轮廓视图600。如图所示,晶片102包括基板层602、电介质层604、阻挡层606,以及导电结构608。应当理解的是,基板层602可同样地存在于上述附图中的任一者上。例如,电介质层104、302、308、402、502和506可各自沉积在单独基板(诸如基板层602)或基板层合物上。
在各种实施方案中,基板602和电介质层604可由具有类似热膨胀系数(CTE)的类似材料构成,而在其它实施方案中,基板602和电介质层604可由不同的材料构成。另外,导电结构608的CTE可高于电介质层604的CTE。例如,导电结构608的CTE可以是电介质层604的CTE的大于十(10)倍。
在一个实施方案中,电介质层604可沉积在基板层602上,并被图案化以形成开口610。当然,应当理解的是,可形成任意数量的开口(包括例如开口610)。此类开口还可具有多种宽度、长度、深度和对应的节距。另外,阻挡层606可沉积在电介质层604上和开口610内。在一些实施方案中,可通过原子层沉积、等离子体溅射和/或化学气相沉积来涂覆阻挡层606。另外,导电结构608可沉积在阻挡层606上方和开口610内,如上文所述(例如,在图2中)。在一个实施方案中,导电结构608可直接耦接到电介质层604的和/或基板层602内的电路或导电结构(未示出),或与它们接触。
如图所示,在沉积阻挡层606和/或导电层608之后,阻挡层606和导电层608两者均可包括不平坦的表面。在一个实施方案中,电介质层604也可包括弯曲的或不平坦的表面。后续的抛光步骤(如本文所公开)可用于使阻挡层606的部分和导电层608的部分平面化以形成导电结构。另外,导电结构608可包括凹进和/或凸起,该凹进和/或凸起也可使用附加的或另选的抛光步骤(如本文所公开)来矫正。此外,导电结构可凸起到高于电介质的邻近导电结构的部分,同时仍相对于接合表面/平面凹陷。
图7示出了根据一个实施方案的用于化学机械抛光的示例性方法700。在这些方法中,可调节工艺变量中的一者或多者,诸如金属层参数、抛光消耗品和抛光参数,以实现期望的结果(例如,使电介质侵蚀最小化并使导电结构凹进最小化)。将讨论三个框(A、B和C),并对关于该三个框所讨论的过程变量进行调整。一般来讲,可能期望平衡影响导电结构凹进的工艺参数和影响电介质侵蚀(“圆化”)的工艺变量。
例如,导电结构凹陷的驱动因素包括相对于导电结构708(例如,铜)的抛光速率,电介质702(例如,氧化物)和阻挡层704(例如,氮化物等)的相对抛光速率(每单位时间的材料去除速率);以及抛光时间(其确定在给定抛光速率下去除的材料的量)。应当指出的是,抛光速率不同于每种材料的整体去除速率。如果相应地调整工艺参数,则电介质702、阻挡层704和导电结构708的抛光材料去除速率可最终达到稳态,并且凹陷水平在抛光时间内变成恒定的(维持相对于电介质702的上表面的相对凹陷)。
例如,在框A步骤1处,可将阻挡层704沉积在电介质层702上,并且可将导电层706沉积在阻挡层704上。在一个实施方案中,电介质层702可类似于电介质层104,并且导电层706可类似于导电结构106。另外,在导电层706的平面化期间,电介质层702和导电层706可存在于中间结构(例如,晶片、互连结构等)上。
参照框A的步骤2处,可去除导电层706的一部分以产生导电结构708。在一个实施方案中,去除导电层706的一部分可显露出阻挡层704以在层608上形成第一预定凹陷。框A的步骤2包括对阻挡层704进行抛光,使得可实现稳态材料去除速率,其中导电结构708的凹陷被维持为在电介质702的上表面的正下方,以相对于电介质702的经平面化的接合表面形成第二预定凹陷。
在一个具体实施中,为了实现材料的此类稳态去除(即,去除的抛光速率,而不是整体材料去除),将电介质层702和导电层706的材料去除速率(以产生导电结构708)调整为尽可能与阻挡层704的去除速率相似。这包括调整工艺参数和消耗品中的一者或多者以实现微妙的平衡,从而在整个抛光过程中产生宽操作范围(process window)和对导电结构708中的凹陷的自调控。在一个实施方案中,导电结构708的凹陷(第一预定凹陷)可在抛光期间保持在阻挡层704的表面下方小于30nm。
在框A步骤3处,在(经由使用CMP)完成对电介质702、阻挡层704和导电结构708进行抛光之后,导电结构708的凹陷(第二预定凹陷)可小于10nm。另外,导电结构708的凹陷(第二预定凹陷)可为阻挡层704的厚度的分数。在具有较薄阻挡层704的一个实施方案中,在阻挡层704的厚度可在3nm至25nm之间变化的情况下,在阻挡件去除步骤之后,第二凹陷可与阻挡层的厚度相当。另外,电介质侵蚀710可为最小的。
在框B步骤1处,电介质层702、阻挡层704和导电层706的结构可为类似于框A步骤1的方式,如本文所述。在框B步骤2处,去除导电层706的一部分(最多至阻挡层704的表面)以产生导电结构712。在一个实施方案中,基于导电层706材料的过度去除,导电结构712的凹陷(第一预定凹陷)可在阻挡层704的表面下方40-50nm。
在框B步骤3处,在(通过使用CMP)完成对电介质702、阻挡层704和导电结构708进行抛光之后,导电结构712的凹陷(第二预定凹陷)可小于20nm。另外,电介质侵蚀714可能更明显(与电介质侵蚀710相比)。因此,确定导电结构712的初始凹陷的工艺参数可对导电结构712的最终凹陷具有影响。
在框C步骤1处,电介质层702、阻挡层704和导电层706的结构可为类似于框A步骤1的方式,如本文所述。在框C步骤2处,去除导电层706的一部分(最多至阻挡层704的表面)以产生导电结构716。在一个实施方案中,基于导电层706材料的过度去除,导电结构716的凹陷(第一预定凹陷)可在阻挡层704的表面下方大于60nm。
在框C步骤3处,在(经由使用CMP)完成对电介质702、阻挡层704和导电结构708进行抛光之后,导电结构716的凹陷(第二预定凹陷)可大于30nm,但大于导电结构712的凹陷(第二预定凹陷)。另外,电介质侵蚀718可能更明显(与电介质侵蚀714相比)。因此,确定导电结构716的初始凹陷的工艺参数可对导电结构716的最终凹陷具有影响。框C步骤3还示出导电结构可凸起到高于电介质层和阻挡层的局部表面,但仍可相对于较大的接合表面齐平或凹陷。当多个接触结构彼此紧邻放置时,可存在次要表面,该次要表面可低于一般接合平面并且高于或低于接触结构。
在各种实施方案中,可为有益的是在去除阻挡层704的期望部分之前使导电结构708、712、716的凹陷(第一预定凹陷)最小化。另外,为了使凹陷(诸如在导电结构708中所示)减小到低于10nm,用于去除阻挡层704的工艺步骤(例如,化学品等)可被选择为对用于导电层706的材料(例如,铜)具有良好选择性。另外,如果在阻挡层704去除之前导电结构(诸如导电结构708)的凹陷较小,例如低于10nm,则基于所用的工艺元件,电介质侵蚀(诸如电介质侵蚀710)也可为最小的。
相比之下,如果在去除阻挡层704的表面之前导电结构712、716的凹陷较大,例如超过60nm(如导电结构716中所示),则电介质侵蚀(诸如电介质侵蚀718)可更显著地增加。
另外,电介质侵蚀可与阻挡层(诸如阻挡层704)的厚度相关。例如,如果阻挡层为约75nm厚,并且如果导电结构的凹陷(第一预定凹陷)为约75nm,则在去除阻挡层之后,电介质侵蚀可为最小的。相比之下,如果阻挡层为约40nm厚,并且如果导电结构的凹陷(第一预定凹陷)为约75nm,则在去除阻挡层之后,电介质侵蚀可更显著地增加。
在一个实施方案中,对阻挡层704进行抛光可用于控制导电结构(诸如导电结构708)的凹陷。例如,如所讨论的,可用于控制导电结构708的凹陷的一个或多个因素包括电介质层(诸如电介质层702)的抛光速率、阻挡层(诸如阻挡层704)的抛光速率、导电结构(诸如导电结构708)的抛光速率以及抛光时间。电介质层、阻挡层和导电结构的抛光速率可被配置为使得可实现每一者的稳态去除。应当理解的是,在去除导电层706的一部分(如框A、B和C的步骤2中所示)之前,将不会发生电介质层702的抛光。在稳态方法中,导电结构708的凹陷可在方法时间内保持恒定。
另外,在另一个实施方案中,抛光压力可用于控制凹进和电介质侵蚀(诸如电介质表面的圆化,诸如电介质侵蚀710、714和/或718)。所施加的抛光压力越高,则导电层706、阻挡层704和电介质层702的去除速率就越高。因此,较高的抛光压力产生导电层中的较高凹进,以及电介质层中的较高侵蚀。类似地,较低的压力产生相反的效应,伴随着较低的吞吐量(thru-put)罚分。在一个实施方案中,可对施加的压力进行分级。例如,导电层的起始压力可为持续适当时间量的4psi。然后,中间抛光压力可为持续适当时间量的2.5psi。用于去除阻挡层的表面上方的导电层的最终抛光压力可在2psi至1.5psi之间的范围内变化,并且在阻挡件表面上停止。类似地,可对用于去除阻挡层的抛光压力进行分级。例如,阻挡层去除压力可在2.5psi至0.5psi之间变化。初始起始压力可为2psi,并且阻挡件步骤结束时的抛光压力可为0.7psi。梯度压力方法的一个优点是,阻挡层下方的电介质层暴露于较低的压力,这倾向于有利于导电层的较低凹进和极低至不存在的电介质侵蚀角。在一个实施方案中,抛光工艺可包括在一些压力下的稳态去除过程,其中导电结构、阻挡层和电介质层的去除速率大致相同。在该方法中,在对导电结构进行抛光之后的第一预定凹陷类似于第二预定凹陷。第二预定凹陷可通过其它附加步骤进行改变,例如通过用稀释的浆液、湿式清洁方法或含氧或含氮的等离子体进一步抛光所述结构以形成第三预定凹陷。在一些应用中,可制备并紧密接合具有包括第二预定凹陷的接合表面的基板。而在其它实施方案中,具有包括第二预定凹陷的接合表面的基板可直接接合到包括具有第三预定凹陷的准备好的表面的另一基板。
图8A至图8D示出了根据一个实施方案的各种示例性导电垫800布局,从而确定了管芯或晶片的表面上的垫金属密度。
例如,在图8A中,利用如垫阵列中所示的导电垫800布置,相对于电介质的金属密度为约20%。例如,利用阵列的垫大小临界尺寸(CD)802(表示每个导电垫800的直径)可小于20μm。节距804(或垫间距)等于CD 802的长度的约两倍。
在图8B中,利用具有如图所示布置的导电垫800的示例,相对于电介质的垫金属密度为约7%。CD 802也可小于20μm,但是节距804等于CD 802的长度的约四倍。换句话讲,通过将垫间距804增加到图8A中的先前情况的两倍,该垫阵列中的垫金属密度受到显著影响(例如,减小65%)。
在图8C中,利用如图所示的导电垫800布置,相对于电介质的金属密度为约13%。CD 802保持为约20μm,然而节距804等于CD 802的长度的约2.8倍。换句话讲,利用图8C的中间布置,通过将垫间距804增加到图8A中的先前情况的间距的1.4倍,该垫阵列中的垫金属密度仍然受到显著影响(例如,减少35%)。在一些其它应用中,阵列内的垫的宽度或垫的宽度可在2微米至50微米的范围内变化,并且所述阵列内的垫的节距可在1.2至8之间变化。另外,具有不同垫构型的垫阵列可以周期性或非周期性图案彼此隔离,或者可聚集以形成垫的聚集阵列。例如,垫的聚集阵列可包括:由具有第一节距的垫组成的第一垫阵列;以及由具有第二节距的垫组成的第二垫阵列;以及由具有第三节距的垫组成的第三垫阵列。第一垫阵列的节距可小于第二垫阵列的节距。在一个实施方案中,在聚集阵列中,第一垫阵列中的垫的大小大于第二垫阵列中的垫的大小。在各种具体实施中,在管芯或晶片的表面上具有变化的金属密度的情况下,本发明的方法对管芯内和基板表面上的垫密度或垫大小的局部或远侧变化不太敏感。可将抛光方法施加到包含具有不同金属图案密度、不同宽度(在合理极限内)和不同深度的金属垫和沟槽的基板上,以产生具有最小电介质侵蚀和在各种导电结构内的适当凹陷的平面电介质表面。在一个实施方案中,各种垫和沟槽包括机械垫和沟槽,该机械垫和沟槽被配置为增强基板的除电特性之外的特性,例如以改善电介质层的热传递能力或提供微机电系统(MEMS)等。
在图8D中,示出了导电垫800的示例性布置。在该示例中,垫880的两种布置各自具有不同的垫大小和不同的节距。此外,可将布置间隔开大于这两种布置的节距中的任一节距的距离。当然,这些只是示例性布置和布局。在至少一个其它示例中,较大垫的布置可具有比较小垫的布置更大的节距。此外,可在这些布置中提供和/或向这些布置添加其它布置和/或非均匀布置的触点。
在一个具体实施中,垫800的布置或布局(例如,图案、分组等)也可用于使电介质侵蚀和导电结构凹陷最小化。在使用常规CMP方法的传统常见布置中,可使用跨越整个晶片902的规则图案(相同的特征大小和大致一致的布置)来在管芯或晶片表面上形成和布置垫800,以作为控制电介质侵蚀和凹进的方法。传统的金属CMP方法趋于产生随着经抛光的导电结构的宽度增加而增大的凹陷。例如,在阻挡件去除步骤之后,可在5微米宽的导电结构中测量到约15nm的凹陷,并且在15微米导电结构中测量到约28nm的凹陷。类似地,大于20微米的导电结构可表现出大于35nm的凹陷。在整个常规管芯上的凹陷的这些大变化意味着较小的导电结构中的导电金属将必须膨胀至少15nm,而较大的导电结构将必须膨胀至少35nm以与相对的接合表面紧密配合。对整个管芯上的凹陷的这些大变化的影响是,将需要例如320℃的更高温度的热处理方法,以实现在各种接触导电结构中的足够机械和电耦接,以及良好的基板接合。相比之下,根据本文所述的新型结构和方法,可使用各种垫布局、布置或图案在管芯或晶片表面上形成和布置垫800,该各种垫布局、布置或图案可以是规则的、不规则的、环状的、准随机的等等。在阻挡抛光步骤之后,这些布置中的接触结构的变化可小于10nm,并且优选地小于6nm。直接的实际意义是可在通常低于250℃且优选低于200℃的较低温度下形成紧密的良好接合。
例如,图9示出了根据各种实施方案的基于示例性图案的一些示例性垫布局。布置906、908和910示出了在通过本发明所公开的技术所实现的整个管芯或晶片上使用的图案的设计灵活性的示例。单个设计中垫大小和布局的此类变化对电路设计者而言是有吸引力的,因为它减少或消除了对虚设垫(dummy pad)的需要,否则虚设垫将需要实现必要的平面性。这种与一致布局的差异是期望的,因为不期望信号线上有未连接的金属(例如,虚设垫),这是由于潜在的耦接损耗。本发明的技术允许设计者具有更大的布局灵活性,以避免这种不期望的情况。
本文所述的技术的其它优点包括减少的金属层和降低的与堆叠相关的成本。例如,将TSV结构与控制质量接合表面的平面度和电介质侵蚀的能力相结合,允许在整个接合界面上实现晶片或管芯TSV至TSV、TSV至垫,和/或垫至垫连接的堆叠。因此,可实现第二电路管芯或晶片的正面上的互连,而不需要在TSV的顶部上进行金属层沉积。这可导致对用于复杂堆叠结构(诸如存储器阵列)的处理的简化。为了控制所有垫800上的凹进,可根据需要将第一图案用于管芯或晶片表面的一个或多个特定区域,而其它图案用于一个或多个其它区域。
如经由图9所示,垫800的分组可具有多种布置中的任一种,包括但不限于所示的那些布置。在A处,示出了第一示例性图案906。在B处,示出了具有不同布置或分组的第二示例性图案908。在C处,示出了具有另选的布置的第三示例性图案910。应当理解的是,可使用示例性晶片902的垫800的任何类型的图案或布置,而不产生有害的电介质侵蚀和导电结构凹陷。这些图案或其它图案可单独使用或在单个管芯或设计内组合到垫800的任何布局中,其中一种图案或布置之后可以是垫800的后续分组中的不同图案或布置。此类图案布置允许适应存储器、逻辑或其它电有源或无源部件和系统的设计。
在一个实施方案中,导电结构608的凹进可在一些或所有垫800上,基于垫800的大小,或者基于垫800的节距或布置以不同的严重性发生,其中所有垫800之间的特征大小是一致的。因此,在各种实施方案中,在维持其它工艺元件相等的同时,通过调整垫(800)的大小、节距和/或布置(分组、图案等)来实现对电介质侵蚀和导电结构凹陷的控制,包括减小或最小化电介质侵蚀和导电结构凹陷。
图10A和图10B示出了根据一个实施方案的基于垫调节参数的示例性表面平面化结果1000。垫调节参数可影响抛光速率,并继而影响最终的电介质侵蚀(诸如电介质层的圆化)和导电结构凹进。例如,当在没有有意调节的情况下使用DOW IC1000TM型垫时,多个晶片上的导电结构、阻挡金属和电介质层的导电材料的抛光速率可被维持,而无需使用利用调节盘对垫进行有意调节。该方法可用于多种DBI图案,包括20um节距上的直径为10um的DBI垫,以及具有5-15μm宽的密封环铜线的密封环晶片。在一个实施方案中,对图案化的金属阻挡晶片进行抛光可有助于自然地调节该垫。另外,定期抛光DBI晶片阻挡层可使DOWIC1000TM垫条件保持在关于DBI凹进的理想状态。
如结果1000所示,可用具有20um节距的直径为10um的垫800来展示低导电结构凹进。如上文所述,在一些情况下,例如包括导电结构(诸如导电结构608)的多个互连垫800的节距可为导电垫800的宽度的两倍。另外,导电结构可包括垫800、沟槽、迹线和/或穿过基板的互连件。
例如,晶片1002可包括节距为20um的多个10um直径的垫800。样本线1004表示在阻挡层去除过程之后的晶片1002的横截面,用于评估垫800的凹进和电介质104的圆化。例如,轮廓线1006示出了垫800和电介质104在横截面样本线1004处的轮廓。另外,表1008示出了在沿样本线1004的光标位置处的轮廓高度的瞬时变化。
示例性抛光方案和参数
在各种实施方案中,可使用与本文给出的公开内容一致的多种方案。例如,用于实现可接受DBI接合表面的第一方案可包括使用具有以下约束的减少的浆液:1)具有ViPR载具的工具IPEC 472;2)工作台速度63;3)晶片载具速度57;4)Pad SubaTM500EMB压花垫;5)有意的垫调节—无;6)向下力1.5;7)浆液流量40ml/min;以及8)Dow ACuPLANETMLK393浆液混合物,其中每升浆液中加入了约13ml的H2O2。这样,与低向下力和SubaTM垫结合的40ml/min的低浆液流量可有助于实现DBI的为5um且低于1-10nm(CMP的最终步骤的)的稳态导电结构凹进值。
用于实现可接受的DBI接合表面的第二方案可包括使用具有以下约束的经稀释的浆液流:1)具有研磨头(contour head)的工具AMATMESA;2)工作台速度113;3)晶片载具速度107;4)Pad SubaTM500GEL XY沟槽状垫;5)有意的垫调节—无;6)向下力2psi;7)浆液流量150ml/min;以及8)将1升的Dow ACuPLANETMLK393加入到2.75升的水中,加入到15mL的H2O2中。在一个实施方案中,该经稀释的浆液流对于5-10μm直径的晶片可为效果良好的,其中在以正常的浆液流量进行正常的阻挡件抛光之后,此类晶片具有凸起的铜和低初始导电结构凹进。这样,经稀释的浆液与较高的工作台和载具速度以及XY切割垫的组合可有助于实现约2-3nm的恒定导电结构凹进(第二预定凹陷)。另外,使用该方案,较长的抛光时间可导致与铜垫相邻处的电介质侵蚀(诸如电介质层的拐角圆化)增加。
用于实现可接受的DBI表面的第三方案可包括使用具有以下约束的减少的H2O2:1)具有钛载具的工具IPEC 472;2)工作台速度63;3)晶片载具速度57;4)Pad SubaTM500EMB压花垫;5)垫调节,原位5次扫描/分钟,6psi,3M调节盘;6)向下力1.5;7)浆液流量40ml/min;以及8)Dow ACuPLANETMLK393 5升,H2O2 13ml。这样,减少的H2O2可有助于回收可能已经早先在(使用CMP)对导电结构进行抛光之后凹进的导电材料(诸如铜)。
用于实现可接受的DBI表面的第三方案可包括调节以下约束:1)具有VipR载具的工具Strasbaugh 6EC;2)工作台速度63;3)晶片载具速度57;4)IC 1000;5)垫调节—无有意调节;6)向下力3;7)浆液流量150ml/min;以及8)Dow ACuPLANETMLK393浆液混合物,每升中有13ml的H2O2。这样,调节可有助于实现对多种金属形状和大小的一致平面化。
图11是流程图1100,示出了根据各种实施方案的对用于混合接合的各层进行抛光的示例性方法。在1102处,该方法包括在基板(诸如基板层602)上沉积和图案化电介质层(诸如电介质层604),以在该电介质层中形成开口(诸如开口610)。另外,在1104处,该方法包括在电介质层上方和开口的第一部分内沉积阻挡层(例如,诸如阻挡层606)。在1106处,该方法包括将导电结构(诸如导电结构608)沉积在阻挡层上方和开口的未被阻挡层占据的第二部分内,导电结构的在开口的第二部分中的至少一部分耦接到或接触电路或一个或多个导电结构。沉积导电结构的方法可包括在沉积导电结构之前将晶种层沉积在阻挡层上方。在一个实施方案中,导电结构的在开口中的至少一部分可耦接到或可接触基板内的电路。另外,该方法可包括制备用于接合操作的第一平面接合表面,以及将该第一平面接合表面与第二平面接合表面接合。例如,通过使接合的结构在低于400℃的温度下退火,可在接合之后在导电结构(诸如导电结构608)与另一导电结构之间形成电连接。在一个实施方案中,可使接合结构在低于350℃的温度下退火。
此外,可通过本文所公开的方法制备任何数量的晶片,然后进行堆叠。例如,第一晶片和第二晶片(诸如,第一晶片102和/或第二晶片306)可以被准备并发现是平面的,并且可以被相应地堆叠(例如,第一晶片102的接合表面可以与第二晶片306的接合表面接合)。任何数量的附加晶片可堆叠在堆叠的第一晶片和第二晶片(诸如第一晶片102和/或第二晶片306)的顶部上或下方(并与堆叠的第一晶片和第二晶片接合)。在一个实施方案中,接合表面准备步骤可包括清洁第一晶片和第二晶片两者的接合表面,以及将第一晶片和/或第二晶片的经清洁的表面暴露于氮或卤化物等离子体。此外,接合的晶片的第二表面(即,未接合的表面)(诸如第一电介质层502和/或第二电介质层506的表面)可被平面化,以准备好用于后续接合。
另外,可使用没有粘合剂的直接接合技术,使用金属至金属扩散接合,或两者(例如,混合接合)来接合基板的接合表面和另一基板的接合表面。此外,接合表面和导电结构的组合表面粗糙度可小于1nm均方根(RMS)。
在一个实施方案中,任何两个相邻的接合晶片(诸如第一晶片102和第二晶片306之间)的CTE可以是不同的。例如,第一电介质层的材料的CTE可以是第二电介质层的材料的CTE的两(2)倍。另外,电介质层的宽度可以是不同的。例如,在一个实施方案中,第二晶片306可包括其中已形成接合表面的分段基板或管芯,并且准备好的接合表面可与另一晶片(诸如第一晶片102)的准备好的表面紧密接合。另外,可对接合的管芯的后表面进行平面化,使得经平面化的后表面可被清洁并准备好用于后续附加接合。这样,可形成多个管芯堆叠。
在1108处,该方法包括对导电结构进行抛光以显露出沉积在电介质层上方而不是开口的第二部分中的阻挡层部分,使得导电结构不会凹陷(或凹进)到在由沉积在电介质层上方而不是开口的第二部分中的阻挡层部分限定的平面下方超过10nm。
在1110处,该方法包括用选择性抛光来对阻挡层进行抛光,以在电介质层上或电介质层处显露出接合表面,而不会使与开口的第二部分中的导电结构相邻的电介质表面圆化。
应当理解的是,流程图1100可在上述附图中的任一者的上下文中操作。例如,以减小导电结构凹进的方式对导电结构进行抛光和/或以减少电介质侵蚀的方式对阻挡层进行抛光,可使用图7的工艺(诸如通过修改电介质层702和导电结构706的抛光速率来实现稳态)、图8的垫布局(其可考虑金属密度、垫的CD,以及垫之间的节距),以及图9的垫布局(其可考虑垫布局的图案)中的一者或多者。这样,图11的方法可应用于上述附图中的任一者的上下文中。
如本文所公开的,对导电结构进行抛光可包括维持一致的导电结构去除速率。另外,对导电结构进行抛光可通过反应性液体浆液来控制。对阻挡层进行抛光可包括去除任何过量的阻挡层,并且可包括同时去除导电材料的至少一部分、阻挡层的至少一部分和电介质层的至少一部分。此外,与对阻挡层进行抛光相关联的去除速率可控制导电结构的深度和电介质层的倾斜度。
与对阻挡层进行抛光相关联的选择性可控制导电结构的深度和电介质层的倾斜度。例如,选择性可以是两种不同材料的去除速率的比率。导电结构对电介质层的选择性可为导电结构(诸如铜)的去除速率除以电介质层(诸如氧化物)的去除速率的比率。
选择性还可包括修改金属层参数,金属层参数包括阻挡金属的类型、阻挡金属的厚度或阻挡金属的侵蚀速率中的至少一者。例如,阻挡金属的类型可包括与Cabot EPOCHC8902铜浆液一起使用的钛,或与Dow ACuPLANETMLK393浆液一起使用的钛或钽中的至少一种。选择性可包括修改抛光消耗品,该抛光消耗品包括抛光垫、浆液类型、浆液流量、浆液稀释度、抛光压力或调节盘(conditioning disc)类型中的至少一者。抛光垫可包括SubaTM500或DOW IC1000TM型垫中的一者。另外,选择性可包括修改抛光参数,抛光参数包括台板速度、晶片载具速度、浆液流量、向下力或垫调节类型中的至少一者。例如,增加浆液流量可使导电材料的凹进减少,或降低浆液流量可使导电材料的凹进增加。
结论
尽管已经用结构特征和/或方法动作专用的语言描述了本公开的实施方式,但是应当理解,这些实施方式不必限于所描述的特定特征或动作。相反,公开了特定特征和动作作为实现示例性装置和技术的代表性形式。
本文档的每个权利要求构成单独的实施方案,并且组合不同权利要求和/或不同实施方案的实施方案在本公开的范围内,并且在阅读本公开后对于本领域普通技术人员将是显而易见的。
Claims (21)
1.一种方法,包括:
在基板的电介质层的表面上形成一个或多个预定开口,所述开口中的至少一者的宽度是至少5微米;
在所述电介质层的所述表面和所述开口上方形成阻挡层;
在所述阻挡层的上方和所述开口内形成导电结构;
对所述导电结构的至少一部分进行抛光以显露出所述阻挡层的表面;以及
对所述阻挡层进行抛光以显露出表面粗糙度小于1nm的平面电介质接合表面,并且使得所述导电结构从所述接合表面凹陷小于20nm。
2.根据权利要求1所述的方法,其中所述导电结构的在所述开口中的至少一部分耦接到或接触所述基板内的电路或导电结构。
3.一种方法,包括:
在基板的电介质层的表面中形成开口;
在所述电介质层的所述表面上方和所述开口内形成阻挡层;
在所述阻挡层的所述表面上方和所述开口内形成导电结构;
对所述导电结构的至少一部分进行抛光以显露出所述阻挡层的表面,使得所述导电结构的在所述开口内的至少一部分从所述阻挡层的在所述电介质层的所述表面上方的一部分凹陷第一预定量,所述导电结构中的至少一者的宽度为至少5微米并且所述导电结构的布置的节距是所述导电结构的所述宽度的至少1.2倍;以及
对所述阻挡层进行抛光以暴露出所述电介质层的接合表面,使得所述导电结构凹陷第二预定量,所述第二预定量在所述电介质层的所述接合表面下方小于20nm。
4.根据权利要求3所述的方法,其中所述导电结构的在所述开口中的至少一部分耦接到或接触所述基板内的电路或导电结构。
5.根据权利要求3所述的方法,还包括在所述导电层的沉积之前将晶种层涂覆在所述阻挡层上。
6.一种形成具有导电结构阵列的电介质接合表面的方法,包括:
在所述基板的电介质层中形成一个或多个预定的开口阵列;
在所述电介质层上方,包括在所述开口内形成阻挡层;
在所述阻挡层上方形成导电材料;
对所述导电材料的一部分进行抛光以显露出所述阻挡层的表面并形成具有在所述阻挡层的所述表面下方的第一预定凹陷处的表面的导电结构,所述导电结构的宽度为5-50微米,并且所述导电结构的阵列的图案密度小于30%;以及
对所述阻挡层进行抛光以显露出平面电介质接合表面并在所述平面电介质接合表面下方的所述导电结构中形成第二预定凹陷。
7.根据权利要求6所述的方法,其中所述第一预定凹陷等于或大于所述第二预定凹陷,并且所述第二预定凹陷小于20nm。
8.根据权利要求6所述的方法,其中所述基板是第一基板,所述方法还包括将所述第一基板的所述平面电介质接合表面接合到第二基板的准备好的平面接合表面。
9.根据权利要求8所述的方法,其中所述第二基板小于所述第一基板。
10.根据权利要求8所述的方法,其中所述第一基板的所述导电结构的阵列中的局部垫金属密度大于5%且小于50%。
11.一种部件,包括:
第一基板,所述第一基板至少包括第一平面电介质层,所述第一平面电介质层包括各自具有至少5微米的宽度的导电结构的布置;和
第二基板,所述第二基板至少包括第二平面电介质层,所述第二平面电介质层与所述第一电介质层直接接合,所述第二平面电介质层包括导电结构的布置,所述第二基板上的所述导电结构中的至少一个与所述第一基板上的所述导电结构中的至少一个接触,
其中所述第一基板上的所述导电结构的所述布置的节距是所述基板上的所述导电结构中的至少一个的宽度的至少1.2倍。
12.根据权利要求11所述的部件,其中在相对于介于所述第一基板与所述第二基板之间的接合界面的第一区域中提供所述第一基板和所述第二基板上的导电结构的所述布置,所述部件还包括相对于介于所述第一基板与所述第二基板之间的接合界面的第二区域,其中沿着所述接合界面没有导电结构。
13.根据权利要求12所述的部件,其中所述第一区域位于相对于并沿着介于所述第一基板与所述第二基板之间的接合界面的中心区域中。
14.根据权利要求12所述的部件,其中所述中心区域包括所述接合界面的所述面积的小于一半。
15.根据权利要求11所述的部件,其中所述第一导电结构的所述布置是第一布置,所述第一基板具有第二导电结构的第二布置,其中所述第一导电结构的所述第一布置的节距不同于所述第一基板上的第二导电结构的所述第二布置的节距。
16.根据权利要求15所述的部件,其中所述第一布置中的所述第一导电结构的至少一个的宽度不同于所述第二布置中的所述第二结构的至少一个的宽度。
17.根据权利要求11所述的部件,其中所述第一基板和所述第二基板上的导电结构的所述布置在所述第二导电结构中的至少一些之间是不规律的。
18.根据权利要求11所述的部件,其中所述第二基板包括微电子存储器件。
19.根据权利要求11所述的部件,其中所述导电结构由铜、铜合金或镍构成。
20.根据权利要求11所述的部件,其中在所述第一基板与所述第二基板之间的界面包含氮。
21.根据权利要求16所述的部件,其中所述第一布置与所述第二布置相隔一定距离,所述距离不同于所述第一布置的所述节距或所述第二布置的所述节距。
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