TWI492350B - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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Publication number
TWI492350B
TWI492350B TW101143204A TW101143204A TWI492350B TW I492350 B TWI492350 B TW I492350B TW 101143204 A TW101143204 A TW 101143204A TW 101143204 A TW101143204 A TW 101143204A TW I492350 B TWI492350 B TW I492350B
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Taiwan
Prior art keywords
conductive
wafer
line
circuit
semiconductor
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TW101143204A
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English (en)
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TW201421631A (zh
Inventor
詹前峰
林畯棠
賴顗喆
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW101143204A priority Critical patent/TWI492350B/zh
Priority to CN201210509778.6A priority patent/CN103839899B/zh
Priority to US13/753,930 priority patent/US8952528B2/en
Publication of TW201421631A publication Critical patent/TW201421631A/zh
Priority to US14/604,128 priority patent/US9269693B2/en
Application granted granted Critical
Publication of TWI492350B publication Critical patent/TWI492350B/zh

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Description

半導體封裝件及其製法
本發明係關於一種半導體封裝件及其製法，尤指一種可降低翹曲現象之半導體晶片堆疊封裝件及其製法。
隨著時代的進步，現今電子產品均朝向微型化、多功能、高電性及高速運作的方向發展，為了配合此一發展趨勢，半導體業者莫不積極研發體積微小、高性能、高功能、與高速度化的半導體封裝件，藉以符合電子產品之需求。
一般而言，為了使半導體封裝件具有體積微小、高性能、多功能、與高速度化之特性與功效，半導體晶片傾向採用覆晶封裝技術。這是因為覆晶技術有縮小晶片封裝面積及縮短訊號傳輸路徑等優點，且目前已經廣泛應用於晶片封裝領域，例如晶片直接貼附(Direct Chip Attached，DCA)、封裝晶片尺寸構裝(Chip Scale Package，CSP)以及多晶片模組(Multi-Chip Module，MCM)封裝等型態的封裝。
為了更進一步發揮上述半導體封裝件之特性與功效及微小化優點，業界遂提出將晶片疊層之封裝技術，但目前晶片疊層技術常碰到因熱應力所產生之翹曲問題，而另一技術：晶粒、晶圓、及封裝基板之疊層技術存在需克服後續製程中與導電凸塊連接時，因熱應力導致導電凸塊破裂或產生孔隙之問題。
第1A至1C圖所示者，係習知技術之半導體封裝件及 其製法之剖面示意圖。
如第1A圖所示，提供具有相對之晶片第一表面10a與晶片第二表面10b之半導體晶圓10，該半導體晶圓10包含複數半導體晶片10’，且該半導體晶圓10內具有複數導電柱10c，於該半導體晶圓10之晶片第一表面10a上設有複數線路連接板11，且各該線路連接板11具有相對之第一表面11a與第二表面11b及貫穿該第一表面11a與第二表面11b的第一導電通孔11c，並藉由複數第一導電元件12使各該線路連接板11之第二表面11b上之第一導電通孔11c與該半導體晶圓10之導電柱10c對應連接。
此外，於該線路連接板11之第一表面11a上設有半導體晶片14，且各該半導體晶片14之底面14a與各該線路連接板11之第一表面11a間係藉由第二導電元件13電性連接，並於該半導體晶圓10之晶片第一表面10a上形成有封裝膠體15，以包覆該線路連接板11、半導體晶片14、第一導電元件12及第二導電元件13。
如第1B圖所示，係接續自第1A圖之製程，研磨該半導體晶圓10之晶片第二表面10b，使該半導體晶圓10之導電柱10c之一端外露，且於該半導體晶圓10之晶片第二表面10b上形成有線路重佈層16，該半導體晶圓10與該線路重佈層16係組合成一線路重佈結構，並於該線路重佈層16上接置有複數導電凸塊17。
如第1C圖所示，係接續自第1B圖之製程，進行切單步驟，並藉由該導電凸塊17以接置於一基板18之頂面18a 上，而該基板18之底面18b係與銲球17’連接。
不過，前述習知之半導體封裝件之製法於封裝時，會因於高溫製程時而產生熱應力，而該熱應力將使得該線路重佈結構與該線路連接板翹曲，因而部份該第一導電元件未確實接合於該半導體晶片與該線路重佈結構之間，又部份該第二導電元件亦未確實接合於該線路重佈結構與該線路連接板之間，導致該第一導電元件與線路連接板處形成空隙或產生虛銲現象，進而使該第一導電元件、線路連接板與半導體晶片間之電性連接失效。
因此，如何克服習知技術之種種問題，實為一重要課題。
為解決上述習知技術之種種問題，本發明遂揭露一種半導體封裝件，係包括：半導體晶片，係具有相對的晶片第一表面與晶片第二表面；線路重佈結構，係設於該半導體晶片之晶片第一表面上，且具有相對的第一表面與第二表面與貫穿該第一表面與第二表面之第一導電通孔，該第一表面上形成有線路重佈層，而該第二表面與該半導體晶片間係藉由複數第一導電元件電性連接；複數導電凸塊，係電性接置於該線路重佈層上；以及封裝膠體，係形成於該半導體晶片之晶片第一表面上，且包覆該線路重佈結構，各該導電凸塊係嵌入且外露於該封裝膠體。
本發明又提供一種半導體封裝件之製法，係包括：提供一具有複數半導體晶片之半導體晶圓，其具有相對的晶 片第一表面與晶片第二表面；以及於該半導體晶圓之半導體晶片之晶片第一表面上設置一線路重佈結構並於該半導體晶片之晶片第一表面上形成封裝膠體，且該線路重佈結構具有貫穿其相對之第一與第二表面的第一導電通孔，而該線路重佈結構之第一表面上設有線路重佈層，並於該線路重佈層上電性接置有複數導電凸塊，該半導體晶片之晶片第一表面與該線路重佈結構第二表面之間係藉由第一導電元件電性連接，該封裝膠體包覆該線路重佈結構及該線路重佈層，各該導電凸塊係嵌入且外露於該封裝膠體。
前述之半導體封裝件之製法中，形成嵌入且外露於該封裝膠體之該導電凸塊的步驟係包括：於該線路重佈層上電性接置該些導電凸塊；以及於該半導體晶片之晶片第一表面上形成包覆該線路重佈結構之該封裝膠體，並外露該導電凸塊於該封裝膠體。
前述之半導體封裝件之製法中，形成嵌入且外露於該封裝膠體之該導電凸塊的步驟係包括：於該線路重佈層上電性接置該些導電凸塊；於該半導體晶片之晶片第一表面上形成包覆該線路重佈結構與該些導電凸塊之該封裝膠體；以及研磨移除部分該封裝膠體與導電凸塊，俾使該導電凸塊齊平於該封裝膠體表面。
前述之半導體封裝件之製法中，形成嵌入且外露於該封裝膠體之該導電凸塊的步驟係包括：於該半導體晶片之晶片第一表面上形成包覆該線路重佈結構之該封裝膠體； 形成複數外露部分該線路重佈層的封裝膠體開孔；以及於各該封裝膠體開孔中電性接置各該導電凸塊。
前述之半導體封裝件之製法中，於該線路重佈結構之第二表面與該半導體晶片之間復設有一線路連接板或相互堆疊之複數線路連接板，該線路連接板係具有貫穿之複數第二導電通孔，該線路連接板與該半導體晶片間係藉由第二導電元件電性連接，且該線路重佈結構之第二表面與該線路連接板之間係藉由該些第一導電元件電性連接，該封裝膠體復包覆該線路連接板。
前述之半導體封裝件之製法中，復包括切單步驟，並於進行切單步驟之後，復包括藉由該些導電凸塊以接置於基板上，並於該線路重佈層與該基板間形成底膠。
依上所述，本發明之半導體封裝件係於線路重佈結構上先形成有線路重佈層，並將該線路重佈結構接置於半導體晶圓上，再電性接置導電凸塊之後，於半導體晶圓上形成有封裝膠體，且該封裝膠體包覆該線路重佈結構及該線路重佈層，並且該半導體晶圓之晶片第二表面外露於外部，因此，本發明之技術可解決習知技術於高溫製程時，該半導體封裝件內部產生之熱能無法快速排出至外部，導致該半導體封裝件翹曲，造成該半導體封裝件內部之電性連接不完全的虛銲現象；再者，本發明之半導體封裝件的製程步驟少且簡單，因此可降低製程成本，並使良率提高。
以下藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「頂」、「底」、「一」、「二」、「三」及「四」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第一實施例
以下將配合第2A至2E圖以詳細說明本發明之半導體封裝件及其製法之第一實施例的剖面示意圖。
如第2A圖所示，提供一半導體晶圓20，該半導體晶圓20包含複數半導體晶片20’，且具有相對之晶片第一表面20a與晶片第二表面20b，於該半導體晶圓20之晶片第一表面20a上設有線路重佈結構21，且該線路重佈結構21具有相對之第一表面21a與第二表面21b、以及貫穿該第一表面21a與該第二表面21b的第一導電通孔21c，於該線路重佈結構21之第一表面21a上形成有線路重佈層22。
於本實施例中，於該線路重佈結構21之第二表面21b 與該半導體晶圓20之晶片第一表面20a間復設一具有相對之第三表面24a與第四表面24b之線路連接板24，而該線路連接板24係具有貫穿該第三表面24a與該第四表面24b之第二導電通孔24c，另外，該線路連接板24係可具有主動元件晶片(如記憶晶片、射頻晶片、邏輯晶片、類比晶片或被動元件晶片)之功能。又於該線路重佈結構21之第二表面21b與該線路連接板24之第三表面24a間係藉由第一導電元件23電性連接，且該第一導電元件23係對應該第一導電通孔21c與該第二導電通孔24c，再利用第二導電元件25電性連接該線路連接板24之第四表面24b與該半導體晶圓20之晶片第一表面20a，使該第二導電元件25對應該第二導電通孔24c，更詳之，該第一導電元件23或該第二導電元件25係各自選自導電柱、導電球或導電凸塊。另外，該線路重佈結構21之尺寸係大於或等於該線路連接板24之尺寸，且該線路重佈結構21與該線路連接板24之材質係為矽(Si)、碳化矽(SiC)、砷化鎵(GaAs)、二氧化矽(例如水晶、玻璃)、三氧化二鋁(例如藍寶石)、或其類似物的半導體晶圓。
復請參閱第2B圖，係延續自第2A圖，於該半導體晶圓20之晶片第一表面20a上形成有封裝膠體26，且該封裝膠體26包覆該線路重佈結構21、線路重佈層22及線路連接板24。
如第2C圖所示，係接續自第2B圖之製程，藉由雷射或蝕刻方式形成複數外露部分該線路重佈層22的封裝膠 體開孔26a，並於該等封裝膠體開孔26a中設置複數導電凸塊27，而各該導電凸塊27係電性連接該線路重佈層22、嵌入且外露於該封裝膠體26。
如第2D圖所示，係接續自第2C圖之製程，進行切單步驟，更進一步來說，外露之該半導體晶片20’可幫助整體半導體封裝件之散熱，以避免半導體封裝件因高溫產生熱應力，導致該整體封裝件有翹曲之現象，使得該線路重佈結構21、線路連接板24及半導體晶片20’之間相互的電性連接不完全，造成虛銲現象。
如第2E圖所示，係接續自第2D圖之製程，藉由該導電凸塊27以電性接置於一例如印刷電路板(PCB)之基板28之頂面上，並於該線路重佈層22與該基板28之頂面間形成底膠29，且可於該基板28之底面接置複數銲球27’，以供外界電性連接。
第二實施例
以下將配合第3A至3E圖以詳細說明本發明之半導體封裝件及其製法之第二實施例的剖面示意圖。
如第3A圖所示，提供一半導體晶圓30，且該半導體晶圓30包含複數半導體晶片30’，且具有相對之晶片第一表面30a與晶片第二表面30b，於該半導體晶圓30之晶片第一表面30a上設有線路重佈結構31，且該線路重佈結構31具有相對之第一表面31a與第二表面31b、以及貫穿該第一表面31a與該第二表面31b的第一導電通孔31c，於該線路重佈結構31之第一表面31a上形成有線路重佈層 32。
於本實施例中，於該線路重佈結構31之第二表面31b與該半導體晶圓30之晶片第一表面30a間設置有一具有相對之第三表面34a與第四表面34b之線路連接板34，而該線路連接板34係具有貫穿該第三表面34a與該第四表面34b之第二導電通孔34c。再者，於該線路重佈結構31之第二表面31b與該線路連接板34之第三表面34a間係藉由第一導電元件33電性連接，且該第一導電元件33係對應該第一導電通孔31c與該第二導電通孔34c，再利用第二導電元件35電性連接該線路連接板34之第四表面34b與該半導體晶圓30之晶片第一表面30a，使該第二導電元件35對應該第二導電通孔34c，並且於該線路重佈層32上係電性接置有複數導電凸塊36。更詳之，該第一導電元件33與該第二導電元件35係各自選自導電凸塊、導電球或導電柱，而該線路連接板34亦可額外具有主動元件晶片(如記憶晶片、射頻晶片、邏輯晶片、類比晶片或被動元件晶片)之功能。
復請參閱第3B圖，係延續自第3A圖，於該半導體晶圓30之晶片第一表面30a上形成有封裝膠體37，且該封裝膠體37包覆該線路重佈結構31、線路連接板34、線路重佈層32及該等導電凸塊36。
或者，如第3B’圖所示，係第3B圖之另一實施態樣，於該半導體晶圓30之晶片第一表面30a上形成有封裝膠體37，且該封裝膠體37包覆該線路重佈結構31、線路重佈 層32、線路連接板34及部分該等導電凸塊36，並使一部分該導電凸塊36外露。
如第3C圖所示，係接續自第3B圖之製程，以研磨方式移除部分該封裝膠體37與該等導電凸塊36，俾使該等導電凸塊36齊平於該封裝膠體37表面。
如第3D圖所示，係接續自第3C圖之製程，接著，進行切單步驟，而外露之該半導體晶片30’並可提供較佳的散熱能力。
或者，如第3D’圖所示，係接續自第3B’圖，進行切單步驟。
如第3E圖所示，係接續自第3D圖之製程，藉由該導電凸塊36以電性接置於一例如印刷電路板(PCB)之基板39之頂面上，且於該基板39之底面接置複數銲球36’，以供外界電性連接。
或者，如第3E’圖所示，係接續自第3D’圖，藉由該導電凸塊36以接置於一基板39之頂面上，且於該基板39之底面接置複數銲球36’，以供外界電性連接。
第三實施例
請參閱第4圖，係本發明之之半導體封裝件之第三實施例的剖面示意圖。本實施例與第一實施例之主要差異在於：本實施例不具有該線路連接板24，該半導體晶片20’之晶片第一表面20a與線路重佈結構21之第二表面21b間係利用該第一導電元件23電性連接。至於其它相關製程均類似，故不再贅述。
第四實施例
請參閱第5圖，係本發明之半導體封裝件之第四實施例的剖面示意圖。本實施例與第一實施例之差異主要在於：該半導體晶片20’之晶片第一表面20a與線路重佈結構21之第二表面21b間係設有相互堆疊之複數該線路連接板24。至於其它相關製程均類似，故不再贅述。
本發明復提供一種半導體封裝件，係包括：半導體晶片20’、線路重佈結構21、複數導電凸塊27及封裝膠體26。
該半導體晶片20’係具有相對晶片第一表面20a與晶片第二表面20b，更詳而言之，該半導體晶片20’包括複數晶片。
根據前述之半導體封裝件，該線路重佈結構21係具有相對之第一表面21a與第二表面21b，並設於該半導體晶片20’之晶片第一表面20a上，且具有貫穿該第一表面21a與該第二表面21b間之第一導電通孔21c，而該線路重佈結構21之第二表面21b與該半導體晶片20’之晶片第一表面20a間係藉由該第一導電元件23電性連接，於該線路重佈結構21之第一表面21a上形成有線路重佈層22。
於前述之半導體封裝件中，該封裝膠體26係形成於該半導體晶片20’之第一表面20a上，且包覆該線路重佈結構21及該線路重佈層22，而各該導電凸塊27係電性接置於該線路重佈層22上，又各該導電凸塊27係嵌入且外露於該封裝膠體26，或者該導電凸塊36係外露齊平或外 露半齊平於該封裝膠體37，又該封裝膠體26兩側係外露且齊平於該半導體晶片20’兩側。
此外，該線路重佈結構21之第二表面21b與該半導體晶片20’之晶片第一表面20a間復設有一該線路連接板24，或者於該線路重佈結構21之第二表面21b與該半導體晶片20’之晶片第一表面20a間復設有相互堆疊之複數該線路連接板24，而該線路連接板24係具有相對之第三表面24a與第四表面24b、及貫穿該第三表面24a與該第四表面24b的第二導電通孔24c，而該線路連接板24與該半導體晶片20’之晶片第一表面20a間係藉由第二導電元件25電性連接，且該線路重佈結構21之第二表面21b與該線路連接板24間係藉由該第一導電元件23電性連接，該封裝膠體26亦復包覆該線路連接板24。
另外，該線路重佈結構21與該線路連接板24之材質係為矽(Si)、碳化矽(SiC)、砷化鎵(GaAs)、二氧化矽(例如水晶、玻璃)、三氧化二鋁(例如藍寶石)或其類似物的半導體晶圓。該封裝膠體26係為高分子材料、樹脂材料、聚亞醯胺、氧化矽、環氧化物、苯并環丁烯(benzocyclobutenes,BCB)、Silk TM(Dow Chemical)或其組合。
又，本發明之半導體封裝件復包括例如印刷電路板(PCB)之基板28，而該線路重佈層22上之該導電凸塊27係電性接置於該基板28上，且該基板28與該線路重佈層22之接置面之相對表面上係電性連接複數銲球27’，並於 該線路重佈層22與該基板28間形成有底膠29。
綜上所述，本發明之半導體封裝件係於線路重佈結構上先形成有線路重佈層，並將該線路重佈結構接置於半導體晶圓上，再接置導電凸塊，之後於半導體晶圓上形成有封裝膠體，且該封裝膠體包覆該線路重佈結構及該線路重佈層，並且該半導體晶圓之晶片第二表面外露於外部，因此，本發明之技術可解決習知技術於高溫製程時，該半導體封裝件內部產生之熱能無法快速排出至外部，導致該半導體封裝件翹曲，造成該半導體封裝件內部之電性連接不完全的虛銲現象；再者，本發明之半導體封裝件的製程步驟少且簡單，因此可降低製程成本，並使良率提高。
上述該等實施樣態僅例示性說明本發明之功效，而非用於限制本發明，任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述該等實施態樣進行修飾與改變。此外，在上述該等實施態樣中之元件的數量僅為例示性說明，亦非用於限制本發明。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
10、20、30‧‧‧半導體晶圓
10a、20a、30a‧‧‧晶片第一表面
10b、20b、30b‧‧‧晶片第二表面
10c‧‧‧導電柱
10’、14、20’、30’‧‧‧半導體晶片
11a、21a、31a‧‧‧第一表面
11b、21b、31b‧‧‧第二表面
11c、21c、31c‧‧‧第一導電通孔
12、23、33‧‧‧第一導電元件
13、25、35‧‧‧第二導電元件
11、24、34‧‧‧線路連接板
14a、18b‧‧‧底面
15、26、37‧‧‧封裝膠體
16、22、32、42、52‧‧‧線路重佈層
17、27、36‧‧‧導電凸塊
17’、27’、36’‧‧‧銲球
18、28、39‧‧‧基板
18a‧‧‧頂面
21、31‧‧‧線路重佈結構
24a、34a‧‧‧第三表面
24b、34b‧‧‧第四表面
24c、34c‧‧‧第二導電通孔
26a‧‧‧封裝膠體開孔
29‧‧‧底膠
第1A至1C圖係習知半導體封裝件及其製法之剖面示意圖；第2A至2E圖係為本發明之半導體封裝件及其製法之第一實施例的剖面示意圖；第3A至3E圖係為本發明之半導體封裝件及其製法之第二實施例的剖面示意圖，其中，第3B’圖係第3B’圖之另 一實施態樣，第3D’與3E’圖係第3B’圖之後續步驟；第4圖係為本發明之半導體封裝件之第三實施例的剖面示意圖：以及第5圖係為本發明之半導體封裝件之第四實施例的剖面示意圖。
20’‧‧‧半導體晶片
20a‧‧‧晶片第一表面
20b‧‧‧晶片第二表面
21‧‧‧線路重佈結構
21a‧‧‧第一表面
21b‧‧‧第二表面
21c‧‧‧第一導電通孔
22‧‧‧線路重佈層
23‧‧‧第一導電元件
24‧‧‧線路連接板
24a‧‧‧第三表面
24b‧‧‧第四表面
24c‧‧‧第二導電通孔
25‧‧‧第二導電元件
26‧‧‧封裝膠體
26a‧‧‧封裝膠體開孔
27‧‧‧導電凸塊

Claims (20)

  1. 一種半導體封裝件，係包括：半導體晶片，係具有相對的晶片第一表面與晶片第二表面；線路重佈結構，係設於該半導體晶片之晶片第一表面上，且具有相對的第一表面與第二表面與貫穿該第一表面與第二表面之第一導電通孔，該第一表面上形成有線路重佈層，而該第二表面與該半導體晶片間係藉由複數第一導電元件電性連接；複數導電凸塊，係電性接置於該線路重佈層上；以及封裝膠體，係形成於該半導體晶片之晶片第一表面上，且包覆該線路重佈結構，各該導電凸塊係嵌入且外露於該封裝膠體，又該封裝膠體兩側齊平於該半導體晶片兩側。
  2. 如申請專利範圍第1項所述之半導體封裝件，復包括一線路連接板或相互堆疊之複數線路連接板，係設於該線路重佈結構之第二表面與該半導體晶片間，該線路連接板係具有貫穿之第二導電通孔，該線路連接板與該半導體晶片表面間係藉由第二導電元件電性連接，且該線路重佈結構之第二表面與該線路連接板之間係藉由該些第一導電元件電性連接，該封裝膠體復包覆該線路連接板。
  3. 如申請專利範圍第2項所述之半導體封裝件，其中， 該線路連接板係具有主動元件晶片或被動元件晶片之功能。
  4. 如申請專利範圍第2項所述之半導體封裝件，其中，該第一或第二導電元件係各自選自導電柱、導電球或導電凸塊。
  5. 如申請專利範圍第1項所述之半導體封裝件，復包括基板，該線路重佈層係藉由該些導電凸塊以接置於該基板上，並於該線路重佈層與該基板間形成有底膠。
  6. 如申請專利範圍第5項所述之半導體封裝件，其中，該基板與該線路重佈層之接置面之相對表面上係電性連接複數銲球。
  7. 如申請專利範圍第1項所述之半導體封裝件，其中，該些導電凸塊係外露半齊平於該封裝膠體。
  8. 如申請專利範圍第1項所述之半導體封裝件，其中，該封裝膠體兩側係外露於該半導體晶片兩側。
  9. 如申請專利範圍第1項所述之半導體封裝件，其中，該些導電凸塊係外露齊平於該封裝膠體。
  10. 如申請專利範圍第2項所述之半導體封裝件，其中，該線路重佈結構與該線路連接板之材質係為矽、碳化矽、砷化鎵、二氧化矽或三氧化二鋁。
  11. 如申請專利範圍第1項所述之半導體封裝件，其中，該線路重佈結構的第一導電通孔係電性連接該線路重佈層。
  12. 一種半導體封裝件之製法，係包括： 提供一具有複數半導體晶片之半導體晶圓，其具有相對的晶片第一表面與晶片第二表面；以及於該半導體晶圓之半導體晶片之晶片第一表面上設置一線路重佈結構並於該半導體晶片之晶片第一表面上形成封裝膠體，且該線路重佈結構具有貫穿其相對之第一與第二表面的第一導電通孔，而該線路重佈結構之第一表面上設有線路重佈層，並於該線路重佈層上電性接置有複數導電凸塊，該半導體晶片之晶片第一表面與該線路重佈結構第二表面之間係藉由第一導電元件電性連接，該封裝膠體包覆該線路重佈結構及該線路重佈層，各該導電凸塊係嵌入且外露於該封裝膠體。
  13. 如申請專利範圍第12項所述之半導體封裝件之製法，其中，形成嵌入且外露於該封裝膠體之該些導電凸塊的步驟係包括：於該線路重佈層上電性接置該些導電凸塊；以及於該半導體晶片之晶片第一表面上形成包覆該線路重佈結構之該封裝膠體，並外露該些導電凸塊於該封裝膠體。
  14. 如申請專利範圍第12項所述之半導體封裝件之製法，其中，形成嵌入且外露於該封裝膠體之該導電凸塊的步驟係包括：於該線路重佈層上電性接置該些導電凸塊；於該半導體晶片之晶片第一表面上形成包覆該線 路重佈結構與該些導電凸塊之該封裝膠體；以及研磨移除部分該封裝膠體與導電凸塊，俾使各該導電凸塊齊平於該封裝膠體表面。
  15. 如申請專利範圍第12項所述之半導體封裝件之製法，其中，形成嵌入且外露於該封裝膠體之該些導電凸塊的步驟係包括：於該半導體晶片之晶片第一表面上形成包覆該線路重佈結構之該封裝膠體；形成複數外露部分該線路重佈層的封裝膠體開孔；以及於各該封裝膠體開孔中電性接置各該導電凸塊。
  16. 如申請專利範圍第15項所述之半導體封裝件之製法，其中，該封裝膠體開孔係藉由雷射或蝕刻方式形成。
  17. 如申請專利範圍第12項所述之半導體封裝件之製法，其中，於該線路重佈結構之第二表面與該半導體晶片之間復設有一線路連接板或相互堆疊之複數線路連接板，該線路連接板係具有貫穿之複數第二導電通孔，該線路連接板與該半導體晶片間係藉由第二導電元件電性連接，且該線路重佈結構之第二表面與該線路連接板之間係藉由該些第一導電元件電性連接，該封裝膠體復包覆該線路連接板。
  18. 如申請專利範圍第12項所述之半導體封裝件之製法，復包括切單步驟。
  19. 如申請專利範圍第18項所述之半導體封裝件之製法， 於進行切單步驟之後，復包括藉由該些導電凸塊以接置於基板上，並於該線路重佈層與該基板間形成底膠。
  20. 如申請專利範圍第17項所述之半導體封裝件之製法，其中，該線路重佈結構與該線路連接板之材質係為矽、碳化矽、砷化鎵、二氧化矽或三氧化二鋁。
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