TWI536468B - 封裝件之製法 - Google Patents

封裝件之製法 Download PDF

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Publication number
TWI536468B
TWI536468B TW101132954A TW101132954A TWI536468B TW I536468 B TWI536468 B TW I536468B TW 101132954 A TW101132954 A TW 101132954A TW 101132954 A TW101132954 A TW 101132954A TW I536468 B TWI536468 B TW I536468B
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Taiwan
Prior art keywords
package
semiconductor wafer
manufacturing
substrate body
substrate
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TW101132954A
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English (en)
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TW201411745A (zh
Inventor
黃品誠
賴顗喆
Original Assignee
矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW101132954A priority Critical patent/TWI536468B/zh
Priority to CN201210352533.7A priority patent/CN103681374A/zh
Priority to US13/680,728 priority patent/US20140073087A1/en
Publication of TW201411745A publication Critical patent/TW201411745A/zh
Application granted granted Critical
Publication of TWI536468B publication Critical patent/TWI536468B/zh

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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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Description

封裝件之製法
本發明係有關於一種封裝件之製法，尤指一種具有可防翹曲、高散熱、高良率之中介板的半導體封裝件之製法。
隨著時代的進步，現今電子產品均朝向微型化、多功能、高電性及高速運作的方向發展，為了配合此一發展趨勢，半導體業者莫不積極研發體積微小、高性能、高功能、與高速度化的半導體封裝件，藉以符合電子產品之要求。
而為使半導體封裝件具有體積微小、高性能、多功能、與高速度化之特性與功效，半導體晶片傾向採用覆晶封裝技術。由於覆晶技術有縮小晶片封裝面積及縮短訊號傳輸路徑等優點，其目前已經廣泛應用於晶片封裝領域，例如晶片尺寸構裝(Chip Scale Package，CSP)、晶片直接貼附(Direct Chip Attached，DCA)封裝以及多晶片模組(Multi-Chip Module，MCM)封裝等型態的封裝。
為了更進一步發揮上述半導體封裝件之特性與功效優點，業界遂提出將一半導體晶片接置於一矽中介板(Through Silicon Interposer，TSI)之技術，其可將各種不同功能晶片模組體積縮小地封裝在一封裝件，該習知封裝件主要包括：一承載件、一矽中介板、至少一半導體晶片、以及包覆該承載件、矽中介板及半導體晶片之封膠，且該矽中介板與該半導體晶片係以金屬凸塊(μ-bump)電性連接，該矽中介板與承載件係以C4凸塊(C4 bump)電性連 接。
該矽中介板係具有複數個貫穿中介層之導電矽通孔，其中由於矽中介板與半導體晶片的材質接近，因此可以避免熱膨脹係數不匹配所產生的問題。而該技術係將一整片矽晶圓形成有導電矽通孔(Through Silicon Via，TSV)後，再將晶圓欲接置半導體晶片之一側視狀況形成重佈線路層(Redistribution Layer，RDL)，並於該重佈線路層作為電性連接墊之表面形成有金屬凸塊(μ-Bump)，以供連接半導體晶片；且於連接半導體晶片後進行模壓製程，利用模壓材料(Molding Compound，M/C)將半導體晶片包覆其中，並保護該半導體晶片不受外界環境影響。最後將未顯露該矽通孔之晶圓表面進行薄化研磨以顯露該矽通孔，之後再於該顯露之矽通孔表面視狀況形成重佈線路層(亦可不形成重佈線路層)，並於該重佈線路層作為電性連接墊之表面形成有銲球，之後進行切割製程，以形成具半導體晶片之矽中介板模組，之後即可供電性連接基板，但是隨矽中介板上所置放之半導體晶片越來越密集及矽中介板的製作厚度越來越薄，上述習知封裝件製程中矽中介板之金屬相對於矽的比例變大，使得矽中介板變得很容易發生翹曲，影響到整個該封裝件之良率。
雖前述之封裝件係具有整體厚度較以往封裝件更小等優點；惟，卻也有製程過於冗長之缺點，並於薄化該矽晶圓時容易損傷矽通孔，且因製程是直到上凸塊於晶圓背部之矽通孔端部後才真正將矽中介板的矽通孔製作完成， 在上凸塊步驟之前是不容易測試出已損壞之矽通孔，又該矽晶圓於製程中時常會發生翹曲現象，所以容易導致整體封裝件良率降低與成本提高；此外，該封裝材料亦會使得整體散熱能力下降。
因此，如何避免上述習知技術中之種種問題，實已成為目前亟欲解決的課題。
有鑒於上述習知技術之缺失，本發明揭露一種封裝件之製法，係包括：提供一具有相對之第一表面與第二表面之基板本體，該基板本體係具有貫穿該第一表面與第二表面的複數導電通孔，且藉其第二表面之一側接置於一第一承載片上並使該第一承載片不翹曲；於該基板本體之第一表面上電性接置至少一第一半導體晶片；移除該第一承載片；以及將該基板本體之第二表面電性接置於一封裝基板上。
由上可知，因為本發明係使第一承載片不翹曲，所以整體結構不易翹曲；此外，本發明可提早進行測試，以提升整體良率與降低成本；又，本發明以底膠取代習知之模壓(Molding)之封裝材料(Molding Compound)，故可使成本降低，並便於多層堆疊半導體晶片，且因為外露半導體晶片之大部分表面，而能有效增進散熱效果。
復又於基板本體上形成貫穿該第一表面的複數導電通孔，以電性接置於第一半導體晶片，以及於基板本體之第二表面上形成重佈線路結構，以電性接置於封裝基板， 經由適當的基板本體設計，調整其金屬與介質材料及其幾何分佈，能有效匹配(matching)其上之第一半導體晶片及其下之封裝基板之熱膨脹係數(CTE)，亦可再減少封裝時或封裝後之翹曲現象，增加良率、散熱、及可靠度。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「不翹曲」、「平貼」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第1A至1F-4圖所示者，係本發明之封裝件及其製法的剖視圖，其中，第1A’與1A”圖係第1A圖的不同實施態樣，第1F-2、1F-3與1F-4圖係第1F-1圖的不同實施態樣。
如第1A圖所示，提供一具有相對之第一表面10a與第二表面10b之基板本體10，該基板本體10係具有貫穿 該第一表面10a及第二表面10b的導電通孔101，該基板本體10之第二表面10b上可選擇性地形成有電性連接該導電通孔101的重佈線路結構102，該重佈線路結構102上形成有例如為C4 Bump的導電凸塊11，且將該導電凸塊11接置於一第一承載片12上，該基板本體10之第一表面10a上亦可選擇性地形成有電性連接該導電通孔101的重佈線路結構(未圖示)，其中，該基板本體10係為貫矽中介板(Through Silicon Interposer，TSI)，且該導電通孔101係為矽通孔(through silicon via，TSV)；或者，該基板本體10之材質可為矽(Si)、砷化鎵(GaAs)、碳化矽(SiC)、玻璃(Glass)、或該基板本體10可為絕緣體上半導體(semiconductor-on-insulator，SOI)或者上述任二材料以上之堆疊層組合，其高度約20至180微米(μm)，例如，該基板本體10係為貫玻璃中介板，且該些導電通孔101係為玻璃穿孔，該第一承載片12係為UV光解膠膜(UV Release Tape)，該重佈線路結構102中之介電材料係可不同於該基板本體10中之介電材料。
或者，如第1A’圖所示，該基板本體10亦可不需該導電凸塊11而直接接置於該第一承載片12上。
或者，如第1A”圖所示，該基板本體10之第一表面10a與第二表面10b上可分別形成有電性連接該導電通孔101的重佈線路結構102’與重佈線路結構102。惟以下步驟僅以第1A圖來進行例示。
如第1B圖所示，藉由空氣吸力使該第一承載片12平 貼於一載台13上，以使該第一承載片12不翹曲，本發明亦可用靜電吸力替代該空氣吸力。
如第1C圖所示，於該基板本體10之第一表面10a上接置至少一第一半導體晶片14，該第一半導體晶片14與基板本體10之間係具有例如為μ-Bump的導電凸塊15，以電性連接該第一半導體晶片14與導電通孔101，其中，該第一半導體晶片14可為記憶晶片、射頻晶片、邏輯晶片、類比晶片或被動元件晶片等等。
如第1D圖所示，於該第一半導體晶片14與該基板本體10之第一表面10a之間形成底膠16，該底膠16可含有環氧樹脂混合填充材(Filler)(未圖示)以改變黏滯性(viscosity)、熱膨脹係數(CTE)及硬度，且該填充材係為二氧化矽(SiO2)或三氧化二鋁(Al2O3)顆粒。
如第1E圖所示，移除該第一承載片12，並使該第一半導體晶片14接置於第二承載片17上，並於該導電凸塊11上進行測試步驟，該第二承載片17係為UV光解膠膜(UV Release Tape)。
如第1F-1圖所示，移除該第二承載片17，並將該導電凸塊11接置於一封裝基板18上，以電性連接該封裝基板18與導電通孔101，再於該封裝基板18與該基板本體10的第二表面10b之間形成底膠21，且可視需要地進行切單步驟。
如第1F-2、1F-3與1F-4圖所示，係第1F-1圖之不同實施態樣，其中，第1F-2圖係顯示該第一半導體晶片14 僅有一個的情況，第1F-3圖係顯示於該等第一半導體晶片14上接置至少一第二半導體晶片19的情況，該第一半導體晶片14與該第二半導體晶片19之間形成有底膠22與複數電性連接該第一半導體晶片14與該第二半導體晶片19的導電凸塊23(例如銲球)，第1F-4圖係顯示於其中一該第一半導體晶片14上接置至少一第二半導體晶片19的情況，該第一半導體晶片14與該第二半導體晶片19之間形成有底膠22與複數電性連接該第一半導體晶片14與該第二半導體晶片19的導電凸塊23，其中，該第二半導體晶片19可為記憶晶片、射頻晶片、邏輯晶片、類比晶片或被動元件晶片等等。
要特別注意的是，於第1F-4圖的情況中，由於該第一半導體晶片14與第二半導體晶片19之排列係構成缺口20，因此於使該第一半導體晶片14接置於該第二承載片17上之前，復可包括於該第二承載片17上形成UV光解膠體(UV Release Adhesive)(未圖示)，藉以於該第一半導體晶片14接置於該第二承載片17上時，填補該缺口20以增加穩定性，並於移除該第二承載片17時，一併移除該UV光解膠體。
本發明復提供一種封裝件，係包括：封裝基板18；基板本體10，係具有相對之第一表面10a與第二表面10b、及貫穿該第一表面10a與第二表面10b的複數導電通孔101，且藉其第二表面10b電性接置於該封裝基板18上；至少一第一半導體晶片14，係電性接置於該基板本體10 之第一表面10a上；以及底膠16，係形成於該第一半導體晶片14與該基板本體10之第一表面10a之間。
於前述之封裝件中，復包括底膠21，係形成於該封裝基板18與該基板本體10的第二表面10b之間，且復包括至少一第二半導體晶片19，係接置於該第一半導體晶片14上，又復包括底膠22，係形成於該第一半導體晶片14與該第二半導體晶片19之間。
本發明之該基板本體10係為貫矽中介板(Through Silicon Interposer，TSI)，且該導電通孔101係為矽通孔(through silicon via，TSV)。
於本實施例中，該第一半導體晶片14與基板本體10的第一表面10a之間係具有導電凸塊15，以電性連接該第一半導體晶片14與導電通孔101。
於所述之封裝件中，該封裝基板18與基板本體10的第二表面10b之間係具有導電凸塊11，以電性連接該封裝基板18與導電通孔101。
又於本發明之封裝件中，該第一半導體晶片14與該第二半導體晶片19之間係具有複數導電凸塊23，以電性連接該第一半導體晶片14與該第二半導體晶片19。
本發明之封裝件係可視需要於該基板本體10之第二表面10b上形成有電性連接該導電通孔101的重佈線路結構102，且該封裝基板18係接置於該重佈線路結構102上。
綜上所述，相較於習知技術，由於本發明係使第一承載片不翹曲，所以整體結構不易翹曲；此外，本發明可提 早進行測試，以提升整體良率與降低成本；又，本發明以底膠取代習知之封裝材料，故可使成本降低，並便於多層堆疊半導體晶片，且因為外露半導體晶片之大部分表面，而能有效增進散熱效果。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
10a‧‧‧第一表面
10b‧‧‧第二表面
10‧‧‧基板本體
101‧‧‧導電通孔
102,102’‧‧‧重佈線路結構
11,15,23‧‧‧導電凸塊
12‧‧‧第一承載片
13‧‧‧載台
14‧‧‧第一半導體晶片
16,21,22‧‧‧底膠
17‧‧‧第二承載片
18‧‧‧封裝基板
19‧‧‧第二半導體晶片
20‧‧‧缺口
第1A至1F-4圖所示者係本發明之封裝件及其製法的剖視圖，其中，第1A’與1A”圖係第1A圖的不同實施態樣，第1F-2、1F-3與1F-4圖係第1F-1圖的不同實施態樣。
10‧‧‧基板本體
10a‧‧‧第一表面
10b‧‧‧第二表面
101‧‧‧導電通孔
102‧‧‧重佈線路結構
11,15‧‧‧導電凸塊
14‧‧‧第一半導體晶片
16,21‧‧‧底膠
18‧‧‧封裝基板

Claims (14)

  1. 一種封裝件之製法，係包括：提供一基板本體，該基板本體具有相對之第一表面與第二表面、及貫穿該第一表面及第二表面的複數導電通孔，且該基板本體藉其第二表面之一側接置於一第一承載片上並藉由空氣吸力或靜電吸力使該第一承載片不翹曲；接著，於該基板本體之第一表面上電性接置至少一第一半導體晶片；移除該第一承載片；以及將該基板本體之第二表面電性接置於一封裝基板上。
  2. 如申請專利範圍第1項所述之封裝件之製法，於電性接置至該第一半導體晶片後，該第一半導體晶片與該基板本體之第一表面之間係具有複數導電凸塊，以電性連接該第一半導體晶片與該基板本體。
  3. 如申請專利範圍第1項所述之封裝件之製法，其中，復包括於該第一半導體晶片與該基板本體之第一表面之間形成底膠。
  4. 如申請專利範圍第1項所述之封裝件之製法，其中，於該基板本體之第二表面電性接置於該封裝基板上後，該封裝基板與該基板本體之第二表面之間係具有複數導電凸塊，以電性連接該封裝基板與該基板本體。
  5. 如申請專利範圍第1項所述之封裝件之製法，其中， 復於該封裝基板與該基板本體之第二表面之間形成底膠。
  6. 如申請專利範圍第1項所述之封裝件之製法，於移除該第一承載片後，復包括使該第一半導體晶片接置於第二承載片上，並進行測試步驟，且於測試完成後，移除該第二承載片。
  7. 如申請專利範圍第6項所述之封裝件之製法，其中，該第二承載片係為UV光解膠膜，且於使該第一半導體晶片接置於該第二承載片上之前，復包括於該第二承載片上形成UV光解膠體，並於移除該第二承載片時，一併移除該UV光解膠體。
  8. 如申請專利範圍第1項所述之封裝件之製法，其中，該第一承載片平貼於一載台上。
  9. 如申請專利範圍第1項所述之封裝件之製法，復包括於該第一半導體晶片上電性接置至少一第二半導體晶片。
  10. 如申請專利範圍第1項所述之封裝件之製法，其中，該第一承載片係為UV光解膠膜。
  11. 如申請專利範圍第1項所述之封裝件之製法，其中，該基板本體係為貫矽中介板，且該些導電通孔係為矽通孔。
  12. 如申請專利範圍第1項所述之封裝件之製法，其中，該基板本體之第一表面或第二表面上係形成有電性連接該導電通孔的重佈線路結構。
  13. 如申請專利範圍第12項所述之封裝件之製法，其中，該重佈線路結構中之介電材料係不同於該基板本體中之介電材料。
  14. 如申請專利範圍第1項所述之封裝件之製法，其中，該基板本體係為貫玻璃中介板，且該些導電通孔係為玻璃穿孔。
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