CN108695265A - 芯片封装结构及其制造方法 - Google Patents

芯片封装结构及其制造方法 Download PDF

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CN108695265A
CN108695265A CN201711431906.9A CN201711431906A CN108695265A CN 108695265 A CN108695265 A CN 108695265A CN 201711431906 A CN201711431906 A CN 201711431906A CN 108695265 A CN108695265 A CN 108695265A
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chip
filling material
frame
road floor
packaging structure
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郑惟元
李正中
郑少斐
陈文龙
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Industrial Technology Research Institute ITRI
Intellectual Property Innovation Corp
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Industrial Technology Research Institute ITRI
Intellectual Property Innovation Corp
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Priority claimed from TW106140493A external-priority patent/TWI636530B/zh
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Publication of CN108695265A publication Critical patent/CN108695265A/zh
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Abstract

本发明公开一种芯片封装结构及其制造方法。上述芯片封装结构包括设置在芯片周围的框架、填入于芯片和框架之间空隙的填充材以及覆盖于芯片、框架和填充材之上的保护层。其中填充材的杨氏模数分别小于芯片的杨氏模数、框架的杨氏模数和保护层的杨氏模数。

Description

芯片封装结构及其制造方法
技术领域
本发明涉及一种封装结构，且特别是涉及一种芯片封装结构及其制造方法。
背景技术
半导体封装的方式分为陶瓷封装和树脂封装两种方式。陶瓷封装具有防潮性佳、寿命长，但成本费用高；树脂封装具有成本低、产量大且性能符合市场需求，故目前是以树脂封装为主。一般树脂封装用的高分子材料有环氧树脂(Epoxy)、聚酰亚胺(Polyimide；PI)、酚醛树脂(Phenolics)、硅氧树脂(Silicones)等。这四种材料中，除散热量大的动力元件必须用成本较高的硅氧树脂外，大部分都采用环氧树脂。使用在封装胶中的环氧树脂有双酚A系(Bisphenol-A)、酚醛环氧树脂(Novolac epoxy)、环状脂肪族环氧树脂(Cyclicaliphatic epoxy)、环氧化丁二烯(epoxydized butadiene)等。目前使用的半导体封装材料以磷甲酚醛的多环性环氧树脂(O-Creso Novolac Epoxy Resin；CNE)为主。
但是，对于面板级封装制作工艺，在模封后，因模封材料热膨胀系数和芯片以及基板的热膨胀系数不同，易造成封装体的翘曲(warpage)，进而造成不易进行后续的取下制作工艺与导致可靠度不佳的问题。此外，若使用高粘度模封材料，因封装制作工艺所造成的热变形与残留应力，使得位于芯片侧边的模封材料易产生剥离(peeling)的问题。
发明内容
本发明一实施例提供一种芯片封装结构包括重布线路层、芯片、框架、填充材和保护层。其中，重布线路层具有一上表面。芯片设置于重布线路层的上表面上，并电连接重布线路层。框架设置于重布线路层的上表面上，且环绕芯片。填充材设置于重布线路层的上表面上，且位于框架和芯片之间。保护层覆盖于芯片、框架和填充材之上。填充材的杨氏模数分别小于芯片、框架和保护层的杨氏模数，且填充材的填充厚度至少为保护层厚度的1.5倍。
本发明另一实施例提供一种芯片封装结构包括重布线路层、芯片、框架、填充材和保护层。其中，重布线路层具有一上表面。芯片设置于重布线路层的上表面上，并电连接重布线路层。框架设置于重布线路层的上表面上，且环绕芯片。低粘度的填充材设置于重布线路层的上表面上，且位于框架和芯片之间。保护层覆盖于芯片、框架和填充材之上。填充材的杨氏模数分别小于芯片、框架和保护层的杨氏模数。
依照另一实施例，填充材的热膨胀系数小于30ppm/℃。
依照另一实施例，填充材上表面的高度低于或等于芯片上表面的高度。
依照另一实施例，填充材的热膨胀系数小于该框架与该保护层的热膨胀系数。
依照另一实施例，填充材包括位于芯片底表面至重布线路层上表面之间的第一填充材，和位于芯片侧面至框架之间的第二填充材。
依照另一实施例，第一填充材的流动性小于或等于第二填充材的流动性。
依照另一实施例，第一填充材的粘度大于或等于第二填充材的黏度。
依照另一实施例，保护层的材料包括金属、陶瓷或热固性环氧树脂。
依照另一实施例，框架的材料包括金属、陶瓷或热固性环氧树脂。
本发明一实施例也提供一种芯片封装结构的制造方法包括形成重布线路层，然后在重布线路层上接合多个芯片。接着，在重布线路层上形成多个环绕芯片的框架，再于框架与芯片间的空隙中填入填充材。在芯片、框架和填充材之上形成保护层后，依照所需进行单体化制作工艺。
为让本发明的内容能更明显易懂，下文特举实施例，并配合所附的附图作详细说明如下。
附图说明
图1A～图1C是本发明一实施例的一种芯片封装结构的示意图，其中图1A为芯片及框架配置方式的俯视图，图1B～图1C为图1A中切线I-I’的剖面结构图；
图2A～图2C是本发明一实施例的一种芯片封装结构的示意图，其中图2A为芯片及框架配置方式的俯视图，图2B～图2C为图2A中切线II-II’的剖面结构图；
图3A～图3H为芯片及框架的其他可能配置方式的俯视图；
图4A～图4E为图1B中芯片封装结构的一种制造流程剖面结构示意图。
符号说明
110、210：基板
120、220：重布线路层
130、230、330：芯片
140、240、340：框架
150、250：填充材
150a、250a：第一填充材
150b、250b：第二填充材
160、260：保护层
170：支撑膜
180、280：凸块
190、290：切割道
242：间隔
345：开口
具体实施方式
承上所述，本发明一实施例提供一种芯片封装结构及其制造方法。此芯片封装结构在芯片周围设置框架结构，然后在芯片和框架结构之间填充具有较低杨氏模数(Young’smodulus)及较低热膨胀系数(Coefficient of thermal expansion；CTE)的填充材。因此，可以减少封装体中不同材料间的残留热应力，并进而解决上述现有翘曲与剥离的问题。
在下面的叙述中，将会介绍上述的芯片封装结构的例示结构与其例示的制造方法。为了容易了解所述实施例之故，下面将会提供不少技术细节。当然，并不是所有的实施例都需要这些技术细节。同时，一些广为人知的结构或元件，仅会以示意的方式在附图中绘出，以适当地简化附图内容。
[芯片封装结构]
图1A～图1C是依照本发明一实施例的一种芯片封装结构的示意图，其中图1A为芯片及框架配置方式的俯视图，图1B～图1C为图1A中切线I-I’的剖面结构图。请参考图1A～图1C，芯片封装结构包括重布线路层120、芯片130、框架140、填充材150和保护层160。
重布线路层120具有相对的一底表面和一上表面。多个管芯或芯片(chip)130配置在重布线路层(Redistribution layer；RDL)120的上表面上，芯片130通过重布线路层120上表面上的接点而电连接至重布线路层120。多个框架140配置在重布线路层120的上表面上，每个芯片130的四周均配置框架140，每个框架140环绕芯片130但并未直接接触芯片130。各框架140彼此连接而整体形成一个类似棋盘格的连续结构。在完成芯片封装结构之后，可沿着各框架140的位置设置切割道(sawing lane)190，在后续制作工艺依照需求将连结的整体框架140切割开来而将芯片130分开来。
在图1B中，重布线路层120包括交替叠置的多层介电层与多层导电层，例如可为4层或8层结构。该重布线路层120结构的厚度例如约为30-60μm，而其杨氏模数约为6Gpa。在重布线路层120于设置芯片130侧的相对侧，亦即在重布线路层120的底表面设置多个凸块180。凸块180通过重布线路层120底表面上的接触垫而电连接至重布线路层120。由于框架140设置在芯片130周围以环绕芯片130，填充材150则填充在框架140之内以及框架140与芯片130之间，并填满由保护层160、框架140、芯片130和重布线路层120所界定的空间，也就是说填充材150位于保护层160、框架140、芯片130和重布线路层120之间。保护层160则设置在芯片130、框架140和填充材150之上。
在图1B中，框架140和填充材150的高度可以和芯片130等高，以提供后续保护层一个较为平坦的底部。依照一实施例，芯片130的厚度可为5～200μm或100～150μm。但是，框架140的高度没有特别的限制，可以略低于或高于芯片130的高度。类似地，填充材150的高度主要由框架140的高度来决定，可以分别大致等于或略低于框架140的高度。
依照一实施例，填充材150的厚度至少为保护层厚度的1.5倍，例如可为1.5、1.6、1.7、1.8、1.9或2倍以上。依照一实施例，填充材150的最大填充厚度与该保护层厚度的比例为2倍以上。
依照另一实施例，填充材150的杨氏模数均小于芯片130、框架140和保护层160的杨氏模数，亦即填充材150的硬度均小于芯片130、框架140和保护层160的硬度。依照另一实施例，填充材150的热膨胀系数小于30ppm/℃，填充材150的热膨胀系数小于其周围的框架140与其上的保护层160的热膨胀系数，故填充材150搭配其周围的框架140与其上的保护层160的整体设计可以有效地减少残留热应力，解决封装体翘曲的问题。依照另一实施例，填充材150乃以低粘度填充胶材所形成，而框架140是以粘度较高的可固化胶材(粘度约为10,000～500,000mPa·s)所形成，其中低粘度填充胶材的粘度低于可固化胶材的粘度。举例而言，填充材150的黏度在25℃时为2,000～20,000mPa·s。
依照本案一些实施例，填充材150可以是由低粘度填充胶材固化后的绝缘性固化填充胶材，低粘度填充胶材例如可为热固性环氧树脂材料(Epoxy)、聚丙烯酸酯(polyacrylate)或聚酰亚胺(polyimide)。依照本案一些实施例，填充材150也可以是非导电胶(non-conductive paste,NCP)、非导电膜(non-conductive film,NCF)或流动性或半流动性的底填材料(underfill materials)。
本案实施例中以低粘度热膨胀系数填充材150作为位于芯片间与芯片框架间的应力缓冲层，以解决现有位于芯片130侧边的模封材料因芯片130的侧边应力而易产生剥离的问题。本案实施例通过形成框架并填入填充材的制作工艺，并且搭配使用合适材料，利用例如挡墙胶材、填胶材料、保护层膜封材料等的选配与结构设计，降低传统膜封制作工艺累积的应力，改善基板翘曲、分层、剥离或是破裂等问题。
依照本案另一些实施例，形成框架140的材料包括金属、陶瓷或热固性环氧树脂，而保护层160的材料也包括金属、陶瓷或热固性环氧聚合物材料。依照本案另一些实施例，框架140和保护层160可使用相同材料，以有效分散热应力的作用处，减少残留热应力的集中度。上述框架140界定填充材150的填充范围与/或高度(厚度)，而保护层160可以协助导热、提供阻挡水气和氧气、防静电及抗挠曲等功能。
因为一般做为模封材料的树脂材料当中，通常会加入大量的氧化硅微粒做为填料(fillers)，以增加模封材料的硬度达到保护芯片的功效。所以，当框架140、填充材150和保护层160都使用类似模封材料的热固性环氧树脂时，填充材150的材料几乎不含填料或含少量的填料，使填充材150的杨氏模数(亦即材料的硬度)变得较低，相较于所使用的类似模封材料的热固性环氧树脂时，填充材150所用环氧树脂中的填料(例如氧化硅微粒)的含量少于框架140和保护层160材料中所含填料(例如氧化硅微粒)的含量。例如，当填充材150使用氧化硅微粒为填料时，氧化硅微粒的平均粒径可大约为0.6～10μm，氧化硅微粒的含量可约为50～65wt％。
在图1C中，为了可以更容易在芯片130底部和重布线路层120之间填入填充材，可以选择在芯片130底部和重布线路层120之间空隙先填入第一填充材150a，再于芯片130侧壁和框架140之间填入第二填充材150b。也就是说，第一填充材150a填在芯片130底部(主动表面)和重布线路层120上表面之间，而第二填充材150b填在芯片130侧壁和框架140之间。依照本案实施例，第一填充材150a的材料与第二填充材150b的材料不相同。例如第一填充材150a的材料不含填料或较少填料而第二填充材150b的材料含较多填料。或者，第一填充材150a的黏度小于第二填充材150b的黏度，亦即第一填充材150a的流动性大于第二填充材150b的流动性。因为芯片130底部和重布线路层120之间的空隙较小，因此要使用粘度较小(亦即流动性较大)的第一填充材150a才比较容易顺利地填入。类似地，若框架140、第一填充材150a、第二填充材150b和保护层160都为热固性环氧树脂时，氧化硅填料的含量为第一填充材150a中氧化硅填料的含量为最少，第二填充材150b中氧化硅填料的含量次之，然后是保护层160中氧化硅填料的含量为最多。上述第一填充材150a的厚度可为45～60μm，第二填充材150b的厚度可为60～250μm。图1C中其它部分和图1B类似，因此不再重复叙述之。
图2A～图2C是依照本发明一实施例的一种芯片封装结构的示意图，其中图2A为芯片及框架配置方式的俯视示意图，图2B～图2C为图2A中切线II-II’的剖面结构示意图。参见图2A～图2B，其芯片封装结构的配置与相对位置类似于图1A～图1B中所示的芯片封装结构的配置，除了框架及保护层的配置有所不同。在图2A～图2B中，每个芯片(chip)230的四周均配置一个独立的框架240，每个框架240环绕芯片230但并未直接接触芯片230。而框架240之间间隔开来互不接触。相似地，重布线路层220包括交替叠置的多层介电层与多层导电层，凸块280配置于重布线路层220底表面上，通过重布线路层220底表面上的接触垫而电连接至重布线路层220。填充材250则填充在框架240和芯片230之间。由于框架240设置在芯片230周围环绕芯片230而框架240之间间隔开来互不接触，后续形成的保护层260则设置在芯片230、框架240和填充材250之上并且填满相邻框架240之间的间隔242。填充材250则填于框架240之内，填满框架240、芯片230、保护层260和重布线路层220所界定的空间，也就是说填充材250位于保护层260、框架240、芯片230和重布线路层220之间。在完成芯片封装结构之后，可沿着相邻框架240之间的间隔242处设置所需的切割道290，依照需求将芯片230分开来。
在图2B中，因为框架240在此是分开的独立结构，而不是如图1B的框架140为连续结构，所以两相邻芯片230之间会有两道框架240，在两道框架240之间形成间隔242。填充材250则填充在框架240和芯片230之间的空隙中以及芯片230和重布线路层220之间的空隙中，但并不会填在相邻框架240之间的间隔242处。保护层260设置在芯片230、框架240和填充材250之上，并且填在相邻框架240之间的间隔242之中。图2B中其他部分和图1B类似，不再重复叙述之。
和图1C类似，在图2C中，也可以在芯片230底部和重布线路层220之间的空隙中先填入第一填充材250a，再于芯片230侧壁和框架240之间填入第二填充材250b。也就是说，第一填充材250a填在芯片230底部(主动表面)和重布线路层220上表面之间，而第二填充材250b填在芯片230侧壁和框架240之间。图2C中其它部分和图2B类似，因此不再重复叙述之。
由上述实施例可知，在芯片和框架之间以及芯片和重布线路层之间都填入低黏度的填充胶材来做为应力缓冲层，使各层应力的分布方式呈现应力梯度(stress gradient)的分布方式。因此，可以让应力分散不会过集中，并提升元件的整体可靠度。此外，若对填充材的热膨胀系数和杨氏模数继续调整，也有机会发展出具有可挠性的封装体。
图3A～图3H显示芯片及框架的其他可能配置方式的俯视图。在图3A～图3H中，为了简化附图起见，只有标出芯片330、框架340和框架340中的开口345的相对位置而省略填充材与保护层。除了上述图1A和图2A所示的芯片及框架的配置方式外，还可以有其他许多种的配置方式，以有效地分散热应力。在图3A～图3H中列出其中几种可能。例如在图3A中，例如以两个芯片330为一封装单元，框架340配置在每一单元的四周彼此连接形成连续的格状结构。而在图3B中，也是两个芯片330为一封装单元，每个框架340呈现双格形状而环绕配置于每一封装单元的每个芯片330的四周，但是每一封装单元的框架340彼此之间相隔开来并未相连。
在图3C～图3H中，展示框架340的其他更多种的配置方式，其共通特点为框架340至少具有一个开口345，而框架340以非连续的形式环绕各封装单元。开口345的宽度必须够窄，使得填充材不会自开口345中溢出，但是气体可以从开口345中泄出，减少填充材中留下气泡的可能性。
在图3C中，其框架340的配置方式基本上类似于图1A的框架140的配置方式，框架340设置环绕在每一芯片330的四周。但是图1A连续相连的框架140在图3C中变更为等距、均等但断续的框架340。也就是说，可以视为变更图1A连续相连的框架140使其具有缺口/开口345，而使连续相连的框架结构变为断续的框架结构。在图3D中，可以看到是以2×2阵列的4个芯片330为一封装单元，框架340为等距、均等但断续的框架结构而设置在每一单元的四周。在图3E中，则以纵向排列的每一栏的6个芯片330为一封装单元，框架340为等距、均等但断续的框架结构设置在每一单元的四周。在图3F～图3G中，框架340则是等距、均等但断续的框架结构，但以同心方形套环的方式设置，只是图3G中在较外围的位置配置框架结构的设置密度较高或相距配置距离较近而已。在图3H中，框架340除了以同心方形套环的方式设置之外，还加了一个十字型的设置。从图3A～图3H可知，这些框架340的配置方式可依整体封装需求或产品应力缓冲的要求而设计，并不仅限于本案实施例所绘示特定的图形所限制。
[芯片封装结构的制造方法]
接下来，介绍上述芯片封装结构的制造方法。首先以图1B中芯片结构为例，在图4A～图4E显示图1B中芯片封装结构的一种制造流程剖面结构示意图。在图4A中，在载板或基板110上形成重布线路层120。依据实施例，形成重布线路层120包括依序形成交替叠置的多层介电层与多层导电层。重布线路层120的形成方法基本可包括例如先沉积再图案化绝缘介电层，在绝缘介电层中形成开口后填入金属插塞，接着，再于绝缘层上沉积并图案化金属层，形成金属线路。然后，依照所需重复上述绝缘层和金属层的步骤数次，达成改变芯片130线路接点位置的目的。而所形成的重布线路层120的最上层导电层形成有多个接点且重布线路层120最底层导电层形成有接触垫。将多个管芯或芯片130配置在重布线路层120的上表面上，然后使芯片130与重布线路层120的接点接合，使芯片130通过重布线路层120上表面上的接点而电连接至重布线路层120。接合芯片130与重布线路层120的方法例如可为焊接。
在图4B中，在芯片130的周围形成多个框架140，使框架140位于重布线路层120的上表面上。如前面所述，框架140的高度没有特别的限制，可以低于、等于或高于芯片130的高度。当框架140的材料为热固化环氧树脂时，其形成方法例如可为打印、喷涂等方法或干膜制作工艺，然后再进行热固化的步骤。当框架140的材料为陶瓷或金属时，框架140也可以是预先形成的，再放置于各芯片130的四周。
然后在图4C中，在芯片130和框架140之间的空隙中填入填充材150。如前面所述，填充材150的高度可以低于或等于芯片130或框架140的高度。若是图1C中的芯片封装结构，在此步骤中则需先填入第一填充材150a，填满芯片130底部到重布线路层120之间的空隙后，再填入第二填充材150b。填充材150、第一填充材150a和第二填充材150b的填入法，例如可将低粘度填充胶材或低粘度模制材料以滴入填充法(drop-fill)或是喷涂法填入到框架140与芯片130之间，然后再进行固化制作工艺使低粘度填充胶材或低粘度模制材料固化即可。
在图4D中，可使用例如滚筒将由支撑膜170所支撑的保护层160滚压贴合在芯片130、框架140和填充材150上。在此步骤中，若为图2A中的芯片封装结构，保护层260也会填入相邻框架240之间的间隔242之内。
在图4E中，移除支撑膜170与基板110，然后在重布线路层120设置芯片130侧的相对侧，亦即在重布线路层120的底表面配置多个凸块180。之后，将凸块180接合固定至重布线路层120，可以通过例如回火焊接制作工艺，将凸块180固定至重布线路层120，而使凸块180通过重布线路层120底表面上的接触垫而电连接至重布线路层120。至此大致完成整个晶片级芯片封装结构的制造，后续可更进行晶片切割制作工艺，将前述晶片级芯片封装结构沿着切割道切割为各个独立的封装单元。上述支撑膜170的杨氏模数小于完成封装结构后的保护层160的杨氏模数。支撑膜170的材料包括金属、陶瓷或热固性环氧树脂。其他部分因为在前面[芯片封装结构]中都有相关的详细叙述，因此不再重复叙述之。
[模拟实验]
接着将对上述翘曲及剥离问题进行模拟比较实验。
在晶片级封装结构翘曲问题的实验中，将针对传统封装结构和类似于图1A-1B中的封装结构进行模拟实验。在传统封装结构中，没有使用图1B中的填充材150，亦即图1B中的框架140、填充材150与保护层160所占区域是由传统模制材料所占据。模拟实验假设传统封装结构和图1B封装结构中的保护层160所用的材料均为相同的环氧树脂，图1B封装结构中的填充材150所用的材料乃是低黏度环氧树脂，且为了让保护层160能具备热稳定性与低吸湿性，一般采取包含双环戊二烯(dicyclopentadiene)和萘(naphthalene)结构的三官能基环氧树脂。模拟实验假设基板为厚度0.7mm和直径370mm的康宁玻璃A1，基板上胶材的总厚度为250μm。加热温度为150℃，加热时间为0.5～2小时。根据热应力模拟实验结果，传统封装结构基板的中心点到边缘翘曲后的高度差高达9.2mm，但是图1B的封装结构翘曲后的高度差只有0.8mm。
在元件可靠度实验中，热翘曲分析(thermal warpage analysis)所使用的分析结构为三层重布线路层，使用环氧成型模料封装，假设芯片厚度范围为100～250μm，在125℃下加热24～48小时。结果传统封装结构其芯片侧边应力高达14MPa，但是类似图1B的封装结构其芯片侧边应力只有1.8MPa。
综上所述，本发明实施例因为使用杨氏模数较低与热膨胀系数较低的低黏度填充材来填充芯片和框架之间的空隙，取代原先所用的高杨氏模数的模制材料或高热膨胀系数材料，因此可以大幅减少残留的热应力，改善热循环后封装体翘曲的问题，更可以改善位于芯片侧边模封材料的剥离问题。此外，因为填充材采用较低黏度的材料，使填充制作工艺容易，可提高制作工艺产量。
虽然结合以上实施例公开了本发明，然其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，可作些许的更动与润饰，故本发明的保护范围应当以附上的权利要求所界定的为准。

Claims (20)

1.一种芯片封装结构，其特征在于，该芯片封装结构包括：
重布线路层，其中该重布线路层具有一上表面；
芯片，设置于该重布线路层的该上表面上并电连接该重布线路层；
框架，设置于该重布线路层的该上表面上且环绕该芯片；
填充材，设置于该重布线路层的该上表面上且位于该框架和该芯片之间；以及
保护层，覆盖于该芯片、该框架和该填充材之上，其中该填充材的杨氏模数分别小于该芯片、该框架和该保护层的杨氏模数，且该填充材的填充厚度至少为该保护层厚度的1.5倍。
2.一种芯片封装结构，其特征在于，该芯片封装结构包括：
重布线路层，其中该重布线路层具有一上表面；
芯片，设置于该重布线路层的该上表面上并电连接该重布线路层；
框架，设置于该重布线路层的该上表面上且环绕该芯片；
填充材，设置于该重布线路层的该上表面上且位于该框架和该芯片之间，其中填充材的黏度在25℃时为2,000～20,000mPa·s；以及
保护层，覆盖于该芯片、该框架和该填充材之上，其中该填充材的杨氏模数分别小于该芯片、该框架和该保护层的杨氏模数。
3.如权利要求2所述的芯片封装结构，其中该填充材的填充厚度至少为该保护层厚度的1.5倍。
4.如权利要求1或2所述的芯片封装结构，其中该填充材的热膨胀系数小于30ppm/℃。
5.如权利要求1或2所述的芯片封装结构，其中该填充材上表面的高度低于或等于该芯片上表面的高度。
6.如权利要求1或2所述的芯片封装结构，其中该填充材的热膨胀系数小于该框架与该保护层的热膨胀系数。
7.如权利要求1或2所述的芯片封装结构，其中该填充材包括位于该芯片底表面至该重布线路层的该上表面之间的第一填充材，和位于该芯片侧面至该框架之间的第二填充材。
8.如权利要求7所述的芯片封装结构，其中该第一填充材的流动性大于或等于该第二填充材的流动性。
9.如权利要求7所述的芯片封装结构，其中该第一填充材的粘度小于或等于该第二填充材的黏度。
10.如权利要求1或2所述的芯片封装结构，其中该保护层的材料包括金属、陶瓷或热固性环氧树脂。
11.如权利要求1或2所述的芯片封装结构，其中该框架的材料包括金属、陶瓷或热固性环氧树脂。
12.一种芯片封装结构的制造方法，其特征在于，该芯片封装结构的制造方法包括：
形成一重布线路层；
接合多个芯片于该重布线路层上；
形成多个框架于该重布线路层上并分别环绕至少该些芯片之一；
填入填充材至该些框架与该些芯片间的空隙中；
形成保护层于该些芯片、该些框架和该填充材上，其中该填充材的杨氏模数分别小于该些芯片、该些框架和该保护层的杨氏模数；以及
进行单体化制作工艺。
13.如权利要求12所述的制造方法，其中该填充材的填充厚度至少为该保护层厚度的1.5倍。
14.如权利要求12所述的制造方法，其中该填充材的热膨胀系数小于30ppm/℃。
15.如权利要求12所述的制造方法，其中该填充材上表面的高度低于或等于该芯片上表面的高度。
16.如权利要求12所述的制造方法，其中该填充材的热膨胀系数小于该些框架与该保护层的热膨胀系数。
17.如权利要求12所述的制造方法，其中该填充材包括位于该芯片底表面至该重布线路层之间的第一填充材以及位于该芯片侧面至该框架之间的第二填充材。
18.如权利要求17所述的制造方法，其中该第一填充材的流动性大于等于该第二填充材的流动性。
19.如权利要求17所述的制造方法，其中该第一填充材的粘度小于等于该第二填充材的黏度。
20.如权利要求12所述的制造方法，其中该保护层的材料包括金属、陶瓷或热固性环氧树脂。
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WO2022126434A1 (zh) * 2020-12-16 2022-06-23 华为技术有限公司 一种芯片封装以及芯片封装的制备方法

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Application publication date: 20181023