CN104465412A - 芯片封装及其制造方法和芯片组件及其制造方法 - Google Patents

芯片封装及其制造方法和芯片组件及其制造方法 Download PDF

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Publication number
CN104465412A
CN104465412A CN201410473648.0A CN201410473648A CN104465412A CN 104465412 A CN104465412 A CN 104465412A CN 201410473648 A CN201410473648 A CN 201410473648A CN 104465412 A CN104465412 A CN 104465412A
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chip
insulating barrier
carrier
package
coating
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CN201410473648.0A
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CN104465412B (zh
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K.侯赛因
F-P.卡尔茨
J.马勒
J.弗尔特
R.沃姆巴赫尔
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Infineon Technologies AG
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Infineon Technologies AG
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract

本发明涉及芯片封装及其制造方法和芯片组件及其制造方法。提供制造芯片封装的方法。所述方法可以包含将至少一个第一芯片用其第二侧电接触到导电载体，所述第一芯片包括第一侧和与所述第一侧相对的第二侧。在所述导电载体的至少一部分之上以及在芯片的第一侧的至少一部分之上形成绝缘层。在所述绝缘层之上布置至少一个第二芯片。在所述第一芯片和所述第二芯片之上形成密封材料。穿过所述密封材料形成到所述至少一个第一芯片的至少一个接触以及到所述至少一个第二芯片的至少一个接触的电接触。

Description

芯片封装及其制造方法和芯片组件及其制造方法
技术领域
各种实施例大体上涉及制造芯片封装的方法、芯片封装、制造芯片组件的方法以及芯片组件。
背景技术
在芯片封装中若干芯片可以并排地或芯片挨芯片被布置在载体上。芯片可以被电耦合到载体。在这样的芯片封装中一个芯片到另一个芯片的电隔离可能对芯片并且大体上对芯片封装的功能性是重要的。芯片可以彼此具有给定的距离和/或可以被隔离材料分离以提供合适的芯片隔离。为了提供更好的隔离，芯片之间距离增加。比如，在如包括比如彼此紧挨的两个功率芯片以及经常作为逻辑驱动器部件的集成电路芯片（IC）的DC-DC转换器的电子系统中，功率芯片和IC之间的距离通常相对大。然而，随着芯片之间的距离增加，系统（比如芯片封装）的尺寸增加。进一步地，当使用导电载体（比如引线框架）时，芯片在载体上布置的不精确性和/或在载体和芯片中的一个之间的隔离层的不精确的厚度（比如如果对应的芯片，比如IC，借助于绝缘粘合剂粘附到载体）可能导致下列问题：不均匀量的粘合剂，粘合剂向芯片上的蔓延，和/或粘合剂在载体上不足够的粘附可能导致用于增加粘合层的粘附的额外工艺步骤。进一步地，粘合剂可能在芯片的侧壁处不合适地粘附。这可能在芯片中的一个比如功率芯片通过扩散焊接被连接到载体时导致问题，因为载体的材料，比如铜，可以扩散穿过芯片的材料，比如硅，并且可以在芯片的侧壁处形成CuSi。这可能导致芯片的电故障。进一步地，在芯片处可能存在焊料溢出（solder-bleed-out）并且粘合剂可能不粘合到焊料溢出。
发明内容
制造芯片封装的方法被提供。所述方法可以包含将至少一个第一芯片（第一芯片包含第一侧和与第一侧相对的第二侧）用其第二侧电接触到导电载体。绝缘层被形成在导电载体的至少一部分之上并且被形成在芯片的第一侧的至少一部分之上。至少一个第二芯片被布置在绝缘层之上。密封材料被形成在第一芯片和第二芯片之上。穿过密封材料形成到至少一个第一芯片的至少一个接触以及到至少一个第二芯片的至少一个接触的电接触。
附图说明
在附图中，贯穿不同视图，相同的参考标记通常指的是相同的部件。附图不必成比例，而通常将重点放在图解本发明的原理。在下列描述中，参考下列附图描述本发明的各种实施例，在附图中：
图1示出了在用于分别制造第一芯片封装和第二芯片封装的方法期间第一工艺阶段中第一芯片封装和第二芯片封装的实施例；
图2示出了在用于分别制造第一芯片封装和第二芯片封装的方法期间第二工艺阶段中第一芯片封装和第二芯片封装的实施例；
图3示出了在用于分别制造第一芯片封装和第二芯片封装的方法期间第三工艺阶段中第一芯片封装和第二芯片封装的实施例；
图4示出了在分别制造第一芯片封装和第二芯片封装的方法期间第四工艺阶段中第一芯片封装和第二芯片封装的实施例；
图5示出了在用于分别制造第一芯片封装和第二芯片封装的方法期间第五工艺阶段中第一芯片封装和第二芯片封装的实施例；
图6示出了在用于分别制造第一芯片封装和第二芯片封装的方法期间第六工艺阶段中第一芯片封装和第二芯片封装的实施例；
图7示出了在用于分别制造第一芯片封装和第二芯片封装的方法期间第七工艺阶段中第一芯片封装和第二芯片封装的实施例；并且
图8示出了用于制造芯片封装的方法的实施例的流程图。
具体实施方式
下列详细的描述参考附图，所述附图通过图解方式示出其中可以实践发明的特定细节和实施例。
本文使用词“示范性的”来表示“用作示例、例子、或图解”。本文描述为“示范性的”的任何实施例或设计不必解释为比其它实施例或设计优选或有优势。
关于“在一侧或表面之上”形成的淀积的材料所使用的词“在…之上”本文可以用来表示淀积的材料可以被“直接形成在暗示的侧或表面上”，例如与暗示的侧或表面直接接触。关于“在一侧或表面之上”形成的淀积的材料所使用的词“在…之上”本文可以用来表示淀积的材料可以“间接形成在暗示的侧或表面上”，其中一个或多个额外的层被布置在暗示的侧或表面和淀积的材料之间。
在各种实施例中用于制造芯片封装的方法可以包含将至少一个第一芯片（第一芯片包含第一侧和与第一侧相对的第二侧）用其第二侧电接触到导电载体。绝缘层可以被形成在导电载体的至少一部分之上并且被形成在芯片的第一侧的至少一部分之上。至少一个第二芯片可以被布置在绝缘层之上。密封材料可以被形成在第一芯片和第二芯片之上。穿过密封材料可以形成到至少一个第一芯片的至少一个接触以及到至少一个第二芯片的至少一个接触的电接触。
在第一芯片之上并且在第二芯片之下的绝缘层使能布置第二芯片相对靠近第一芯片并且带有到第一芯片相对小的距离。这可以促成小尺寸芯片封装。绝缘层为用于密封芯片封装的密封材料和/或为用于将第二芯片固定到载体的粘合剂提供合适的接触表面。这分别增加了密封材料和粘合剂的粘合效果。绝缘材料可以被布置以使得第一芯片的侧壁（该侧壁从第一芯片的第一侧延伸到第一芯片的第二侧）被密封，这促成了没有或只有更少的载体材料可以向上蔓延第一芯片的侧壁。这可以促成芯片封装在长的使用期限内合适的功能性。在各种实施例中，可以存在两个、三个或更多每个包含第一侧和与第一侧相对的第二侧的第一芯片，其中对应的第一芯片用其对应的第二侧电接触到导电载体。
在各种实施例中，第二芯片可以紧挨第一芯片布置。
在各种实施例中，第二芯片可以被布置在第一芯片之上。
在各种实施例中，绝缘层可以被形成在第一芯片的整个第一侧之上。
在各种实施例中，整个第二芯片可以被布置在绝缘层之上。
在各种实施例中，绝缘层在载体之上的厚度以及绝缘层在第一芯片之上的厚度可以是相同的或在相同的范围中，其中所述范围可以由绝缘层中的一个的厚度定义以及由这个厚度与其它绝缘层的厚度的小于比如10%、5%、或1%的偏差定义。
在各种实施例中，绝缘层可以由气相淀积形成。
在各种实施例中，绝缘层可以由化学气相淀积形成。
在各种实施例中，当形成绝缘层时，用于形成绝缘层的绝缘材料可以处于其液相。
在各种实施例中，绝缘材料包含陶瓷和/或聚合物。
在各种实施例中，芯片封装被提供。芯片封装可以包含导电载体。至少一个第一芯片（第一芯片包含第一侧和与第一侧相对的第二侧）可以用其第二侧电接触到导电载体。绝缘层可以被形成在导电载体的至少一部分之上并且被形成在芯片的第一侧的至少一部分之上。至少一个第二芯片可以被布置在绝缘层之上。密封材料可以被形成在第一芯片和第二芯片之上。电接触可以穿过密封材料延伸到至少一个第一芯片的至少一个接触并且延伸到至少一个第二芯片的至少一个接触。在各种实施例中，可以存在两个、三个或更多每个包含第一侧和与第一侧相对的第二侧的第一芯片，其中对应的第一芯片用其对应的第二侧电接触到导电载体。
在各种实施例中，第二芯片可以紧挨第一芯片布置。
在各种实施例中，第二芯片可以被布置在第一芯片之上。
在各种实施例中，绝缘层可以被形成在第一芯片的整个第一侧之上。
在各种实施例中，整个第二芯片可以被布置在绝缘层之上。
在各种实施例中，绝缘层在载体之上的厚度以及绝缘层在第一芯片之上的厚度可以是相同的、近似相同的或在相同的范围中，其中所述相同的范围可以由绝缘层的厚度中的一个的数量级定义。换句话说，绝缘层的厚度可以具有相同的数量级。
在各种实施例中，绝缘层的材料包括陶瓷和/或聚合物。
在各种实施例中，第一芯片可以是功率芯片。
在各种实施例中，第二芯片可以是IC。
在各种实施例中，制造芯片组件的方法被提供。方法可以包含：将至少一个第一芯片（所述第一芯片包含第一侧和与第一侧相对的第二侧）用其第二侧布置在载体上；并且将第一芯片与载体电耦合。涂层可以被形成在载体的至少一部分之上并且可以形成在芯片的第一侧的至少一部分之上，其中涂层电绝缘载体的涂布部分以及第一芯片的涂布部分。至少一个第二芯片可以被布置在涂层之上。可选地，密封可以被形成在第一芯片和第二芯片之上。
在第一芯片之上并且在第二芯片之下的涂层使能布置第二芯片相对靠近第一芯片并且带有到第一芯片相对小的距离。这可以促成小尺寸芯片封装。涂层为用于密封芯片封装的密封材料和/或为用于将第二芯片固定到载体的粘合剂提供合适的接触表面。这分别增加了密封材料和粘合剂的粘合效果。涂层的绝缘材料可以被布置以使得第一芯片的侧壁（该侧壁从第一芯片的第一侧延伸到第一芯片的第二侧）被涂布，这可以促成没有或只有更少的载体材料可以向上蔓延第一芯片的侧壁。这可以促成芯片封装在长的使用期限内合适的功能性。在各种实施例中，可以存在两个、三个或更多每个包含第一侧和与第一侧相对的第二侧的第一芯片，其中对应的第一芯片布置在导电载体上并且用其对应的第二侧电接触到导电载体。
在各种实施例中，第二芯片可以在平行于第一芯片的第一侧的方向中被布置在第一芯片旁边。
在各种实施例中，第二芯片可以被布置在第一芯片之上的涂层上。
在各种实施例中，涂层可以被形成在第一芯片的整个第一侧之上。
在各种实施例中，第二芯片具有第二芯片的第一侧以及第二芯片的第二侧，其中第二芯片可以用其第二侧被布置在涂层上并且其中第二芯片的整个第二侧可以与涂层接触。
在各种实施例中，涂层在载体之上的厚度可以与涂层在第一芯片之上的厚度相同。
在各种实施例中，涂层可以由气相淀积形成。
在各种实施例中，涂层可以由化学气相淀积形成。
在各种实施例中，当形成涂层时，用于形成涂层的材料可以处于其液相。
在各种实施例中，涂层可以包含陶瓷和/或聚合物。
在各种实施例中，芯片组件可以被提供。芯片组件可以包含载体和至少一个第一芯片，第一芯片包含第一侧和与第一侧相对的第二侧，其中其第二侧被布置在载体上并且其中第一芯片与载体电接触。涂层可以被形成在载体的至少一部分之上并且被形成在芯片的第一侧的至少一部分之上。涂层可以电隔离第一芯片和载体的对应部分。至少一个第二芯片可以被布置在涂层之上。可选地，密封材料可以被形成在第一芯片和第二芯片之上。在各种实施例中，可以存在两个、三个或更多每个包含第一侧和与第一侧相对的第二侧的第一芯片，其中对应的第一芯片布置在导电载体上并且用其对应的第二侧电接触到导电载体。
在各种实施例中，第二芯片可以在平行于第一芯片的第一侧的方向中被布置在第一芯片旁边。
在各种实施例中，第二芯片可以被布置在第一芯片之上。
在各种实施例中，涂层可以被形成在第一芯片的整个第一侧之上。
在各种实施例中，第二芯片具有第二芯片的第一侧以及第二芯片的第二侧，其中第二芯片可以用其第二侧被布置在涂层上并且其中第二芯片的整个第二侧可以与涂层接触。
在各种实施例中，涂层在载体之上的厚度可以与涂层在第一芯片之上的厚度相同、近似地相同、或类似、至少类似。
在各种实施例中，涂层可以包含无机材料，陶瓷和/或聚合物。
在各种实施例中，第一芯片可以是功率芯片。
在各种实施例中，第二芯片可以是集成电路（IC）。
图1示出了在用于分别制造第一芯片封装10和第二芯片封装12的方法期间第一工艺阶段中第一芯片封装10和第二芯片封装12的实施例。第一芯片封装10和第二芯片封装12可以分别形成第一芯片组件和第二芯片组件。在图1所示的第一工艺阶段中，可以已经提供载体带14，载体带15承载用于每个芯片封装10、12的一个导电载体。载体可以包含衬底16和/或在衬底16上的导电涂层17。替选地，载体和例如衬底16和/或导电涂层17可以由一件制成。衬底16可以是导电的或可以是电隔离的。比如，衬底16可以包含导电材料或可以由导电材料构成。导电涂层17可以比如是在衬底16上的传导层。导电涂层17可以覆盖整个衬底16或可以只覆盖衬底16的一部分。导电载体可以是引线框架，比如铜引线框架。
至少一个第一芯片18被布置在每个芯片封装10、12的载体上。第一芯片18可以包括第一侧和与第一侧相对的第二侧。第一芯片18可以用其第二侧被布置到和/或电接触到比如具有导电涂层17的导电载体。第一芯片18可以包含第一电接触20和第二电接触22。第一芯片18可以在其面对载体的第二侧上包含一个、两个或多个电接触（未被示出）。第一芯片18可以通过扩散焊接被布置在载体上。比如，第一芯片19可以包含在其第二侧上的AuSn层，所述AuSn层可以在高温和/或高压下与载体的材料（比如铜引线框架的铜）反应以使得第一芯片18被固定到载体。高温可以在200℃到400℃的范围中，比如处于近似300℃。第一芯片18可以是功率芯片，比如CoolMOS（Cool金属氧化物半导体）、MOSFET（金属氧化物半导体场效应晶体管）或IGBT（绝缘栅双极晶体管）。在各种实施例中，芯片封装10、12中的至少一个可以包括两个、三个或更多被布置在导电载体上并且被电接触到导电载体的第一芯片18。
第一芯片封装10和第二芯片封装12经由载体带14被连接并且因而形成芯片封装阵列。替选地，可以只存在一个芯片封装10或进一步芯片封装。
图2示出了在如图1所示的第一工艺阶段之后用于分别制造第一芯片封装10和第二芯片封装12的方法期间第二工艺阶段中第一芯片封装10和第二芯片封装12的实施例。在如图2所示的第二工艺阶段中，绝缘层24可以被形成在载体（比如导电载体）的至少一部分之上并且在第一芯片18的第一侧的至少一部分之上。绝缘层24可以形成涂层，例如电绝缘涂层。绝缘层24可以被形成在第一芯片18的整个第一侧之上。比如，绝缘层24覆盖第一芯片18的整个第一侧和/或整个载体除了第一芯片18被布置的区域。替选地，第一芯片18的只有一部分和/或载体的只有一部分可以被绝缘层24覆盖。绝缘层24在载体之上的厚度和绝缘层24在第一芯片18之上的厚度可以是相同的。比如，在载体之上和在第一芯片18之上的绝缘层24可以在单个工艺中被形成以使得绝缘层24的厚度是均匀的、近似均匀的或相当均匀的。绝缘层的厚度可以在从0.2μm到100μm的范围中，比如在从0.5μm到20μm的范围中，比如在从1μm到5μm的范围中。
绝缘层24可以由气相淀积形成。绝缘层24可以由化学气相淀积（CVD）形成。替选地，绝缘层24可以由物理气相淀积（PVD）形成。替选地，绝缘层24可以由旋涂形成、由溅射形成或由热解淀积形成，比如来自硅烷和/或二氧化硅。当形成绝缘层24时，用于形成绝缘层24的绝缘材料可以处于其气相和/或其液相。
绝缘层24的材料可以包含无机材料和/或陶瓷和/或聚合物。比如，绝缘层24的绝缘材料可以包含无机陶瓷如比如氮化硅、二氧化硅、和/或包含碳的一层或多层，比如无定形碳层（比如被氧，硅、和/或氢修饰）比如a-C:H:Si:O层。这可以是有优势的，因为绝缘层的高绝缘强度和绝缘层对湿气非常低的可渗透率，和/或因为绝缘层24材料的热膨胀系数对芯片18、28的适应是可能的。替选地，绝缘材料可以包含聚合物如帕里纶，比如聚对二甲苯聚合物和/或聚对二甲苯（parylene N）、聚一氯对二甲苯（parylene C）、聚二氯对二甲苯（parylene D）、或环氧化物或丙烯酸酯或硅酮或其混合体。这可以是有优势的，因为然后绝缘层24可以在室温下或接近室温形成，因为可以形成厚层，比如高到50μm、比如高到100μm、比如高到200μm，和/或因为弹性缓冲层可以由绝缘层24形成。
绝缘层24起载体和第一芯片18的电隔离的作用。额外地，绝缘层24可以起对来自载体（例如引线框架）的铜的扩散势垒的作用。进一步地，可以选择绝缘材料以使得在稍后步骤中密封材料可以合适地粘附到绝缘层24。
图3示出了在如图2所示的第二工艺阶段之后用于分别制造第一芯片封装10和第二芯片封装12的方法期间第三工艺阶段中第一芯片封装10和第二芯片封装12的实施例。在如图3所示的第三工艺阶段中，至少一个第二芯片28被布置在绝缘层24之上。比如，第二芯片28可以直接被布置在绝缘层24上。第二芯片可以通过粘合剂26，比如通过层压工艺，通过转移成型、通过转移成型、或通过铸模化合物被布置在绝缘层24上。用于将第二芯片28固定到绝缘层24的粘合剂26的材料可以是导电的或电隔离的。粘合剂26可以包含银颗粒，比如大量的银颗粒。
第二芯片28可以紧挨第一芯片28被布置。比如，第二芯片28可以被布置成在平行于第一芯片18的第一侧和/或第二侧的方向中紧挨第一芯片18并且具有到第一芯片18给定的距离。整个第二芯片28可以被布置在绝缘层24之上。换句话说，绝缘层24可以在整个第二芯片28之下延伸。比如，第二芯片28可以包含第二芯片28的第一侧和第二芯片28的第二侧并且第二芯片28的第二侧可以与绝缘层24完全地或部分地直接接触。第二芯片28可以包含第二芯片28的电接触（未被示出）。第二芯片28的电接触可以被布置在第二芯片28的第一侧处，背对载体。
第二芯片28可以是集成电路（IC）。IC可以是控制芯片。IC可以包含外壳（未被示出）。比如，IC可以被密封以使得形成外壳（未被示出）。
图4示出了在如图3所示的第三工艺阶段之后用于分别制造第一芯片封装10和第二芯片封装12的方法期间第四工艺阶段中第一芯片封装10和第二芯片封装12的实施例。在如图4所示的第四工艺阶段中，密封材料30可以被形成在第一芯片18和第二芯片28之上。密封材料30可以形成密封芯片18、28和绝缘层24的密封。进一步地，密封材料30可以被形成在绝缘层24之上。第二芯片28在其第二侧处被绝缘层24密封并且在其第一侧处以及在其第一侧和其第二侧之间的侧处被密封材料30密封。密封材料30可以通过层压、成型（比如转移成型或注入成型）、通过旋涂、或通过印刷被布置。
可以形成穿过密封材料30到至少一个第一芯片18的至少一个电接触20、22以及到至少一个第二芯片28的至少一个电接触的电接触32。电接触32可以通过在密封材料30中形成孔（比如通过钻孔例如激光或机械钻孔，或通过刻蚀）并且通过将导电材料比如金属（比如铜、银或金）插入到孔中而形成。
图5示出了在如图4所示的第四工艺阶段之后用于分别制造第一芯片封装10和第二芯片封装12的方法期间第五工艺阶段中第一芯片封装10和第二芯片封装12的实施例。在如图5所示的第五工艺阶段中，第一芯片封装10和第二芯片封装12可以彼此分离，比如通过切或锯。
图6示出了在如图3所示的第三工艺阶段之后用于分别制造第一芯片封装10和第二芯片封装12的方法期间第六工艺阶段中第一芯片封装10和第二芯片封装12的实施例。在如图6所示的第六工艺阶段中，第二绝缘层34可以形成在绝缘层24和第二芯片28之上。第二绝缘层34可以覆盖整个绝缘层24和/或第一芯片18。第二绝缘层34可以使能电隔离第二芯片28。这可以使一个、两个或多个进一步芯片能够布置在第二芯片28之上。进一步地，第二绝缘层34可以针对有害的物理或化学外部影响如碰撞和/或氧和/或潮湿而额外地保护芯片18、28。第二芯片28在其第二侧处被绝缘层24密封并且在其第一侧处以及在其第一侧和其第二侧之间的侧处被第二绝缘层34密封。
第二绝缘层34可以形成涂层，例如电绝缘涂层。第二绝缘层34可以形成在第二芯片28的整个第一侧之上。比如，第二绝缘层34覆盖第二芯片28的整个第一侧。替选地，第二芯片28的只有一部分可以被第二绝缘层34覆盖。第二绝缘层34在第一绝缘层24之上的厚度以及第二绝缘层34在第二芯片28之上的厚度可以相同、近似相同或在相同的数量级。比如，在第一绝缘层24之上以及在第二芯片28之上的第二绝缘层34可以在单个工艺中形成以使得第二绝缘层34的厚度是均匀的、近似均匀的或相当均匀的。第二绝缘层34的厚度可以在从0.2μm到100μm的范围中，比如在从0.5μm到20μm的范围中，比如在从1μm到5μm的范围中。
第二绝缘层34可以由气相淀积形成。第二绝缘层34可以由化学气相淀积（CVD）形成。替选地，第二绝缘层34可以由物理气相淀积（PVD）形成。替选地，第二绝缘层34可以由旋涂形成、由溅射形成或由热解淀积形成，比如来自硅烷和/或二氧化硅。当形成第二绝缘层34时，用于形成第二绝缘层34的绝缘材料可以处于其气相和/或其液相。
第二绝缘层34的材料可以包含无机材料和/或陶瓷和/或聚合物。比如，第二绝缘层34的绝缘材料可以包含无机陶瓷如比如氮化硅、二氧化硅、和/或包含碳的一层或多层，比如无定形碳层（比如被氧，硅、和/或氢修饰）比如a-C:H:Si:O层。这可以是有优势的，因为绝缘层的高绝缘强度和绝缘层对湿气非常低的可渗透率，和/或因为第二绝缘层34材料的热膨胀系数对芯片18、28的适应是可能的。替选地，绝缘材料可以包含聚合物如帕里纶，比如聚对二甲苯聚合物和/或聚对二甲苯（parylene N）、聚一氯对二甲苯（parylene C）、聚二氯对二甲苯（parylene D）、或环氧化物或丙烯酸酯或硅酮或其混合体。这可以是有优势的，因为然后第二绝缘层34可以在室温下或接近室温形成，因为可以形成厚层比如高到50μm、比如高到100μm、比如高到200μm，和/或因为弹性缓冲层可以由第二绝缘层34形成。
第二绝缘层34可以起第二芯片28的电隔离的作用。额外地，第二绝缘层34可以起对来自载体（例如引线框架）的铜的扩散势垒的作用。进一步地，可以选择绝缘材料以使得在稍后步骤中密封材料可以合适地粘附到第二绝缘层34。
图7示出了在如图2所示的第二工艺阶段之后用于分别制造第一芯片封装10和第二芯片封装12的方法期间第七工艺阶段中第一芯片封装10和第二芯片封装12的实施例。在如图7所示的第七工艺阶段中，第二芯片28可以被布置在第一芯片18之上。比如第二芯片28可以被布置在绝缘层24上在第一芯片18上。因而，第二芯片28可以在与第一芯片18的第一侧和/或第二侧垂直的方向中远离第一芯片18被布置，其中绝缘层24将第一芯片18与第二芯片28分离并且隔离。
图8示出了用于制造芯片封装比如第一芯片封装10或第二芯片封装12的方法的实施例的流程图。用于制造芯片封装的方法可以是用于制造芯片组件的方法。
在S2中，可以提供载体。比如，可以形成载体。载体可以包含衬底16和导电涂层17。载体可以是导电载体。载体可以是引线框架。导电载体可以包含铜或可以由铜构成。导电载体可以包含导电涂层。载体可以由一件或由两件或多件制成。载体可以包含导电通孔，线焊盘比如键合焊盘，和/或接触区域和包含电绝缘材料的主体。
在S4中，至少一个第一芯片18（第一芯片18包含第一侧和与第一侧相对的第二侧）可以用其第二侧被布置到载体上并且可以与载体电耦合。比如，在S4中，第一芯片18可以用其第二侧电接触到导电载体。第一芯片18可以通过将第一芯片18布置在载体上而比如经由第一芯片18的第二侧与载体电耦合，或在将第一芯片18布置在载体上之后（在后者的情形中）比如借助于线键合与载体电耦合。第一芯片18可以通过焊接比如通过扩散焊接与载体接触。在各种实施例中，可以存在两个、三个或更多每个包含第一侧和与第一侧相对的第二侧的第一芯片18，其中对应的第一芯片被布置在导电载体上并且用其对应的第二侧电接触到导电载体。
在S6中，绝缘层，比如以上绝缘层24，比如涂层，例如电绝缘涂层，被形成在载体的至少一部分之上并且被形成在第一芯片18的第一侧的至少一部分之上，其中涂层电绝缘载体的涂布部分和第一芯片18的涂布部分。绝缘层24或涂层可以被形成在第一芯片18的整个第一侧之上。涂层可以对应于以上解释的绝缘层24。涂层可以包含电绝缘材料和/或涂层可以由电绝缘材料构成。绝缘层24可以由气相淀积形成。绝缘层24可以由化学气相淀积（CVD）形成，比如绝缘层24可以由CVD陶瓷或由CVD聚合物形成。替选地，绝缘层24可以由物理气相淀积（PVD）形成。替选地，绝缘层24可以由旋涂形成、由溅射形成或由热解淀积形成，比如来自硅烷和/或二氧化硅。替选地，绝缘层24可以由烧结工艺或由熔化形成。当形成绝缘层24时，用于形成绝缘层24的绝缘材料可以处于其气相和/或其液相。比如，绝缘层24的材料被提供为溶液。绝缘层24或涂层在载体之上的厚度可以与绝缘层24或涂层在第一芯片18之上的厚度相同、近似相同、或类似。
在S8中，至少一个第二芯片28被布置在绝缘层24或涂层之上。第二芯片28可以在与第一芯片18的第一侧平行的方向中被布置在第一芯片18旁边。替选地，第二芯片28可以被布置在第一芯片24之上的绝缘层24或涂层上。第二芯片28可以具有第二芯片28的第一侧和第二芯片28的第二侧，其中第二芯片28可以用其第二侧被布置在绝缘层24或涂层上并且其中第二芯片28的整个第二侧可以与绝缘层24或涂层接触。
在S10中，密封被形成在第一芯片18和第二芯片28之上，比如通过将密封材料30布置在芯片18、28之上。比如密封材料3以其液相被带到芯片18、28之上并且然后密封材料30变干和/或固化。可选地，第二绝缘层34被形成在第一绝缘层24或涂层和第二芯片28之上。
在S12中，形成电接触，比如以上的电接触32。可以由下述方式形成电接触32：在密封中钻孔（比如机械钻孔或激光钻孔）出孔以使得第一芯片10和第二芯片12的电接触20、22被暴露；并且将导电材料插入到孔中，其中导电材料接触第一芯片10和第二芯片12的电接触20、22。比如，液体的导电材料被填充在孔中并且然后变干或固化。
如果芯片封装10、12被形成在芯片封装布置中，芯片封装可以在分离步骤中被彼此分离。
以上的芯片封装10、12可以被形成为半桥电路并且可以包含对应的部件例如芯片。半桥电路可以被形成在芯片封装10、12的再分布层之上。以上的芯片封装10、12可以包含一个、两个或多个进一步芯片，所述芯片可以被绝缘层24、第二绝缘层34、密封材料30和/或进一步绝缘层或进一步密封材料密封。
虽然参考特定实施例特定地示出和描述本发明，但是应该被本领域技术人员理解的是，可以在其中进行在形式和细节上的各种变化而没有脱离如所附权利要求书定义的本发明的精神和范围。本发明的范围因而由所附权利要求书指示并且因此意图涵盖在权利要求的等价物的含义和范围之内的所有变化。

Claims (25)

1.一种制造芯片封装的方法，所述方法包括：
将至少一个第一芯片用其第二侧电接触到导电载体，所述第一芯片包括第一侧和与所述第一侧相对的第二侧；
在所述导电载体的至少一部分之上以及在芯片的第一侧的至少一部分之上形成绝缘层；
在所述绝缘层之上布置至少一个第二芯片；
在所述第一芯片和所述第二芯片之上形成密封材料；并且
穿过所述密封材料形成到所述至少一个第一芯片的至少一个接触以及到所述至少一个第二芯片的至少一个接触的电接触。
2.依据权利要求1的所述方法，其中所述第二芯片紧挨所述第一芯片布置。
3.依据权利要求1的所述方法，其中所述第二芯片被布置在所述第一芯片之上。
4.依据权利要求1的所述方法，其中所述绝缘层被形成在所述第一芯片的整个第一侧之上。
5.依据权利要求1的所述方法，其中整个第二芯片被布置在所述绝缘层之上。
6.依据权利要求1的所述方法，其中所述绝缘层在所述载体之上的厚度和所述绝缘层在所述第一芯片之上的厚度相同或在类似的范围中。
7.依据权利要求1的所述方法，其中所述绝缘层由气相淀积形成。
8.依据权利要求7的所述方法，其中所述绝缘层由化学气相淀积形成。
9.依据权利要求1的所述方法，其中当形成所述绝缘层时，用于形成所述绝缘层的绝缘材料处于其液相。
10.依据权利要求1的所述方法，其中所述绝缘材料包括陶瓷、无机类型和聚合物中的至少一个。
11.一种芯片封装，包括：
导电载体；
至少一个第一芯片，所述第一芯片包括第一侧和与所述第一侧相对的第二侧，其中其第二侧被电接触到所述导电载体；
绝缘层，在所述导电载体的至少一部分之上并且在芯片的第一侧的至少一部分之上；
至少一个第二芯片，在所述绝缘层之上；
密封材料，在所述第一芯片和所述第二芯片之上；以及
电接触，穿过所述密封材料延伸到所述至少一个第一芯片的至少一个接触并且到所述至少一个第二芯片的至少一个接触。
12.依据权利要求11的所述芯片封装，其中所述第二芯片紧挨所述第一芯片布置。
13.依据权利要求11的所述芯片封装，其中所述第二芯片被布置在所述第一芯片之上。
14.依据权利要求11的所述芯片封装，其中所述绝缘层被形成在所述第一芯片的整个第一侧之上。
15.依据权利要求11的所述芯片封装，其中整个第二芯片被布置在所述绝缘层之上。
16.依据权利要求11的所述芯片封装，其中所述绝缘层在所述载体之上的厚度和所述绝缘层在所述第一芯片之上的厚度相同或在类似的范围中。
17.依据权利要求11的所述芯片封装，其中所述绝缘层的材料包括陶瓷、无机类型和聚合物中的至少一个。
18.依据权利要求11的所述芯片封装，其中所述第一芯片是功率芯片。
19.依据权利要求11的所述芯片封装，其中所述第二芯片是集成电路。
20.一种制造芯片组件的方法，所述方法包括：
将至少一个第一芯片用其第二侧布置在载体上并且将所述第一芯片与所述载体电耦合，所述第一芯片包括第一侧和与所述第一侧相对的第二侧；
在所述载体的至少一部分之上以及在所述第一芯片的所述第一侧的至少一部分之上形成涂层，其中所述涂层电绝缘所述载体的涂布部分和所述第一芯片的涂布部分；并且
将至少一个第二芯片布置在所述涂层之上。
21.依据权利要求20的所述方法，其中所述第二芯片在平行于所述第一芯片的所述第一侧的方向中被布置在所述第一芯片旁边。
22.依据权利要求20的所述方法，其中所述第二芯片被布置在所述第一芯片之上的所述涂层上。
23.一种芯片组件，包括：
载体；
至少一个第一芯片，所述第一芯片包括第一侧和与所述第一侧相对的第二侧，其中所述第一芯片的第二侧被布置在载体上并且其中所述第一芯片与所述载体电接触；
涂层，在所述载体的至少一部分之上以及在所述芯片的所述第一侧的至少一部分之上，所述涂层隔离所述载体和所述第一芯片的对应部分；以及
至少一个第二芯片，在所述涂层之上。
24.依据权利要求23的所述芯片组件，其中所述第二芯片在与所述第一芯片的所述第一侧平行的方向中被布置在所述第一芯片旁边。
25.依据权利要求23的所述芯片组件，其中所述第二芯片被布置在所述第一芯片之上。
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