CN102610590A - 具电磁干扰屏蔽的封装模块 - Google Patents

具电磁干扰屏蔽的封装模块 Download PDF

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CN102610590A
CN102610590A CN2011102372700A CN201110237270A CN102610590A CN 102610590 A CN102610590 A CN 102610590A CN 2011102372700 A CN2011102372700 A CN 2011102372700A CN 201110237270 A CN201110237270 A CN 201110237270A CN 102610590 A CN102610590 A CN 102610590A
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substrate
package module
electromagnetic interference
screen
dielectric layer
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林南君
郑雅云
郑靖桦
刘广三
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ADL Engineering Inc
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Abstract

本发明揭露具电磁干扰屏蔽的封装模块及其方法。上述封装模块包含基板或印刷电路板，其具有至少一接地接垫。复数电子组件装设于基板上。介电层覆盖一选定范围，其涵盖复数电子组件及接地接垫。开孔是形成于介电层内及接地接垫之上。具有至少二金属层的屏蔽层覆盖介电层且通过开孔电性耦合至接地接垫。一般而言，尚有保护层以密封整个基板。本发明的封装模块不但可达到微型封装的要求，还可减少高速电子装置所造成的电磁干扰。

Description

具电磁干扰屏蔽的封装模块
技术领域
本发明有关于电子封装模块，特定而言是有关于具有电磁干扰屏蔽功能及微型封装特性的封装模块。
背景技术
由于半导体科技的快速发展，电子产品例如移动电话、电视、笔记本计算机等的复杂度及功能性大为增加。越来越多复杂且高速的半导体装置被封装于基板或印刷电路板内。高速半导体装置会产生电磁波而干扰其它装置，或受到其它高速装置所发射的电磁波干扰。电磁干扰(electromagnetic interference，EMI)将会负面影响电子系统的操作，而电磁干扰所造成的问题对电子仪器的制造者而言已属常见。
一种传统减少电磁干扰的方法是提供分离的金属壳于模制的半导体封装上。金属壳一般连接至接地平面或印刷电路板上的接垫上，以减少电磁干扰。然而，金属壳却会负面增加封装的厚度，而此情况必定无法满足微型封装的趋势。此外，金属壳的形成需要额外的工艺及附加的材料，而将显著增加封装成本。于另一方法中，导电泡沫塑料或橡胶被施于模制封装上，以吸收电磁干扰。然而，导电泡沫塑料或橡胶必须以人工施加，且需要特别的材料及额外的工艺，而将会显著增加封装成本。再者，导电泡沫塑料或橡胶也会负面增加模制封装的厚度。一种改进的现有方法是将屏蔽表面直接金属化，并将其与接地金属线接触。然而，因屏蔽范围是涵盖整个封装，且若要改变屏蔽的形状及范围则只有较小的弹性。
发明内容
本发明是揭露具电磁干扰屏蔽的封装模块，以及制造此模块的方法。仅选定的范围需要屏蔽层。选定范围的基板具有会发射电磁波的电子装置，或易受到来自其它电子装置或系统的电磁波所负面影响的电子装置。因此，屏蔽层的形状及范围可弹性且节约地加以设计，以节省材料成本。此外，由于不再需要预留电磁干扰屏蔽用的专属区域或在各屏蔽范围之间不再需要较大的接地空间，故封装密度可更加紧密。
本发明揭露一种具电磁干扰屏蔽的封装模块，上述封装模块包含一基板，其具有至少一接地接垫，以及复数电子组件，其装设于上述基板之上。上述封装模块还包含一介电层，其覆盖一选定范围，该选定范围涵盖含有该复数电子组件及该接地接垫的该基板的一部分，复数开孔，其形成于上述介电层内且于上述接地接垫之上，以及一屏蔽层，其覆盖上述介电层且通过该复数开孔电性耦合至该接地接垫。上述封装模块还包含一接合层，其形成于该屏蔽层之上，覆盖上述屏蔽层，以及一保护层，其覆盖于整个基板之上。
选定范围为该基板的牲定区域。在选定范围内的基板装设有会发射电磁波或易受到电磁波负面影响的电子组件。屏蔽层可减少电磁干扰。屏蔽层包含至少二金属层以改善屏蔽层与介电层之间之的黏着性。
接合层位于屏蔽层之上，可提升屏蔽层与保护层之间的黏着性。然而，当屏蔽层与保护层之间无黏着性问题时，接合层可予以省略。保护层为密封整个基板的覆盖层，其材料为一模封材料，可防止封装模块受到来自于周围环境的污染及湿气。
于一实施例中，基板包含印刷电路板、半导体基板、陶瓷、玻璃或任何其结合。介电层为将接地接垫及电子组件与屏蔽层电性隔离，介电层为绝缘体例如二氧化硅(SiO2)、氮化硅(Si3N4)或任何由下列组成的化学组成物：硅(Si)、氮(N)及氧(O)。
本发明揭露一种用以形成具电磁干扰屏蔽的封装模块的方法，上述方法包含提供一基板，上述基板具有至少一接地接垫；设置复数电子组件于上述基板上；执行回焊工艺(reflow process)以将上述电子组件耦合至上述基板；沉积一介电层于一选定范围上，上述选定范围涵盖含有上述复数电子组件及上述接地接垫的上述基板的一部分；形成复数开孔于上述介电层内且于上述接地接垫之上；形成一屏蔽层，上述屏蔽层覆盖上述介电层且通过上述复数开孔电性耦合至上述接地接垫；以及形成一保护层于整个基板之上。于一实施例中，还形成一接合层在形成保护层之前形成于屏蔽层之上。
以下将叙述若干用以形成各层的技术。于一实施例中，形成接地接垫的技术包含溅镀、印刷、电镀、物理气相沉积(PVD)、化学气相沉积(CVD)或任何其结合。形成介电层的技术包含溅镀、化学气相沉积(CVD)、印刷或任何其结合。形成屏蔽层的技术包含溅镀、印刷、电镀、物理气相沉积(PVD)、化学气相沉积(CVD)或任何其结合。形成接合层的技术包含溅镀、印刷、化学气相沉积(CVD)或任何其结合。形成保护层的技术包含射出、印刷、模造工艺或任何其结合。
本发明的封装模块能有效降低从高速电子装置所发射的电磁波或来自于其它电子装置的电磁波；不会体积庞大且可符合现行应用中微型封装的需求。此外，屏蔽层的范围及形状并不固定，可弹性设计。故可减少每一屏蔽范围之间的接地接垫空间，以此可大量节省介电层及屏蔽层的材料。
附图说明
图1是显示本发明的实施例封装模块。
图2是显示仅覆盖一部分基板的屏蔽层。
图3a是显示先提供有接地接垫的基板或印刷电路板。
图3b是显示装设于基板上的复数电子组件及沉积于屏蔽范围的介电层。
图3c是显示形成于介电层内且于接地接垫上的开孔以及沉积于介电层及开孔上的屏蔽层。
图4a是显示覆盖整个基板或印刷电路板的保护覆盖层。
图4b是显示在形成保护层之前沉积于屏蔽层上的接合层。
主要组件符号说明：
100 接地接垫          101 主动式电子组件
102 被动式组件        103 开孔
110 基板              120 介电层
130 屏蔽层            140 接合层
150 保护层            200 接地接垫
201 主动式电子组件    203 开孔
210基板            230屏蔽层
301、302电子组件
具体实施方式
本发明将以下述实施例加以叙述，此类实施例的叙述及范例仅用以说明而非用以限制本发明的权利要求。因此，除说明书中所述的实施例以外，本发明也可实行于其它大体上等同的实施例中。
以下将详细叙述具电磁干扰屏蔽的封装模块以及其制造方法，上述封装模块具有薄型屏蔽层。本发明的封装模块有效降低从高速电子装置所发射的电磁波或来自于其它电子装置的电磁波。电子装置或系统之间的电磁干扰(electromagnetic interference，EMI)会影响电子产品的正常运作。
本发明的封装模块因薄型屏蔽层而不会体积庞大且可符合现行应用中微型封装的需求。此外，屏蔽层的范围及形状并不固定，可弹性设计。故可减少每一屏蔽范围之间的接地接垫空间，以此可大量节省介电层及屏蔽层的材料。
于一实施例中，图1是揭露本发明的实施例封装模块。基板110，例如印刷电路板(PCB，printed circuit board)、半导体基板、陶瓷、玻璃或任何其结合，可作为支撑其上的复数电子组件例如主动式电子组件101及被动式组件102的基底。因基板110的主要功能是作为基底，故基板110的材料并不限于上述材料。
基板110具有电子电路、复数接触垫、接地平面或接地接垫100。基板110装设有各式主动式电子组件101及被动式组件102。之后，介电层120沉积于其上，用以将基板110上的电子电路、接地地垫及电子组件与屏蔽层130电性隔离。一般而言，二氧化硅(SiO2)、氮化硅(Si3N4)或SixNy的化学组成物是用作为介电层120。然而，只要介电层120的材料为绝缘体，本发明的介电层120的材料并不限于上述化学组成物。
复数开孔103形成于接地接垫100之上且于介电层120内，以此屏蔽层130电性耦合至接地接垫100。屏蔽层130含有至少二金属层，以改善屏蔽层130的黏着性，屏蔽层130沉积于介电层120之上，并填充开孔103，以减少电磁干扰。于一实施例中，屏蔽层130为铜/钛(Cu/Ti)或钛/铜/钛(Ti/Cu/Ti)的多层结构，以用于电磁干扰屏蔽及不同层之间的黏着性改善。
接合层140沉积于屏蔽层130之上，以提升保护层150的黏着性。保护层150用以密封封装模块并防止其受到湿气及污染，保护层150的材料可为模封材料(molding compounds)，其大体上由下列所组成：环氧树脂(epoxy resins)、酚醛硬化剂(phenolic hardeners)、二氧化硅(silicas)、催化剂(catalysts)、颜料(pigments)及脱模剂(mold release agents)。于一实施例中，接合层140可予以省略，省略接合层140不会导致保护层150的黏着性问题。
于一实施例中，屏蔽层130的形状及范围可弹性设计成用于特定区域，而非基板110的整个区域。如图2所示，在整个基板210中仅主动式电子组件201会发射电磁波或易受电磁波的负面影响，故屏蔽层230只需覆盖主动式电子组件201。由于不再需要为电磁干扰屏蔽设计特定大范围的屏蔽层，故电子组件的设置可更加弹性且微型化。屏蔽层230因通过复数开孔203电性耦合至接地接垫200而能够吸收电磁波。
以下将叙述用以制造具有选定电磁干扰屏蔽范围的封装模块的工艺。如图3a所示，首先提供含有电子电路、连接垫、接地接垫100之基板110，接着通过回焊(reflow)工艺将电子组件301、302装设于基板110之上。电子电路、连接垫、接地接垫100通过溅镀(sputtering)、印刷(printting)、电镀(electroplating)、物理气相沉积(PVD，physical vapor deposition)、化学气相沉积(CVD，chemicalvapor deposition)或任何其结合而予以形成。假设选定电子组件301为要由电磁干扰屏蔽层所覆盖的组件。如图3b所示，介电层120是通过利用溅镀、化学气相沉积、印刷或任何其结合而沉积于电子组件301及邻近的接地接垫100上。介电层120是定义电磁干扰屏蔽的范围，只要介电层120有覆盖到需要电磁干扰屏蔽的组件，介电层120可为任何形状。
复数开孔103是通过执行涂布光阻、平版印刷(lithography)及蚀刻的工艺而形成于接地接垫100上。于另一实施例中，开孔103是通过激光切割而形成。如图3c所示，接续介电层120，含有至少二金属层的屏蔽层130是利用溅镀、印刷、电镀、物理气相沉积、化学气相沉积或任何其结合而形成于介电层120之上。进行到此时，具有电磁干扰屏蔽的封装模块遂完成。
于一实施例中，具有电磁干扰屏蔽层的封装模块是由模封材料(moldingcompound)所密封以作为保护层，用以防止封装模块的内部装置受到来自于周围环境的污染及/或湿气。如图4a所示，保护层150是利用射出(injection)、印刷、模造工艺(molding process)或任何其结合而形成于整个封装模块的整个基板之上。于另一实施例中，如图4b所示，为提升保护层150与屏蔽层130之间的黏着性，接合层140先利用射出或印刷工艺而形成于屏蔽层130之上，接着保护层150再模制于其上。
虽本发明的较佳实施例已叙述如上，但此领域的技术人员应得以领会本发明不限于此处所述的较佳实施例。在不脱离权利要求所定义的本发明的精神及范围下可作若干改动及润饰。

Claims (10)

1.一种具电磁干扰屏蔽的封装模块，其特征在于，包含：
一基板，具有至少一接地接垫；
复数电子组件，装设于该基板之上；
一介电层，覆盖一选定范围，该选定范围涵盖含有该复数电子组件及该接地接垫的该基板的一部分；
复数开孔，形成于该介电层内且于该接地接垫之上；以及
一屏蔽层，覆盖该介电层且通过该复数开孔电性耦合至该接地接垫。
2.根据权利要求1所述的具电磁干扰屏蔽的封装模块，其特征在于，还包含一接合层，形成于该屏蔽层之上。
3.根据权利要求1或2所述的具电磁干扰屏蔽的封装模块，其特征在于，还包含一保护层，覆盖于整个该基板之上。
4.根据权利要求3所述的具电磁干扰屏蔽的封装模块，其特征在于，其中该保护层为一模封材料，以阻挡来自于周围环境之湿气或污染。
5.根据权利要求1所述的具电磁干扰屏蔽的封装模块，其特征在于，其中该介电层为一绝缘材料，将该接地接垫及该复数电子组件与该屏蔽层电性隔离。
6.根据权利要求1所述的具电磁干扰屏蔽的封装模块，其特征在于，其中该选定范围为该基板的特定区域，会发射电磁波或易受到电磁波影响的该电子组件位于该特定区域中。
7.根据权利要求1所述的具电磁干扰屏蔽的封装模块，其特征在于，其中该屏蔽层减少电磁干扰且包含至少二金属层，以改善该屏蔽层之黏着性。
8.一种用以形成具电磁干扰屏蔽的封装模块的方法，该具电磁干扰屏蔽的封装模块如权利要求1所述，该方法的特征在于，包含：
提供一基板，该基板具有至少一接地接垫；
设置复数电子组件于该基板上；
执行回焊工艺以将该电子组件耦合至该基板；
沉积一介电层于一选定范围上，该选定范围涵盖含有该复数电子组件及该接地接垫的该基板的一部分；
形成复数开孔于该介电层内且于该接地接垫之上；以及
形成一屏蔽层，该屏蔽层覆盖该介电层且通过该复数开孔电性耦合至该接地接垫。
9.根据权利要求8所述的用以形成具电磁干扰屏蔽的封装模块的方法，其特征在于，还包含形成一接合层于该屏蔽层之上。
10.根据权利要求8或9所述的用以形成具电磁干扰屏蔽的封装模块的方法，其特征在于，还包含形成一保护层于整个该基板之上。
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Application publication date: 20120725