CN106098664A - 一种埋入式半导体芯片扇出型封装结构及其制作方法 - Google Patents
一种埋入式半导体芯片扇出型封装结构及其制作方法 Download PDFInfo
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Abstract
本发明公开了一种埋入式半导体芯片扇出型封装结构及其制作方法。该封装结构包括半导体基板、芯片。芯片的正面设置有若干导电垫,半导体基板开设有容纳槽,芯片收容在容纳槽内且正面朝外。每个导电垫上长有金属柱,且金属柱高于半导体基板的上表面。容纳槽与芯片之间的间隙、上表面及金属柱的四周由绝缘层填充或包覆。所有金属柱顶面均连接一条金属重布线,至少有一条金属重布线延伸至芯片的表面之外。本发明通过在芯片上长金属柱,并用聚合物材料覆盖住芯片及金属柱,再使用平坦化工艺,将芯片的金属柱露出,保证封装体表面的平整度;同时凹槽的尺寸范围可扩大。本发明还公开了该埋入式半导体芯片扇出型封装结构的制作方法。
Description
技术领域
本发明涉及半导体封装技术领域的一种芯片扇出型封装结构及其制作方法,尤其涉及一种埋入式半导体芯片扇出型封装结构及其制作方法。
背景技术
本公司一直注重芯片封装技术的研究,如发明专利申请号为201510486674.1、申请日为2015年08月11号、公开号为CN105023900A、公开日为2015年11月04号的《埋入硅基板扇出型封装结构及其制造方法》。然而,芯片埋入硅基板时,由于工艺或设计原因,芯片可能低于或高出基板表面,难以保证所有芯片表面与基板表面保持一致。如高度差较大,会导致其上绝缘层上金属线路不平整,增加金属线路上的应力,存在金属线路被拉断的隐患。并且后续长锡球时,芯片上的锡球与扇出到基板上的锡球存在高度差,芯片焊接到外电路板时也会有可靠性问题。
发明内容
为解决上述技术问题,本发明提供一种埋入式半导体芯片扇出型封装结构及其制作方法。
本发明的解决方案是:一种埋入式半导体芯片扇出型封装结构,其包括半导体基板、至少一个芯片;芯片的正面设置有若干导电垫,半导体基板开设有至少一个容纳槽,至少一芯片收容在容纳槽内且正面朝外;每个导电垫上连接一金属柱,且金属柱高于半导体基板的上表面;容纳槽与芯片之间的间隙、上表面及金属柱的四周由绝缘层填充或包覆;所有金属柱顶面均连接一条金属重布线,至少有一条金属重布线延伸至芯片的表面之外。
作为上述方案的进一步改进,半导体基板为硅基板。
作为上述方案的进一步改进,芯片的背面采用粘结剂层固定在容纳槽的底部。
作为上述方案的进一步改进,绝缘层采用模塑料、环氧树脂、聚合物基树脂薄膜、硅酮或硅酮基材料、感光材料中的至少一种材料制成。
作为上述方案的进一步改进,金属重布线和金属柱的材质均包括铝、钛、铬、钨、铜、镍、金、银、锡中的至少一种。
作为上述方案的进一步改进,金属柱(110)直接长在导电垫上,或通过一层导电线路连接导电垫。
作为上述方案的进一步改进,该导电垫上铺有一层绝缘缓冲层,金属柱形成于该绝缘缓冲层在该导电垫位置的开口处。
作为上述方案的进一步改进,绝缘层上铺有覆盖金属重布线的防焊层。
优选地,每个金属重布线预设一个导电体,防焊层在金属重布线预设导电体的位置开口并在开口处制备相应导电体。
本发明还提供上述任意埋入式半导体芯片扇出型封装结构的制作方法,其包括以下步骤:
步骤一、提供一包含若干芯片的晶圆,在晶圆正面导电垫上长金属柱,分离单颗芯片;
步骤二、提供一半导体基板,在半导体基板的上表面挖若干容纳槽,每个容纳槽中将至少一芯片背面朝下贴于相应容纳槽的槽底;
步骤三、在半导体基板的上表面上覆盖绝缘层,绝缘层包裹芯片的金属柱;
步骤四、平坦化绝缘层,并暴露出金属柱;
步骤五、在绝缘层上设置若干金属重布线,且布线范围超出芯片的面积区域;
步骤六、在每个金属重布线上制作一个导电体,并切割半导体基板,形成单颗封装体。
本发明的有益效果为:通过在芯片上长金属柱,并用聚合物材料覆盖住芯片及金属柱,再使用平坦化工艺,将芯片的金属柱露出,这样保证了封装体表面的平整度;同时凹槽的尺寸范围可扩大。通过调节不同芯片金属柱的高度,可实现不同厚度的芯片同时埋入至容纳槽中实现扇出封装,扩大埋入硅基板扇出封装的应用范围。
附图说明
图1是本发明实施例1的埋入式半导体芯片扇出型封装结构的剖面示意图。
图2是图1中芯片导电垫与金属柱直接连接的剖面示意图。
图3是图1中芯片导电垫与金属柱通过导电线路连接的剖面示意图。
图4是图1中埋入式半导体芯片扇出型封装结构的制作方法的流程图。
图5是图4中制作方法的步骤示意图:提供一长有金属柱的芯片晶圆。
图6是图4中制作方法的步骤示意图:切割形成单颗芯片。
图7是图4中制作方法的步骤示意图:提供一基板晶圆,在基板上表面挖若干容纳槽。
图8是图7的部分剖视图。
图9是图4中制作方法的步骤示意图:将芯片非金属柱面朝下贴于容纳槽底部。
图10是图4中制作方法的步骤示意图:在基板上表面覆盖绝缘层,绝缘层包裹芯片的金属柱。
图11是图4中制作方法的步骤示意图:研磨去除部分绝缘层,暴露出金属柱。
图12是图4中制作方法的步骤示意图:在绝缘层上重布线,至少一条线路超出芯片的投影区域。
图13是图4中制作方法的步骤示意图:在金属线路合适位置制作导电体.
图14是本发明实施例2的埋入式半导体芯片扇出型封装结构的剖面示意图,其中,容纳槽内放入两个尺寸相同芯片。
图15是本发明实施例3的埋入式半导体芯片扇出型封装结构的剖面示意图,其中,容纳槽内放入两个尺寸不同芯片。
图16是本发明实施例4的埋入式半导体芯片扇出型封装结构的剖面示意图,其中,封装体背部研磨。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
图1绘示根据本发明一实施方式的埋入式半导体芯片扇出型封装结构的剖面图。如图1、图2、图3所示,埋入式半导体芯片扇出型封装结构包含至少一个芯片100(在本实施例中以1个为例)、半导体基板200。芯片100的正面设置有若干导电垫,每个导电垫上长有金属柱110,使得芯片100表面具有金属柱110,金属柱110高于半导体基板200的上表面202。半导体基板200开设有至少一个容纳槽201(在本实施例中以1个为例),芯片100收容在容纳槽201内且正面朝外,故半导体基板200表面具有埋入芯片100的容纳槽201,带金属柱110的芯片100,非金属柱面朝下放置于半导体基板200的容纳槽201内。在其他实施例中,容纳槽201还可以收容多个芯片100,每个芯片100的形状、大小等尺寸均可不同。半导体基板200优选为硅基板。芯片100的背面可采用粘结剂层120固定在容纳槽201的底部,故芯片100的非金属柱面可用粘结剂固定在半导体基板200的容纳槽201的底部。
容纳槽201与芯片100之间的间隙、上表面202及金属柱110的四周由绝缘层301填充或包覆,故绝缘层301覆盖芯片100的表面、半导体基板200额表面及金属柱110的侧壁。所有金属柱110顶面均连接一条金属重布线400,至少有一条金属重布线400延伸至芯片100的正面的投影面积之外,故金属线路即金属重布线400铺于绝缘层301上,且至少一条金属线路从金属柱110末端延伸到超出芯片100正投影区域的部分。
绝缘层301可以为一种材料,也可以有多层材料组成,材料不限于模塑料、环氧树脂、聚合物基树脂薄膜、硅酮或硅酮基材料、感光材料。金属线路和金属柱110材质均可包括铝、钛、铬、钨、铜、镍、金、银、锡中的一种或几种。
在本实施方式中,芯片100可为多I/O端口的IC芯片,I/O端口为位于芯片100表面的导电垫111,导电垫111表面上形成有金属柱110,金属柱110电性连接芯片100的导电垫111,如图2所示。本实施方式中,芯片100导电垫面上可以铺一绝缘缓冲层,金属柱110形成于该绝缘缓冲层在导电垫位置的开口处。优选的,金属柱110的高度范围为5μm~150μm。其他实施例中,金属柱110可以通过一层导电线路112连接导电垫111,金属柱110通过导电线路112重新分布导电垫111的导电位置,如图3所示。
本实施例金属线路上覆盖有防焊层500,每个金属重布线400预设一个导电体410,防焊层500在金属线路预设导电体410的位置开口,并在开口处制备导电体410。该导电体410可以是焊球(solder ball)、焊料凸点(solder bump)或金属柱凸点(pillar),其材质包括钛、铬、钨、铜、镍、金、银、锡中的一种或几种。如图1所示的导电体以锡球为例。
请参阅图4,本发明的埋入式半导体芯片扇出型封装结构的制作方法包括以下步骤:
步骤一、提供一包含若干芯片100的晶圆,在晶圆正面导电垫111上长金属柱110(如图5所示),分离单颗芯片100(如图6所示);
步骤二、提供一半导体基板200,在半导体基板200的上表面202挖若干凹槽即容纳槽201(如图7及图8所示),每个容纳槽201中将一芯片100背面朝下贴于相应容纳槽201的槽底(如图9所示);
步骤三、在半导体基板200的上表面202上覆盖绝缘层301,绝缘层301包裹芯片100的金属柱110(如图10所示);
步骤四、平坦化绝缘层301,并暴露出金属柱110(如图11所示);
步骤五、在绝缘层301上设置若干金属重布线400,且布线范围超出芯片100的表面积区域(如图12所示);
步骤六、在每个金属重布线400上制作一个导电体410(如图13所示),并切割半导体基板200,形成单颗封装体。
在步骤一中,金属柱110可以以电镀或化镀方式形成,金属柱110为一种金属,或多种金属沉积而成,如从导电垫111接触位置到远离导电垫111位置,分别为钛、铜、锡银,各层金属沉积厚度相同或不同。分离芯片前可减薄晶圆到设定厚度,分离芯片方式包括切割,刻蚀或激光烧蚀等。
在步骤二中,保证芯片100黏贴到容纳槽201后,金属柱110顶部高出硅基板表面。
在步骤三中,绝缘层301形成方法不限于(真空)涂布绝缘胶、(真空)贴干膜、塑封等。
在步骤四中,平坦化绝缘层301的方法不限于研磨、抛光等。步骤四过后,金属柱110的四周依旧被绝缘层301包覆。
在步骤五中,绝缘层301上的金属重布线400中的线路,至少一条延伸到芯片100投影面积之外。
在步骤六中,在重布线合适位置制作导电体410之前,还可在重布线上覆盖一层保护层或防焊层500,并打开预设导电体410位置,以便导电体410与保护层或防焊层500下的金属重布线路400连接。
其他实施例中,容纳槽201中可以放置多颗芯片100,多颗芯片100可以为相同芯片(如图14所示的实施例2),也可为不同芯片,各芯片尺寸可相同或不同(如图15所示的实施例3)。
其他实施例中,完成的封装体背部可研磨暴露出芯片基材(如图16所示的实施例4),增加散热效果。并可以在该面设一保护膜,保护芯片100不受损伤。
显然,本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。
Claims (10)
1.一种埋入式半导体芯片扇出型封装结构,其包括半导体基板(200)、至少一个芯片(100);芯片(100)的正面设置有若干导电垫,半导体基板(200)开设有至少一个容纳槽(201),至少一个芯片(100)收容在容纳槽(201)内且正面朝外;其特征在于,每个导电垫上连接一金属柱(110),且金属柱(110)高于半导体基板(200)的上表面(202);容纳槽(201)与芯片(100)之间的间隙、上表面(202)及金属柱(110)的四周由绝缘层(301)填充或包覆;所有金属柱(110)顶面均连接一条金属重布线(400),至少有一条金属重布线(400)延伸至芯片(100)的表面之外。
2.如权利要求1所述的埋入式半导体芯片扇出型封装结构,其特征在于:半导体基板(200)为硅基板。
3.如权利要求1所述的埋入式半导体芯片扇出型封装结构,其特征在于:芯片(100)的背面采用粘结剂层(120)固定在容纳槽(201)的底部。
4.如权利要求1所述的埋入式半导体芯片扇出型封装结构,其特征在于:绝缘层(301)采用模塑料、环氧树脂、聚合物基树脂薄膜、硅酮或硅酮基材料、感光材料中的至少一种材料制成。
5.如权利要求1所述的埋入式半导体芯片扇出型封装结构,其特征在于:金属重布线(400)和金属柱(110)的材质均包括铝、钛、铬、钨、铜、镍、金、银、锡中的至少一种。
6.如权利要求1所述的埋入式半导体芯片扇出型封装结构,其特征在于:金属柱(110)直接长在导电垫上,或通过一层导电线路连接导电垫。
7.如权利要求1所述的埋入式半导体芯片扇出型封装结构,其特征在于:该导电垫上铺有一层绝缘缓冲层,金属柱(110)形成于该绝缘缓冲层在该导电垫位置的开口处。
8.如权利要求1所述的埋入式半导体芯片扇出型封装结构,其特征在于:绝缘层(301)上铺有覆盖金属重布线(400)的防焊层(500)。
9.如权利要求8所述的埋入式半导体芯片扇出型封装结构,其特征在于:每个金属重布线(400)预设一个导电体(410),防焊层(500)在金属重布线(400)预设导电体(410)的位置开口并在开口处制备相应导电体(410)。
10.一种如权利要求1至9中任意一项所述的埋入式半导体芯片扇出型封装结构的制作方法,其特征在于:其包括以下步骤:
步骤一、提供一包含若干芯片(100)的晶圆,在晶圆正面导电垫上长金属柱(110),分离单颗芯片(100);
步骤二、提供一半导体基板(200),在半导体基板(200)的上表面(202)挖若干容纳槽(201),每个容纳槽(201)中将至少一芯片(100)背面朝下贴于相应容纳槽(201)的槽底;
步骤三、在半导体基板(200)的上表面(202)上覆盖绝缘层(301),绝缘层(301)包裹芯片(100)的金属柱(110);
步骤四、平坦化绝缘层(301),并暴露出金属柱(110);
步骤五、在绝缘层(301)上设置若干金属重布线(400),且布线范围超出芯片(100)的面积区域;
步骤六、在每个金属重布线(400)上制作一个导电体(410),并切割半导体基板(200),形成单颗封装体。
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Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106298709A (zh) * | 2016-11-11 | 2017-01-04 | 三星半导体(中国)研究开发有限公司 | 低成本扇出式封装结构 |
CN106597765A (zh) * | 2016-12-08 | 2017-04-26 | 深圳市华星光电技术有限公司 | 显示装置、显示面板及其封装方法 |
CN106601628A (zh) * | 2016-12-30 | 2017-04-26 | 通富微电子股份有限公司 | 一种芯片的封装方法及芯片封装结构 |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102751204A (zh) * | 2012-07-16 | 2012-10-24 | 江阴长电先进封装有限公司 | 一种扇出型圆片级芯片封装方法 |
CN202905686U (zh) * | 2012-07-30 | 2013-04-24 | 江阴长电先进封装有限公司 | 一种多芯片圆片级封装结构 |
CN103681371A (zh) * | 2013-12-26 | 2014-03-26 | 江阴长电先进封装有限公司 | 一种硅基圆片级扇出封装方法及其封装结构 |
CN105448752A (zh) * | 2015-12-01 | 2016-03-30 | 华天科技(昆山)电子有限公司 | 埋入硅基板扇出型封装方法 |
-
2016
- 2016-06-12 CN CN201610408852.3A patent/CN106098664A/zh active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102751204A (zh) * | 2012-07-16 | 2012-10-24 | 江阴长电先进封装有限公司 | 一种扇出型圆片级芯片封装方法 |
CN202905686U (zh) * | 2012-07-30 | 2013-04-24 | 江阴长电先进封装有限公司 | 一种多芯片圆片级封装结构 |
CN103681371A (zh) * | 2013-12-26 | 2014-03-26 | 江阴长电先进封装有限公司 | 一种硅基圆片级扇出封装方法及其封装结构 |
CN105448752A (zh) * | 2015-12-01 | 2016-03-30 | 华天科技(昆山)电子有限公司 | 埋入硅基板扇出型封装方法 |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106298709A (zh) * | 2016-11-11 | 2017-01-04 | 三星半导体(中国)研究开发有限公司 | 低成本扇出式封装结构 |
CN106597765A (zh) * | 2016-12-08 | 2017-04-26 | 深圳市华星光电技术有限公司 | 显示装置、显示面板及其封装方法 |
CN106601628A (zh) * | 2016-12-30 | 2017-04-26 | 通富微电子股份有限公司 | 一种芯片的封装方法及芯片封装结构 |
CN109119344A (zh) * | 2017-06-23 | 2019-01-01 | 力成科技股份有限公司 | 半导体封装及半导体封装的制造工艺方法 |
WO2019179184A1 (zh) * | 2018-03-21 | 2019-09-26 | 华为技术有限公司 | 一种封装结构及其制作方法、电子设备 |
CN110299329A (zh) * | 2018-03-21 | 2019-10-01 | 华为技术有限公司 | 一种封装结构及其制作方法、电子设备 |
CN109085224B (zh) * | 2018-08-27 | 2023-11-03 | 浙江大学 | 用于细胞表面区域atp检测的敏感微电极 |
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