CN106560918A - 半导体封装结构及其形成方法 - Google Patents

半导体封装结构及其形成方法 Download PDF

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Publication number
CN106560918A
CN106560918A CN201610770244.7A CN201610770244A CN106560918A CN 106560918 A CN106560918 A CN 106560918A CN 201610770244 A CN201610770244 A CN 201610770244A CN 106560918 A CN106560918 A CN 106560918A
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China
Prior art keywords
semiconductor body
moulding compound
insulating barrier
semiconductor
dielectric layer
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CN201610770244.7A
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English (en)
Inventor
刘乃玮
林子闳
彭逸轩
萧景文
黄伟哲
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MediaTek Inc
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MediaTek Inc
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Publication of CN106560918A publication Critical patent/CN106560918A/zh
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Abstract

本发明实施例提供了一种半导体封装结构及其形成方法。其中该半导体封装结构包括：半导体主体；互连结构，设置在该半导体主体的表面上；模塑料，围绕该半导体主体及该互连结构；以及重分布层结构，设置在该互连结构及该模塑料上；其中，该模塑料的一部分在该重分布层结构及该半导体主体之间延伸，并且该部分的模塑料位于该半导体主体的表面的正下方。本发明实施例的半导体封装结构，具有好的可靠性。

Description

半导体封装结构及其形成方法
技术领域
本发明涉及半导体封装技术领域，尤其涉及一种半导体封装结构及其形成方法，例如封装上封装(Package-on-Package，PoP)结构及其形成方法。
背景技术
半导体封装不仅能够为封装于其中的半导体晶粒提供免受环境污染的保护，而且也能够提供该半导体晶粒与印刷电路板(PCB)之间的电连接。例如，半导体晶粒封闭于封装材料中，并且线路(trace)电性连接至该半导体晶粒及该印刷电路板。
但是，半导体晶粒与封装材料之间的黏合性差。可以轻易在两种材料的界面处(诸如半导体晶粒与封装材料之间的界面)引起脱层。另外，集中于两种材料的界面处的应力可能导致线路破裂。
如此，期望一种创新的半导体封装结构及其形成方法。
发明内容
有鉴于此，本发明实施例提供了一种半导体封装结构及其形成方法，可以提高可靠性。
本发明实施例提供了一种半导体封装结构，包括：半导体主体；互连结构，设置在该半导体主体的表面上；模塑料，围绕该半导体主体及该互连结构；以及重分布层结构，设置在该互连结构及该模塑料上；其中，该模塑料的一部分在该重分布层结构及该半导体主体之间延伸，并且该部分的模塑料位于该半导体主体的表面的正下方。
其中，该互连结构露出该半导体主体的表面的一部分，该部分的模塑料直接接触该半导体主体的表面的露出的部分。
其中，该互连结构包括：介电层，设置在该半导体主体的表面上；绝缘层，设置在该介电层的表面上，并且该介电层位于该半导体主体与该绝缘层之间；以及导电结构，耦接至该重分布层结构，并且该介电层围绕该导电结构的底部，绝缘层围绕该导电结构的顶部。
其中，该介电层完全覆盖该半导体主体的表面，该绝缘层露出该介电层的表面的部分；其中，该部分的模塑料夹在该重分布层结构和该介电层的表面的露出的部分之间。
其中，该半导体主体的长度大于该绝缘层的长度；或者，该部分的模塑料堆叠在该半导体主体的表面上；或者，该部分的模塑料的侧壁与该半导体主体的侧壁不共平面；或者，该部分的模塑料围绕该绝缘层。
本发明实施例提供了一种半导体封装结构，包括：半导体主体；导电垫，设置在该半导体主体的表面的下方；重分布层结构，位于在该半导体主体的下方；导电结构，位于该导电垫及该重分布层结构之间，其中该半导体主体的表面面向该重分布层结构；绝缘层，位于该半导体主体的该表面与该重分布层结构之间，其中该表面的部分从该绝缘层中露出；以及模塑料，围绕该半导体主体并且覆盖该表面的该部分。
其中，该模塑料从该半导体主体的侧壁横向地延伸至该绝缘层的侧壁。
其中，该模塑料的延伸长度介于1μm～200μm之间。
其中，该模塑料的邻接该绝缘层的侧壁与该半导体主体的侧壁不共平面；或者，覆盖该表面的该部分的模塑料夹在该重分布层结构与该半导体主体之间。
其中，进一步包括：导电通孔结构，耦接至该重分布层结构；其中，该模塑料的第一部分位于该导电通孔结构与该绝缘层之间，该模塑料的第二部分位于该导电通孔结构与该半导体主体之间，并且该模塑料的第一部分的宽度大于该模塑料的第二部分的宽度。
其中，进一步包括：黏合层，其中，该半导体主体的一部分位于该黏合层与该绝缘层之间以及另一部分位于该黏合层与该模塑料之间。
本发明实施例提供了一种形成半导体封装结构的方法，包括：提供晶粒，其中该晶粒包括：半导体主体；导电结构，设置在该半导体主体的表面上；以及绝缘层，围绕该导电结构，其中该半导体主体的表面的部分从该绝缘层中露出；形成围绕该半导体主体及覆盖该半导体主体的表面的露出的部分的模塑料；以及在该模塑料及该绝缘层上形成重分布层结构。
其中，形成该晶粒的步骤包括：在该绝缘层中形成第一开口，以露出该半导体主体的表面的部分；以及在该半导体主体中形成沿该第一开口方向的第二开口。
其中，该第一开口宽于该第二开口。
其中，该第一开口与该第二开口连通。
其中，在形成该模塑料之后，该方法进一步包括：对该模塑料执行减薄工艺。
本发明实施例提供了一种形成半导体封装结构的方法，包括：提供晶粒，其中该晶粒包括：半导体主体；介电层，设置在该半导体主体的表面上；以及绝缘层，设置在该介电层的表面上，其中该介电层位于该半导体主体与该绝缘层之间，该介电层的表面的一部分从该绝缘层中露出；形成围绕该半导体主体及覆盖该介电层的表面的露出的部分的模塑料，；以及在该模塑料及该绝缘层上形成重分布层结构。
本发明实施例的有益效果是：
以上的半导体封装结构，部分的模塑料在重分布层结构和半导体主体之间延伸，并且该部分的模塑料是位于半导体主体的正下方的，因此该部分的模塑料可以作为释放应力的缓冲层，以提高半导体封装接结构的可靠性。
附图说明
通过阅读接下来的详细描述以及参考附图所做的示例，可以更全面地理解本发明，其中：
图1A～1G为根据本发明一些实施例的形成半导体封装结构的方法中的各阶段的横截面示意图；
图2A～2B为根据本发明一些实施例的形成半导体封装结构的方法中的各阶段的横截面示意图；
图3为根据本发明一些实施例的半导体封装结构的横截面示意图；
图4为根据本发明一些实施例的半导体封装结构的横截面示意图。
具体实施方式
以下描述为实现本发明的较佳预期模式。该描述仅出于说明本发明一般原理的目的，而不应视为限制。本发明的范围可参考所附的权利要求来确定。
参考特定实施例与参考确定的附图来描述本发明，但是本发明不限制于此，并且本发明仅由权利要求来限定。描述的附图仅是示意图而非限制。在附图中，出于说明目的而夸大了某些元件的尺寸，并且某些元件的尺寸并非按比例绘制。图中的尺寸及相对尺寸不对应本发明实践中的真实尺寸。
图1A～1G为根据本发明一些实施例的形成半导体封装结构的方法中的各阶段的横截面示意图。在图1A～1G中描述的各阶段之前、期间及/或之后，可以提供额外的操作。对于不同实施例，可以替换或者取消描述的该些阶段中的部分。额外的特征(如结构)可以添加至该半导体封装结构。对于不同的实施例，可以替换或者取消以下描述的特征中的部分。为了简化图形，在图1A～1G中仅绘示了半导体封装结构的部分。
如图1A所示，提供了半导体主体100。在一些实施例中，该半导体主体100可以为晶圆或者面板(panel)。该半导体主体100可以包括：至少一个芯片区110。在一些实施例中，该半导体主体100包括：半导体材料，诸如硅或者另一合适的半导体材料。
互连结构形成于该半导体主体100的表面100a上，该表面100a可被称为有源面。在一些实施例中，该互连结构包括：多个导电垫120和介电层130。如图1A所示，该多个导电垫120位于每个芯片区110中的表面100a上。介电层130位于表面100a上并且覆盖每个导电垫120的部分。
该互连结构可以进一步包括：至少一条导电线路，层间介电(InterlayerDielectric，ILD)层和金属间介电(Inter-Metal Dielectric，IMD)层，位于导电垫120及介电层130的下面。例如，导电垫120为互连结构中的最上层的导电线路。介电层130为互连结构中的最上层的介电层并且可被称为“钝化层”。为了简化图形，此中仅描绘了导电垫120与介电层130作为示例。
如图1A所示，该互连结构可以进一步包括：多个导电结构140形成于介电层130的多个开口中，其中开口露出对应的导电垫120的部分。导电结构140伸出介电层130。换言之，介电层130仅围绕导电结构140的底部。
在一些实施例中，导电结构140可以为凸块或者柱形物。在一些实施例中，导电结构140可以包括：铜或者另一合适的导电材料。
如图1A所示，该互连结构可以进一步包括：绝缘层150，形成于该介电层130上。该绝缘层150围绕导电结构140的顶部。绝缘层150为保护导电结构140的缓冲层。绝缘层150也被称为用于在半导体主体100上提供平坦表面的平坦化层(flattening layer)。
在一些实施例中，绝缘层150包括：聚合物或者另一合适的绝缘材料。在一些实施例中，通过沉积工艺来形成绝缘层150，诸如涂布(coating)工艺、物理气相沉积工艺、化学气相沉积工艺或者另一合适的工艺。
在一些实施例中，沉积的绝缘层150覆盖导电结构140。接着，在沉积的绝缘层150上执行减薄工艺(thinning process)，诸如蚀刻工艺、铣销工艺(milling process)、磨光工艺或者抛光工艺。如此，导电结构140的顶面从减薄的绝缘层150中露出。在一些实施例中，绝缘层150的顶面与导电结构140的顶面大致共平面。
如图1B所示，在半导体主体100的相对于表面100a的表面100b上执行减薄工艺。如此，降低半导体主体100的厚度。
接着，至少一个第一开口160形成于绝缘层150及介电层130中。如此，半导体主体100的一部分的表面100a通过第一开口160从绝缘层150和介电层130中露出。如上所述，介电层130与半导体主体100之间可以存在其他的介电层。第一开口160可以进一步穿透这些介电层以露出表面100a。
每个第一开口160位于两个相邻的芯片区110之间并且延伸进芯片区110中。换言之，将第一开口160设置在芯片区110的边缘并且将其延伸到芯片区110之外。
在一些实施例中，第一开口160沿芯片区110延伸。在一些实施例中，第一开口160连续地围绕芯片区域110的中心。例如，从俯视图来看，第一开口160连续地围绕导电垫120及导电结构140。
在一些实施例中，在绝缘层150及介电层130上执行激光开槽工艺来形成第一开口160。在一些实施例中，通过合适的刀片切割绝缘层150及介电层130以形成第一开口160。在一些实施例中，在绝缘层150与介电层130上执行光刻与蚀刻工艺以形成第一开口160。蚀刻工艺可以为干式蚀刻工艺、湿式蚀刻工艺、电浆蚀刻工艺、反应离子(reactive ion)蚀刻工艺或者另一合适的蚀刻工艺。
在其他的一些实施例中，绝缘层150包括：光敏材料，并且在绝缘层150上执行光刻工艺。对绝缘层150的一些部分曝光并显影以移除这些部分。如此，在绝缘层150中形成没有延伸进介电层130的第一开口160。如上所述，在介电层130与半导体主体100之间可以存在其他的介电层。可以在绝缘层150中形成没有延伸进这些介电层的第一开口160。
如图1C所示，在半导体主体100中形成一个或多个第二开口170。第二开口170沿第一开口160和芯片区110延伸。每个第二开口170可与第一开口160连通。如此，半导体主体100中对应芯片区110的部分彼此隔开。相应地，形成多个芯片或晶粒180。在一些实施例中，使用合适的刀片来切割半导体主体100以形成晶粒180。
在一些实施例中，第一开口160宽于第二开口170。相应地，开口160露出每个晶粒180中的半导体主体100的表面100a的一部分。换言之，半导体主体100宽于绝缘层150及介电层130，如图1C所示。
每个晶粒180中的表面100a的露出部分具有长度L。在一些实施例中，长度L的范围大约从1μm至200μm，例如从10μm至200μm。在一些实施例中，第一开口160与第二开口170之间的宽度差大致等于2倍的长度L(即2L)，如图1C所示。在一些实施例中，半导体主体100与绝缘层150(或介电层130)之间的宽度差大致等于2倍的长度L(即2L)，如图1C所示。
如图1D所示，提供载体基底200。在一些实施例中，载体基底200为晶圆或者面板。载体基底200可以包括：玻璃或者其他的支撑材料。
接着，在载体基底200上形成多个导电通孔结构210。导电通孔结构210可以为穿过插入层的通孔(through interposer vias，TIV)。在一些实施例中，导电通孔结构210为柱形物或者其他合适的导电结构。在一些实施例中，导电通孔结构210包括：铜或者另一合适的导电材料。在一些实施例中，通过电镀工艺或者另一合适的工艺形成导电通孔结构210。
本发明实施例不限制于此。在其他的一些实施例中，在形成导电通孔结构210之前，可以在载体基底200上形成RDL结构。接着，在载体基底200上的RDL结构上形成导电通孔结构210。
如图1D所示，含有部分露出的表面100a的晶粒180接合至载体基底200上。在一些实施例中，晶粒180中的半导体主体100的表面100b经由黏合层220附着至载体基底200。在一些实施例中，黏合层220包括：胶水或者另一合适的黏性材料。在其他的一些的实施例中，多个含有部分露出的表面100a的晶粒180接合至载体基底200上。
在一些实施例中，晶粒180为有源元件。例如，晶粒180可以为逻辑晶粒，该逻辑晶粒包括：中央处理单元(Central Processing Unit，CPU)、图形处理单元(GraphicsProcessing Unit，GPU)、DRAM控制器或者他们的任意组合。在其他的一些的实施例中，一个或多个无源元件也可以接合至该载体基底200上。无源元件可以包括或者不包括部分露出的表面，类似于部分露出的表面100a。
在一些实施例中，晶粒180设置在两个导电通孔结构210之间。在一些实施例中，从俯视图来看，导电通孔结构210围绕晶粒180。
如图1E所示，在载体基底200上形成模塑料230。该模塑料230围绕并邻接半导体主体100的侧壁、介电层130的侧壁、绝缘层150的侧壁及黏合层220的侧壁。模塑料230也围绕并邻接导电通孔结构210。
根据本发明的一些实施例，模塑料230的一部分230a从半导体主体100的侧壁沿其表面100a横向地延伸至绝缘层150的侧壁及介电层130的侧壁。如此，模塑料230的延伸的部分230a(以下称为“延伸部230a”)覆盖表面100a露出的部分。其中，该延伸部230a位于该半导体主体100的表面100a的正下方，其中正下方可以是指半导体主体100正对RDL结构240(如图1F所示)的方向。
在一些实施例中，模塑料230的延伸部230a的延伸长度(即长度L)的范围为11μm～200μm，例如为10μm～200μm。
在一些实施例中，模塑料230的延伸部230a的侧壁邻接绝缘层150的侧壁及介电层130的侧壁，并且与半导体主体100的侧壁不共平面。模塑料230的延伸部230a堆叠在半导体主体100上，例如延伸部230a与半导体主体100在俯视方向上重叠。在一些实施例中，从俯视图来看，模塑料230的延伸部230a连续地围绕绝缘层150及介电层130。
在一些实施例中，模塑料230的延伸部230a直接接触表面100a露出的部分。在其他的一些实施例中，模塑料230的延伸部230a不直接接触表面100a的露出的部分。
在一些实施例中，半导体主体100的边缘部分夹在黏合层220与模塑料230的延伸部230a之间。在一些实施例中，如图1E所示，模塑料230中位于导电通孔结构210和绝缘层150(或者介电层130)之间的部分宽于模塑料230中位于导电通孔结构210与半导体主体210之间的部分。
如上所述，在其他的一些实施例中，含有部分露出的表面的一个或多个无源元件也接合至载体基底200上。模塑料230的延伸部230a也覆盖该无源元件的表面的露出部分。
在一些实施例中，模塑料230包括：非导电材料，诸如环氧树脂、树脂、可塑聚合物或者另一合适的模塑料。在一些实施例中，该模塑料230可以在大致为液体时应用，然后通过化学反应固化。在其他的一些实施例中，模塑料230可以为紫外(ultraviolet，UV)或者热固化并且应用为凝胶或者可塑固体的聚合物，接着通过UV或者热固化工艺固化该聚合物。模塑料230可以按照模型(未示出)来固化。
在一些实施例中，模塑料230的材料可以不同于绝缘层150的材料。在一些实施例中，绝缘层150的材料具有好的间隙填充(gap-filling)能力。例如，绝缘层150的材料比模塑料230的材料更容易填充导电结构140之间的空间。相比于模塑料230的材料，当由绝缘层150的材料来覆盖半导体主体100的表面100a时，可以更容易地执行缺陷测试及/或对准步骤。
在一些实施例中，沉积的模塑料230覆盖导电通孔结构210的顶面、绝缘层150的顶面及导电结构140的顶面。接着，执行研磨工艺来使沉积的模塑料230变薄。堆叠在半导体主体100之上的模塑料230的延伸部230a也变薄。如此，变薄了的模塑料230露出导电通孔结构210的顶面，绝缘层150的顶面及导电结构140的顶面。
在一些实施例中，模塑料230的上表面与导电通孔结构210的上表面大致共平面。在一些实施例中，模塑料230的上表面与绝缘层150及导电结构140的顶面也大致共平面。
如图1F所示，在模塑料230及绝缘层150上形成重分布层(Redistribution Layer，RDL)结构240。在一些实施例中，RDL结构240包括：一个或多个IMD层250及一条或多条导电线路260。导电线路260设置在IMD层250中并且被IMD层250围绕。导电线路260的接垫部分从RDL结构240的顶面露出。需要注意的是，图中所示的IMD层250及导电线路260的数量和配置仅是示例而不是对本发明的限制。
导电垫120通过导电结构140电性连接至RDL结构240的导电线路260。导电通孔结构210直接电性连接至RDL结构240的导电线路260。
在一些实施例中，如图1F所示，模塑料230的延伸部230a夹在RDL结构240与半导体主体100之间。更具体地，模塑料230的延伸部230a夹在最底层的IMD层250和表面100a的露出的部分之间。
如图1F所示，在RDL结构240上形成一个或多个导电结构280。例如，导电结构280形成在导电线路260的接垫部分上。在一些实施例中，导电结构280为接合球(诸如焊料球)或者另一合适的导电结构。
在一些实施例中，在一个导电结构280与导电线路260的一个接垫部分之间存在凸块下金属(Under-Bump Metallurgy，UBM)层270。该UBM层270可以包括：单层或者多层，诸如阻挡层(barrier layer)和晶种层。此中描绘了含有单层的UBM层270作为示例。
如图1G所示，移除载体基底200。如此，露出附着至半导体主体100的表面100b的黏合层220。在一些实施例中，消除黏合层220的黏性以使载体基底200脱层。
接着，在黏合层220及模塑料230上形成背面膜(backside film，BSF)290。BSF290和半导体主体100位于黏合层220的两相对侧。在一些实施例中，通过BSF290来防止形成的半导体封装的翘曲。在其他的一些实施例中，可以省略BSF290。
在一些实施例中，如图1G所示，在BSF290中形成一个或多个开口300。在一些实施例中，通过激光钻孔工艺或者另一合适的工艺形成开口300。
为了进一步电连接，开口300露出导电通孔结构210的远离RDL结构240的表面。例如，芯片/晶粒可以接合在BSF290上并通过开口300电性连接至导电通孔结构210。可选地，封装可堆叠在BSF290上并且通过开口300电性连接至导电通孔结构210。例如，该封装可以为存储器封装或者另一合适的封装，诸如DRAM封装。
根据本发明的一些实施例，在形成BSF290之后，可以执行分离工艺。例如，切割RDL结构240、模塑料230及BSF290。如此形成多个半导体封装结构。
可以对本发明实施例做出许多变化及/或修改。图2A至2B为根据本发明实施例的形成半导体封装结构的方法的各阶段的横截面示意图。图2A～2B与图1A～1G中，相同的元件使用相同的参考符号，并且出于简洁而不再描述。
如图2A所示，提供了芯片或者晶粒190。该晶粒190的结构类似于图1C～1G中的晶粒180的结构。形成晶粒190的方法也类似于形成晶粒180的方法，如图1A～1C所示。晶粒180与190之间的差别在于：晶粒180的第一开口160穿透绝缘层150和介电层130，而晶粒190的第一开口160仅穿透绝缘层150。如此，如图2A所示，绝缘层150通过第一开口160露出介电层130的表面的边缘部分。相应地，介电层130和半导体主体100均宽于绝缘层150。
在一些实施例中，绝缘层150包括：光敏材料，并且在绝缘层150上执行光刻工艺。对绝缘层150的一些部分进行曝光和显影以移除这些部分。如此，在绝缘层150中形成没有延伸进介电层130的第一开口160。如上所述，在介电层130与半导体主体100之间可以有其他介电层。在一些实施例中，第一开口160没有延伸进入这些介电层。
如图2A所示，RDL结构310，类似于RDL结构240，形成于载体基底200上。在一些实施例中，RDL结构310包括：一个或者多个IMD层320以及一条或者多条导电线路330。导电线路330设置在IMD层320中，并且由IMD层320围绕。导电线路330的接垫部分自RDL结构310的顶面露出。
接着，在RDL结构310上形成多个导电通孔结构210。接着，含有第一开口160的晶粒190接合至RDL结构310上。在一些实施例中，在晶粒190中的半导体主体100的表面100b通过黏合层220附着至RDL结构310。在其他的一些实施例中，多个含有第一开口160的晶粒190接合至RDL结构310上。
如图2B所示，模塑料230围绕并且邻接半导体主体100的侧壁、介电层130的侧壁、绝缘层150的侧壁及黏合层220的侧壁。模塑料230也围绕并且邻接导电通孔结构210。
根据本发明的一些实施例，模塑料230的延伸部230a从半导体主体100的侧壁横向延伸至绝缘层150的侧壁。由于晶粒190的第一开口160穿透绝缘层150但没有延伸进介电层130中，因此图2B所示的延伸部230a薄于图1G所示的延伸部230a。
在一些实施例中，模塑料230的延伸部230a的侧壁邻接绝缘层150的侧壁，并且与半导体主体100及介电层130的侧壁不共平面。模塑料230的延伸部230a堆叠在半导体主体100及介电层130上。在一些实施例中，从俯视图来看，模塑料230的延伸部230a连续地围绕绝缘层150。在一些实施例中，模塑料230的延伸部230a直接接触介电层130的远离RDL结构310的表面。
在一些实施例中，如图2B所示，模塑料230的延伸部230a夹在介电层130与RDL结构240之间。特别地，模塑料230的延伸部230a夹在介电层130的边缘部分与RDL结构240的IMD层250之间。
如图2B所示，移除图2A所示的载体基底200。如此，露出RDL结构310的一个IMD层320。接着，在RDL结构310上形成BSF290。在BSF290中形成一个或多个开口300并且该一个或多个开口300延伸进入RDL结构310的一个IMD层320。如此，通过开口300露出RDL结构310的一条导电线路330，以用于进一步的电连接。
根据本发明的一些实施例，在形成BSF290之后，执行分离工艺。例如，切割RDL结构240，模塑料230，RDL结构310及BSF290。如此，形成多个半导体封装。
如上所述，半导体封装可以堆叠在BSF290上并且通过开口300电性连接至导电通孔结构210。例如，如图3所示，半导体封装400垂直地堆叠在图2B所示的半导体封装结构上。如此，提供了封装上封装(PoP)结构。
图3为根据本发明一些实施例的半导体封装结构的横截面示意图。在图3与图1A～1G及2A～2B中，相同的元件使用相同的参考符号，并且出于简洁而不再描述。需要注意的是，图3所示的半导体封装400的结构仅是示例而不是对本发明的限制。
半导体封装400安装于RDL结构310上并且通过导电结构410电性连接至RDL结构310。导电结构410位于开口300中并且从BSF290中伸出。在一些实施例中，导电结构410可以为导电凸块(诸如微凸块(micro bump))，导电柱，导电膏结构，或者另一合适的导电结构。导电结构410可以包括：铜、焊料、或者另一合适的导电材料。在其他的一些实施例中，底部填充材料可以围绕导电结构410。
在一些实施例中，半导体封装400包括：基底420，至少一个半导体晶粒(如两个垂直堆叠的半导体晶粒430与440)，接合线450及模塑料460。在一些实施例中，基底420可以为PCB并且由PP或者另一合适的材料形成。基底420通过导电结构410电性连接至RDL结构310。
半导体晶粒430通过黏合层(诸如胶水或者另一合适的黏性材料)附着至基底420。半导体晶粒430通过其接垫431及接合线450电性连接至基底420。在一些实施例中，半导体晶粒430为存储器晶粒或者另一合适的半导体晶粒。半导体晶粒440通过黏合层(诸如胶水或者另一合适的黏性材料)附着至半导体晶粒430。半导体晶粒440通过其接垫441及接合线450电性连接至基底420。在一些实施例中，半导体晶粒440为存储器晶粒或者另一合适的半导体晶粒。在一些实施例中，半导体晶粒430与440均为DRAM晶粒。
模塑料460覆盖基底420及围绕半导体晶粒430与440。接合线450嵌入于模塑料460中。在一些实施例中，模塑料460由非导电材料形成，诸如环氧树脂、树脂、可塑聚合物或另一合适的模塑材料。
可以对本发明实施例做出许多的变形及/或修改。图4为根据本发明一些实施例的半导体封装结构的横截面示意图。在图4与图1A～1G中，相同的元件使用相同的参考符号，并且出于简洁而不再描述。
图4的半导体封装结构类似于图1G的半导体封装结构。两者之间的差异在于：在图1G中存在多个由模塑料230封闭的导电通孔结构210，而在图4中，在模塑料230中没有导电通孔结构。另外，在图1G中的BSF290包括：露出导电通孔结构210的开口300，而在图4中，在BSF290中没有开口300。
根据本发明实施例的半导体封装结构及其形成方法提供了各种优势。该半导体封装结构包括：晶粒。该晶粒包括：位于半导体主体上的绝缘层。在绝缘层中形成开口使得绝缘层的侧壁相对半导体主体的侧壁缩进。晶粒可由模塑料围绕。如此，模塑料包括：填充上述开口的延伸部。相应地，模塑料的侧壁与半导体主体的侧壁不共平面，使得模塑料可以作为用于释放应力的缓冲层。
具有延伸部(堆叠在半导体主体上)的模塑料可以阻止应力拉伸或者撕扯导电线路，诸如在模塑料上的RDL结构中的导电线路。因此，可以阻止由于应力集中而导致的导电线路的缺陷或者破裂。也可以缓和或者消除两种材料界面处的脱层，诸如半导体主体与模塑料之间的界面处的脱层。显著地改善半导体封装结构的质量和可靠性。
可以对本发明实施例做出许多变化及/或修改。根据本发明实施例的半导体封装结构及其形成方法可以用于形成三维(three-dimensional，3D)封装，2.5D封装，扇出封装，或者另一合适的封装。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (17)

1.一种半导体封装结构，其特征在于，包括：
半导体主体；
互连结构，设置在该半导体主体的表面上；
模塑料，围绕该半导体主体及该互连结构；以及
重分布层结构，设置在该互连结构及该模塑料上；
其中，该模塑料的一部分在该重分布层结构及该半导体主体之间延伸，并且该部分的模塑料位于该半导体主体的表面的正下方。
2.如权利要求1所述的半导体封装结构，其特征在于，该互连结构露出该半导体主体的表面的一部分，该部分的模塑料直接接触该半导体主体的表面的露出的部分。
3.如权利要求1所述的半导体封装结构，其特征在于，该互连结构包括：
介电层，设置在该半导体主体的表面上；
绝缘层，设置在该介电层的表面上，并且该介电层位于该半导体主体与该绝缘层之间；以及
导电结构，耦接至该重分布层结构，并且该介电层围绕该导电结构的底部，该绝缘层围绕该导电结构的顶部。
4.如权利要求3所述的半导体封装结构，其特征在于，该介电层完全覆盖该半导体主体的表面，该绝缘层露出该介电层的表面的部分；其中，该部分的模塑料夹在该重分布层结构和该介电层的表面的露出的部分之间。
5.如权利要求3所述的半导体封装结构，其特征在于，该半导体主体的长度大于该绝缘层的长度；
或者，该部分的模塑料堆叠在该半导体主体的表面上；
或者，该部分的模塑料的侧壁与该半导体主体的侧壁不共平面；
或者，该部分的模塑料围绕该绝缘层。
6.一种半导体封装结构，其特征在于，包括：
半导体主体；
导电垫，设置在该半导体主体的表面的下方；
重分布层结构，位于在该半导体主体的下方；
导电结构，位于该导电垫及该重分布层结构之间，其中该半导体主体的表面面向该重分布层结构；
绝缘层，位于该半导体主体的该表面与该重分布层结构之间，其中该表面的部分从该绝缘层中露出；以及
模塑料，围绕该半导体主体并且覆盖该表面的该部分。
7.如权利要求6所述的半导体封装结构，其特征在于，该模塑料从该半导体主体的侧壁横向地延伸至该绝缘层的侧壁。
8.如权利要求7所述的半导体封装结构，其特征在于，该模塑料的延伸长度介于1μm～200μm之间。
9.如权利要求6所述的半导体封装结构，其特征在于，该模塑料的邻接该绝缘层的侧壁与该半导体主体的侧壁不共平面；
或者，覆盖该表面的该部分的模塑料夹在该重分布层结构与该半导体主体之间。
10.如权利要求6所述的半导体封装结构，其特征在于，进一步包括：
导电通孔结构，耦接至该重分布层结构；
其中，该模塑料的第一部分位于该导电通孔结构与该绝缘层之间，该模塑料的第二部分位于该导电通孔结构与该半导体主体之间，并且该模塑料的第一部分的宽度大于该模塑料的第二部分的宽度。
11.如权利要求6所述的半导体封装结构，其特征在于，进一步包括：
黏合层，其中，该半导体主体的一部分位于该黏合层与该绝缘层之间以及另一部分位于该黏合层与该模塑料之间。
12.一种形成半导体封装结构的方法，其特征在于，包括：
提供晶粒，其中该晶粒包括：半导体主体；导电结构，设置在该半导体主体的表面上；以及绝缘层，围绕该导电结构，其中该半导体主体的表面的部分从该绝缘层中露出；
形成围绕该半导体主体及覆盖该半导体主体的表面的露出的部分的模塑料；以及
在该模塑料及该绝缘层上形成重分布层结构。
13.如权利要求12所述的形成半导体封装结构的方法，其特征在于，形成该晶粒的步骤包括：
在该绝缘层中形成第一开口，以露出该半导体主体的表面的部分；以及
在该半导体主体中形成沿该第一开口方向的第二开口。
14.如权利要求13所述的形成半导体封装结构的方法，其特征在于，该第一开口宽于该第二开口。
15.如权利要求13所述的形成半导体封装结构的方法，其特征在于，该第一开口与该第二开口连通。
16.如权利要求12所述的形成半导体封装结构的方法，其特征在于，在形成该模塑料之后，该方法进一步包括：对该模塑料执行减薄工艺。
17.一种形成半导体封装结构的方法，其特征在于，包括：
提供晶粒，其中该晶粒包括：半导体主体；介电层，设置在该半导体主体的表面上；以及绝缘层，设置在该介电层的表面上，其中该介电层位于该半导体主体与该绝缘层之间，该介电层的表面的一部分从该绝缘层中露出；
形成围绕该半导体主体及覆盖该介电层的表面的露出的部分的模塑料，；以及
在该模塑料及该绝缘层上形成重分布层结构。
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