CN108666280A - 封装结构 - Google Patents

封装结构 Download PDF

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Publication number
CN108666280A
CN108666280A CN201710992581.5A CN201710992581A CN108666280A CN 108666280 A CN108666280 A CN 108666280A CN 201710992581 A CN201710992581 A CN 201710992581A CN 108666280 A CN108666280 A CN 108666280A
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CN
China
Prior art keywords
plastic compound
dielectric layer
layer
semiconductor device
wafer
Prior art date
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Pending
Application number
CN201710992581.5A
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English (en)
Inventor
戴志轩
郭婷婷
黄育智
陈志华
蔡豪益
刘重希
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN108666280A publication Critical patent/CN108666280A/zh
Pending legal-status Critical Current

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Abstract

一种封装结构，包含半导体装置、第一塑模化合物、通孔、第一介电层、第一重分布线，和第二塑模化合物。第一塑模化合物与半导体装置的侧壁接触。通孔位于第一塑模化合物，并电性连接到半导体装置。第一介电层在半导体装置上。第一重分布线在第一介电层中并且电性连接到半导体装置和通孔。第二塑模化合物与第一介电层的侧壁接触。

Description

封装结构
技术领域
本揭露是关于封装结构。
背景技术
半导体工业透过不断地减少最小特征的尺寸，使得更多元件被整合至特定的区域，以达到持续性地提高各种电子元件(如晶体管、二极管、电阻、电容等)的整合密度的情况。这些较小的电子元件在部分应用中也有较小的封装。用于半导体的一些较为小型的封装包括四方封装(quad flat pack，QFP)、插针网格阵列(pin grid array，PGA)、球栅阵列(ball grid array，BGA)、覆晶封装(flip chips，FC)、三维集成电路(three dimensionalintegrated circuits，3DIC)、晶圆级封装(wafer level package，WLP)、铜柱导线直连(bump-on-trace，BOT)、封装对封装(package on package，PoP)结构。
发明内容
本揭露实施例提供了一种封装结构包含半导体装置、第一塑模化合物、通孔、第一介电层、第一重分布线，和第二塑模化合物。第一塑模化合物与半导体装置的侧壁接触。通孔位于第一塑模化合物，并电性连接到半导体装置。第一介电层在半导体装置上。第一重分布线在第一介电层中并且电性连接到半导体装置和通孔。第二塑模化合物与第一介电层的侧壁接触。
附图说明
当与附图一起阅读时，可以从以下的详细描述中更好的理解本揭露的各个面向。值得注意的是，根据工业上的标准做法，各种特征并没有按照比例进行绘制。事实上，为了清楚地讨论，可以任意的增加或减少各种特征尺寸。
图1为根据本揭露的一些实施例的形成封装结构的方法的流程图；
图2-16为根据本揭露的一些实施例的各个阶段的封装结构的横截面图；
图17为根据本揭露的一些实施例的封装结构的俯视图。
具体实施方式
以下揭露提供了用于实行提供主题的不同特征的许多不同的实施例或范例。以下描述的组件和安排的具体范例以简化本揭露。这些仅仅是范例，而非限制性的。例如，在接下来的描述中，在第二特征之上或设置形成的第一特征可以包括第一和第二特征形成直接接触的实施例，并且可以包括在第一和第二特征之间形成附加特征的实施例，使得第一和第二特征可以不直接接触。此外，本揭露可以重复各种在各种范例中的附图标记和/或文字。该重复是为了使目的简单且清楚，本身并不讨论各种实施例和/或配置之间的关系。
此外，如图所示，为了便于描述一元件或特征与另一元件或特征之间的关系，在本文中可以使用“在下”、“在……之下”、“较低的”、“在……之上”、“较高的”等空间相对术语。空间相对术语意旨包括除了图中所指示的定位之外的使用或操作不同装置的不同取向。该装置可以以其他方法定向(旋转90度或其他方向)，并且此处使用的空间相对描述，也可以相应地被解释。
同时也包含了其他的特征和过程。例如，测试结构可以帮助3D封装或3DIC设备的验证测试。测试结构包含例如：允许测试3D封装或3DIC的重分布层或基板上形成的测试焊垫，使用探针和/或探针卡等。验证测试可以在中间结构与最终结构上执行，此外，本揭露的结构和方法可以与测试的方法结合使用，当中包含已知优良模具的中间验证，以提高产量并且降低成本。
图1为根据本揭露的一些实施例的形成封装结构的方法的流程图。图2-16为根据本揭露的一些实施例的各个阶段的封装结构的横截面图。该方法从图1的区块10开始，其中在载体210上形成具有重分布层120的介电层110。参见图2，介电层110在载体210上形成。载体210可以是空白玻璃载体，空白陶瓷载体等。介电层110可以为聚合物层。聚合物层可以包含如聚亚酰胺(polyimide)、聚苯并恶唑(polybenzoxazole，PBO)、苯并环丁烯(benzocyclobutene，BCB)、味素积累膜(ajinomoto buildup film，ABF)、阻焊膜(solderresist film，SR)等。此外，重分布层120在介电层110中形成，且重分布层120的一部分透过介电层110的部分暴露出来。在一些实施例中，重分布层120一层的形成包括形成毯覆铜种子层，在毯覆铜种子层上形成和图案化遮罩层，进行电镀以形成重分布层120，移除遮罩层，并执行闪蚀(flash etching)以除去未被重分布层120覆盖的毯覆铜种子层。在替代实施例中，重分布层120透过沉积金属层，图案化金属层，以及介电层110填充重分布层120和之间的间隙而形成。图2所显示的重分布层的一层是为了用于说明，而各种实施例在本揭露中不受限于此方面。在替代实施例中，具有多层的重分布层120的介电层110在载体210上形成。
该方法延续到图1的区块11，参见图3，举例来说，透过PVD或金属箔压层，一种子层132在介电层110和暴露的重分布层120上形成。种子层132可以包含铜、铜合金、铝、钛、钛合金或其合金。在一些实施例中，种子层132包含在钛层之上的钛层与铜层。在替代实施例中，种子层132为铜层。
该方法延续到图1的区块12，其中在种子层132上形成具有开口232的光抗蚀剂230。参见图4，光抗蚀剂230被涂布于种子层132上。开口232形成于光抗蚀剂230中，而种子层132的一部分暴露于开口232中。
该方法延续到图1的区块13，参见图5，导电特征134分别透过电镀，其中如电镀、无电镀或金属浆糊印刷的方法，形成于光抗蚀剂230的开口232上，导电特征134分别电镀于开口232下面的种子层的暴露部分之上。导电特征134可以包含铜、铝、钨、镍、焊料、银或其合金。第三导电特征134的俯视图可以为矩形、正方形、圆形等，第三导电特征134高度根据随后放置的半导体装置140的厚度决定。
该方法延续到图1的区块14。在电镀导电特征134之后，去除光抗蚀剂230，得到的结构如图6所示。在去除光抗蚀剂230之后，种子层132的部分暴露出来。
该方法延续到图1的区块15。参考图7，执行蚀刻步骤用以移除未被导电特征134覆盖的种子层132的暴露部分，其中蚀刻步骤可以包含异向性蚀刻。另一方面，由第三导电特征134覆盖的种子层132的一部分维持不被蚀刻。在整份说明书中，导电特征134和种子层132的其余底层部分组合在一起被称为通过集成扇出(InFO)互连通孔(TIV)130，其他则称为通孔。尽管种子层132显示出为自导电特征134为分开的层，但当种子层132由与相应的导电特征134相似或基本上相同的材料制成时，种子层132可以与导电特征134合并，基本上他们之间没有可区分的介面。在替代实施例中，种子层132与上覆的导电特征134之间存在可区分的介面。
该方法延续到图1的区块16。图8显示出半导体装置140在介电层110上的放置。半导体装置140可以透过粘着剂142而被设置在介电层110上，其中半导体装置140可以是逻辑半导体装置包含逻辑晶体管。在一些实施例中，半导体装置140被设计于可携式装置应用，并且为中央处理单元(CPU)的芯片，感测芯片等。每个半导体装置140包含半导体基板141(如硅基板)，该基板与粘着剂142接触，意即其中半导体装置的背面(即下表面)与粘着剂142接触。
在一些实施例中，导电焊垫143(例如铜柱)形成为半导体装置140的顶部，并且电耦合到半导体装置140中的装置如晶体管(未显示)。在一些实施例中，一介电层144在各半导体装置140的顶表面形成，而导电焊垫143在介电层144中至少具有下部分。在一些实施例中，导电焊垫143的顶表面可以与介电层144的顶表面实质上同水平。或者，不形成介电层144，且导电焊垫143从相应的半导体装置140伸出(该布置未显示)。
该方法延续到图1的区块17。参考图9，一第一塑模化合物150为了与半导体装置140和互连通孔130接触，在介电层110上形成。第一塑模化合物150为成型于半导体装置140和互连通孔130周围。第一塑模化合物150填充了半导体装置140和互连通孔130之间的间隙，且可以与介电层110接触。在一些实施例中，第一塑模化合物150可以包含一种基于聚合物的材料。“聚合物”可以代表热固性聚合物，热塑性聚合物，或其化合物。基于聚合物的材料可以包含如塑胶材料、环氧树脂(epoxy resin)、聚亚酰胺(polyimide)、聚对苯二甲酸乙二醇酯(polyethylene terephthalate，PET)、聚氯乙烯(polyvinyl chloride，PVC)、聚甲基丙烯酸甲酯(polymethylmethacrylate，PMMA)、掺杂有纤维的填料的聚合物成分、粘土、陶瓷、无机粒子，或其化合物的组合。
在一些实施例中，成型加工为一暴露成型，其中半导体装置140和互连通孔130的顶表面通过第一塑模化合物150露出。此外，可以使用传递成型来成型。在一些实施例中，使用模具(未显示)进行成型以覆盖半导体装置140和互连通孔130的顶表面，使得所得到的第一塑模化合物150不会覆盖半导体装置140和互连通孔130的顶表面。在传递成型期间，模具的内部空间被抽真空，且成型材料被注入到模具的内部空间以形成第一塑模化合物150。
得到的结构如图9所示，其中第一塑模化合物150与半导体装置140和互连通孔130的侧壁接触。由于为暴露成型，互连通孔130的顶端和导电焊垫143的顶端为和第一塑模化合物150的顶表面实质上同水平(共平面)。第一塑模化合物150的厚度H1和互连通孔130的厚度实质上相同，也就是说，互连通孔130延伸通过第一塑模化合物150。
该方法延续到图1的区块18，其中具有重分布层170的一介电层160，形成于半导体装置140、第一塑模化合物150和互连通孔130上。参考图10，介电层160形成于第一塑模化合物150，半导体装置140和互连通孔130上，使得半导体装置140和互连通孔130位在介电层110和介电层160之间。此外，重分布层170形成在介电层160中且设置在第一塑模化合物150上以电性连接到半导体装置140和互连通孔130。换言之，介电层160具有重分布层170，形成在半导体装置140，第一塑模化合物150和互连通孔130上。在一些实施例中，重分布层170一层的形成包含形成毯覆铜种子层，在毯覆铜种子层上形成和图案化遮罩层，进行电镀以形成重分布层170，移除遮罩层，并执行闪蚀以除去未被重分布层170覆盖的毯覆铜种子层。在替代实施例中，重分布层170透过在金属层沉积，在金属层图案化，以及填充重分布层170和介电层160之间的间隙而形成。
重分布层170可以包含一金属或一金属合金如铝、铜、钨和/或其合金。这些实施例中，介电层160可以包含聚亚酰胺(polyimide)，苯并环丁烯(benzocyclobutene，BCB)，聚苯并恶唑(polybenzoxazole，PBO)等聚合物。或者，介电层160可以包含无机介电材料如氧化硅，氮化硅，碳化硅，氮氧化硅等。
该方法延续到图1的区块19，参考图11，半导体装置140和第一塑模化合物150形成介电层160和重分布层170在互连通孔130，一切割带220粘着到介电层160上。接下来，图10中具有切割带220的结构可以翻转，而后将载体210自介电层110暂时解焊。
该方法延续到图1的区块20。自从载体210自介电层110暂时解焊后，对于介电层110进行图案化以形成开口111，以至少暴露部分重分布层120，且得到的结果如图11所示。在一些实施例中，开口111可以使用光刻工艺或是透过激光钻孔形成于介电层110中。
该方法延续到图1的区块21，其中开口111中形成焊料凸块180和180a。参考图12，焊料凸块180和180a形成在重分布层120的暴露部分上。焊料凸块180和180a可以透过涂布于露出的重分布层120的锡膏印刷制程来形成。根据重分布层120暴露的位置，可以使用模板将锡膏印刷在重分布层120的顶部。应用回焊工艺，可以使得锡膏聚集在重分布层120的顶部的焊料凸块180和180a。在一些实施例中，焊料凸块180与焊料凸块180a的尺寸不同。例如，焊料凸块180a比焊料凸块180小。
该方法延续到图1的区块22，其中第一塑模化合物150被切割通过。参考图12，在形成焊料凸块180和180a之后，沿着切割线L1切割介电层110，第一塑模化合物150和介电层160进行分割处理，使得可以形成切割带220上的多个芯片级封装155。
该方法延续到图1的区块23，其中介电层110附于载体210a。参考图13，在切割步骤之后，从切割带220拾取芯片级封装155，而后拾取的芯片级封装155放置在载体210a的晶圆贴覆膜(die attach film，DAF)240上。因此，载体210上的晶圆贴覆膜240可以覆盖焊料凸块180，180a和介电层110以用于保护。换句话说，焊料凸块180和180a嵌入在晶圆贴覆膜240中。图13所示拾取芯片级封装155的数量是为了说明，且本揭露的各种实施例在这方面不受限制。在一些实施例中，载体210a可以与第2-10图所示的载体210相同。在替代实施例中，载体210a不同于载体210，且本揭露的各种实施例在这方面不受限制。例如，载体210a可以是胚料玻璃载体，胚料陶瓷载体等。
该方法延续到图1的区块24，其中第二塑模化合物190围绕着第一塑模化合物150形成。参考图13，在芯片级封装155被放置在的晶圆贴覆膜240后，第二塑模化合物190围绕着芯片级封装155成型。介电层110，介电层160和第一塑模化合物150都被第二塑模化合物190所包围。介电层110的底表面实质上与第二塑模化合物190的底表面共平面，以及介电层160的顶表面实质上与第二塑模化合物190的顶表面共平面。第二塑模化合物190可以是聚合物、树脂等。第二塑模化合物190与第一塑模化合物150可以由相同的材料或是不同的材料制成，且本揭露的各种实施例在这方面不受限制。在一些实施例中，第二塑模化合物190包含成型填料，可以做为成型化合物和底部填充物。因此，第二塑模化合物190被填充于两个相邻的芯片级封装155之间的间隙，且可以接触并围绕芯片级封装155。
在一些实施例中，成型为暴露成型，其中芯片级封装155的顶表面透过第二塑模化合物190露出。此外，可以使用传递成型来进行成型。在一些实施例中，使用模具(未显示)进行成型以覆盖芯片级封装155的顶表面，使得所得到的第二塑模化合物190不会覆盖芯片级封装155的顶表面。在传递成型的过程中，将模具的内部空间成真空，并将成型材料注入模具的内部空间以形成第二塑模化合物190。
由于为暴露成型，第二塑模化合物190的顶表面可以实质上与芯片级封装155的顶表面同平面。在一些实施例中，第二塑模化合物190的顶表面实质上与芯片级封装155的顶表面共平面。在替代实施例中，第二塑模化合物190的顶表面比芯片级封装155的顶表面稍微低一些，且本揭露的各种实施例在这方面不受限制。
第二塑模化合物190于介电层160，第一塑模化合物150，和介电层110周围形成。此外，第二塑模化合物190的厚度H2与相应芯片级封装155的第一塑模化合物150，介电层110和介电层160的总厚度H3实质上相同。
由于第二塑模化合物190成型芯片级封装155，因此可以减小每一个芯片级封装155的面积与相应的半导体装置140的面积的比率。在芯片级封装155的制造过程(如图2至图12)中，由于第一塑模化合物150的减少，可以预防芯片级封装155的翘曲，因此提高了芯片级封装155的制程良率和可靠产量。
该方法延续到图1的区块25和26，参考图14，在第二塑模化合物190成型后，一切割带220a粘附到第二塑模化合物190和介电层160上。接着，可以翻转图13具有切割带220a的结构，然后载体210a从晶圆贴覆膜240解焊，所得到的结构如图14所示。在一些实施例中，切割带220a可以与图11和图12的切割带220相同。在替代实施例中，切割带220a不同于切割带220，且本揭露的各种实施例在这方面不受限制。
该方法延续到图1的区块27，其中晶圆贴覆膜240已经被去除。参考图15，在移除载体210a之后，将晶圆贴覆膜240从芯片级封装155清除，使得焊料凸块180，180a和介电层110暴露。
该方法延续到区块28，其中切割第二塑模化合物190至少产生一封装结构100。参考图15，切割步骤为沿着切割线L2切割图15的结构。具有嵌入式芯片级封装155的第二塑模化合物190被切割以形成多个独立封装，且每个封装都具有半导体装置140，第一塑模化合物150，和第二塑模化合物190。换句话说，在切割步骤后，从切割带220a拾取至少一封装结构100，获得如第16和17图的封装结构100。在切割步骤中，封装结构100的尺寸可以透过第二塑模化合物190的切割位置来决定，因此可以实现封装结构100所需的尺寸。
图16为图17沿着第16-16线所截取的封装结构100。由于第二塑模化合物190的厚度H2与第一塑模化合物150，介电层110和介电层160的总厚度H3实质上相同，第一塑模化合物150的厚度H1比第二塑模化合物190的厚度H2较小。此外，第一塑模化合物150与半导体装置140的侧壁145接触。第二塑模化合物190与介电层110的侧壁112，第一塑模化合物150的侧壁152和介电层160的侧壁162接触。换句话说，介电层110和第二塑模化合物190具有介面，第一塑模化合物150和第二塑模化合物190具有介面，且介电层160和第二塑模化合物190具有介面。
图17为根据且本揭露的一些实施例的封装结构100的俯视图。半导体装置140被第一塑模化合物150所包围，且第一塑模化合物150被第二塑模化合物190所包围。换句话说，第一塑模化合物150位于半导体装置140与第二塑模化合物190之间，因此第二塑模化合物190不含导电特征134。由于在芯片级封装155成型后形成第二塑模化合物190，第二塑模化合物190可以将芯片级封装155扩展到所需的尺寸。
在前述的封装结构中，利用两种成型步骤来形成封装结构。最终封装结构的尺寸可以透过设置在第一塑模化合物的周围的第二塑模化合物的不同区域来决定。换句话说，封装来结构可以利用第二塑模化合物来实现多样化的产品尺寸。此外，在第二塑模化合物中或其上没有重分布层和介电层。因此，可以降低制造封装结构的成本。
根据一些实施例，封装结构包括半导体装置、第一塑模化合物、通孔、第一介电层、第一重分布线，和第二塑模化合物。第一塑模化合物与半导体的侧壁接触。通孔位于第一塑模化合物，并电性连接到半导体装置和通孔。第一介电层在半导体装置上。第一重分布线在第一介电层中并且电性连接到半导体装置。第二塑模化合物与第一介电层的侧壁接触。
根据一些实施例，第一塑模化合物被第二塑模化合物所包围。
根据一些实施例，第一塑模化合物与第二塑模化合物接触。
根据一些实施例，第一介电层被第二塑模化合物所包围。
根据一些实施例，第一塑模化合物的厚度小于第二塑模化合物的厚度。
根据一些实施例，封装结构还包含第二介电层和第二重分布线。半导体装置设置在第一介电层第二介电层之间。第二重分布线设置在第二介电层中，并电性连接半导体装置。
根据一些实施例，第二塑模化合物与第二介电层的侧壁接触。
根据一些实施例，第二介电层的底表面与第二塑模化合物的底表面实质上共平面。
根据一些实施例，第一介电层的顶表面与第一塑模化合物的顶表面实质上共平面。
根据一些实施例，封装结构包括半导体装置、第一塑模化合物、通孔、第一介电层、第一重分布线，和第二塑模化合物。第一塑模化合物与半导体的侧壁接触。通孔位于第一塑模化合物并且电性连接到半导体装置。第一介电层在半导体装置上。第一重分布线在第一介电层中并且电性连接到半导体装置和通孔。第二塑模化合物在第一塑模化合物的周围，且第一塑模化合物和第二塑模化合物具有介面。
根据一些实施例，第二塑模化合物围绕第一介电层。
根据一些实施例，第一介电层和第二塑模化合物间具有介面。
根据一些实施例，第二塑模化合物不具有导电特征。
根据一些实施例，形成封装结构的方法，包含在介电层上形成通孔，其中通孔与介电层中的重分布线电性连接；在介电层上设置半导体装置；在介电层上形成第一塑模化合物，其中半导体装置和通孔嵌入第一塑模化合物；以及在第一塑模化合物周围形成第二塑模化合物。
根据一些实施例，形成封装结构的方法还包含切割至少通过第一塑模化合物。
根据一些实施例，第二塑模化合物是在切割步骤之后形成。
根据一些实施例，形成封装结构的方法还包含将介电层图案化以露出重分布线，以及形成焊料凸块电性连接到重分布线。
根据一些实施例，第二塑模化合物是在形成焊料凸块后形成。
根据一些实施例，形成封装结构的方法还包含在形成第二塑模化合物之前，使用晶圆贴覆膜将介电层附着到载体上，其中焊料凸块嵌入晶圆贴覆膜中。
根据一些实施例，形成封装结构的方法还包含切割通过第二塑模化合物。
前面概述了数个实施例的特征，使得本领域技术人员可以更好的理解本揭露的各个方面。本领域技术人员应该要理解，他们可以容易使用本揭露为基础用于设计或修改用于执行其他程序或结构以完成相同的目的和/或实现本文所介绍实施例的相同的优点。本领域技术人员应该还要意识到，这样的等效架构不能脱离本揭露的精神和范围，并且在不脱离本揭露的精神和范围的情况下，他们可以进行各种变化、替换和改变。

Claims (1)

1.一种封装结构，其特征在于，包含：
一半导体装置；
一第一塑模化合物，与该半导体装置的侧壁接触；
一通孔，设置于该第一塑模化合物中，并电性连接该半导体装置；
一第一介电层，设置在该半导体装置上；
一第一重分布线，设置在该第一介电层中，且电性连接该半导体装置和该通孔；以及
一第二塑模化合物，与该第一介电层的侧壁接触。
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