TW201838124A - 封裝結構 - Google Patents

封裝結構 Download PDF

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Publication number
TW201838124A
TW201838124A TW106136205A TW106136205A TW201838124A TW 201838124 A TW201838124 A TW 201838124A TW 106136205 A TW106136205 A TW 106136205A TW 106136205 A TW106136205 A TW 106136205A TW 201838124 A TW201838124 A TW 201838124A
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Taiwan
Prior art keywords
molding compound
dielectric layer
semiconductor device
layer
redistribution
Prior art date
Application number
TW106136205A
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English (en)
Inventor
戴志軒
郭婷婷
黃育智
陳志華
蔡豪益
劉重希
余振華
Original Assignee
台灣積體電路製造股份有限公司
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Publication of TW201838124A publication Critical patent/TW201838124A/zh

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Abstract

一種封裝結構包含半導體裝置、第一塑模化合物、通孔、第一介電層、第一重分佈線，和第二塑模化合物。第一塑模化合物與半導體裝置的側壁接觸。通孔位於第一塑模化合物，並電性連接到半導體裝置。第一介電層在半導體裝置上。第一重分佈線在第一介電層中並且電性連接到半導體裝置和通孔。第二塑模化合物與第一介電層的側壁接觸。

Description

封裝結構
本揭露是關於封裝結構。
半導體工業透過不斷地減少最小特徵的尺寸，使得更多元件被整合至特定的區域，以達到持續性地提高各種電子元件(如電晶體、二極體、電阻、電容等)的整合密度的情況。這些較小的電子元件在部分應用中也有較小的封裝。用於半導體的一些較為小型的封裝包括四方封裝(quad flat pack，QFP)、插針網格陣列(pin grid array，PGA)、球柵陣列(ball grid array，BGA)、覆晶封裝(flip chips，FC)、三維積體電路(three dimensional integrated circuits，3DIC)、晶圓級封裝(wafer level package，WLP)、銅柱導線直連(bump-on-trace，BOT)、封裝對封裝(package on package，PoP)結構。
本揭露實施例提供了一種封裝結構包含半導體裝置、第一塑模化合物、通孔、第一介電層、第一重分佈線，和第二塑模化合物。第一塑模化合物與半導體裝置的側壁接觸。通孔位於第一塑模化合物，並電性連接到半導體裝置。第一介 電層在半導體裝置上。第一重分佈線在第一介電層中並且電性連接到半導體裝置和通孔。第二塑模化合物與第一介電層的側壁接觸。
110‧‧‧介電層
111‧‧‧開口
112‧‧‧側壁
120‧‧‧重分佈層
130‧‧‧互連通孔
132‧‧‧種子層
134‧‧‧導電特徵
140‧‧‧半導體裝置
141‧‧‧半導體基板
142‧‧‧黏著劑
143‧‧‧導電焊墊
144‧‧‧介電層
150‧‧‧第一塑模化合物
152‧‧‧側壁
155‧‧‧芯片級封裝
160‧‧‧介電層
162‧‧‧側壁
170‧‧‧重分佈層
180、180a‧‧‧焊料凸塊
190‧‧‧第二塑模化合物
210、210a‧‧‧載體
220‧‧‧切割帶
230‧‧‧光抗蝕劑
232‧‧‧開口
240‧‧‧晶圓貼覆膜
L1、L2‧‧‧切割線
H1、H2、H3‧‧‧厚度
當與附圖一起閱讀時，可以從以下的詳細描述中更好的理解本揭露的各個面向。值得注意的是，根據工業上的標準做法，各種特徵並沒有按照比例進行繪製。事實上，為了清楚地討論，可以任意的增加或減少各種特徵尺寸。
第1圖為根據本揭露的一些實施例的形成封裝結構的方法的流程圖。
第2-16圖為根據本揭露的一些實施例的各個階段的封裝結構的橫截面圖。
第17圖為根據本揭露的一些實施例的封裝結構的俯視圖。
以下揭露提供了用於實行提供主題的不同特徵的許多不同的實施例或範例。以下描述的組件和安排的具體範例以簡化本揭露。這些僅僅是範例，而非限制性的。例如，在接下來的描述中，在第二特徵之上或設置形成的第一特徵可以包括第一和第二特徵形成直接接觸的實施例，並且可以包括在第一和第二特徵之間形成附加特徵的實施例，使得第一和第二特徵可以不直接接觸。此外，本揭露可以重複各種在各種範例中 的附圖標記和/或文字。該重複是為了使目的簡單且清楚，本身並不討論各種實施例和/或配置之間的關係。
此外，如圖所示，為了便於描述一元件或特徵與另一元件或特徵之間的關係，在本文中可以使用「在下」、「在……之下」、「較低的」、「在……之上」、「較高的」等空間相對術語。空間相對術語意旨包括除了圖中所指示的定位之外的使用或操作不同裝置的不同取向。該裝置可以以其他方法定向(旋轉90度或其他方向)，並且此處使用的空間相對描述，也可以相應地被解釋。
同時也包含了其他的特徵和過程。例如，測試結構可以幫助3D封裝或3DIC設備的驗證測試。測試結構包含例如：允許測試3D封裝或3DIC的重分佈層或基板上形成的測試焊墊，使用探針和/或探針卡等。驗證測試可以在中間結構與最終結構上執行，此外，本揭露的結構和方法可以與測試的方法結合使用，當中包含已知優良模具的中間驗證，以提高產量並且降低成本。
第1圖為根據本揭露的一些實施例的形成封裝結構的方法的流程圖。第2-16圖為根據本揭露的一些實施例的各個階段的封裝結構的橫截面圖。該方法從第1圖的區塊10開始，其中在載體210上形成具有重分佈層120的介電層110。參見第2圖，介電層110在載體210上形成。載體210可以是空白玻璃載體，空白陶瓷載體等。介電層110可以為聚合物層。聚合物層可以包含如聚亞醯胺(polyimide)、聚苯并噁唑(polybenzoxazole，PBO)、苯並環丁烯(benzocyclobutene， BCB)、味素積累膜(ajinomoto buildup film，ABF)、阻焊膜(solder resist film，SR)等。此外，重分佈層120在介電層110中形成，且重分佈層120的一部分透過介電層110的部分暴露出來。在一些實施例中，重分佈層120一層的形成包括形成毯覆銅種子層，在毯覆銅種子層上形成和圖案化遮罩層，進行電鍍以形成重分佈層120，移除遮罩層，並執行閃蝕(flash etching)以除去未被重分佈層120覆蓋的毯覆銅種子層。在替代實施例中，重分佈層120透過沉積金屬層，圖案化金屬層，以及介電層110填充重分佈層120和之間的間隙而形成。第2圖所顯示的重分佈層的一層是為了用於說明，而各種實施例在本揭露中不受限於此方面。在替代實施例中，具有多層的重分佈層120之介電層110在載體210上形成。
該方法延續到第1圖的區塊11，參見第3圖，舉例來說，透過PVD或金屬箔壓層，一種子層132在介電層110和暴露的重分佈層120上形成。種子層132可以包含銅、銅合金、鋁、鈦、鈦合金或其合金。在一些實施例中，種子層132包含在鈦層之上的鈦層與銅層。在替代實施例中，種子層132為銅層。
該方法延續到第1圖的區塊12，其中在種子層132上形成具有開口232的光抗蝕劑230。參見第4圖，光抗蝕劑230被塗佈於種子層132上。開口232形成於光抗蝕劑230中，而種子層132的一部分暴露於開口232中。
該方法延續到第1圖的區塊13，參見第5圖，導電特徵134分別透過電鍍，其中如電鍍、無電鍍或金屬漿糊印刷 的方法，形成於光抗蝕劑230的開口232上，導電特徵134分別電鍍於開口232下面的種子層的暴露部分之上。導電特徵134可以包含銅、鋁、鎢、鎳、焊料、銀或其合金。第三導電特徵134的俯視圖可以為矩形、正方形、圓形等，第三導電特徵134高度根據隨後放置的半導體裝置140的厚度決定。
該方法延續到第1圖的區塊14。在電鍍導電特徵134之後，去除光抗蝕劑230，得到的結構如第6圖所示。在去除光抗蝕劑230之後，種子層132的部分暴露出來。
該方法延續到第1圖的區塊15。參考第7圖，執行蝕刻步驟用以移除未被導電特徵134覆蓋的種子層132的暴露部分，其中蝕刻步驟可以包含異向性蝕刻。另一方面，由第三導電特徵134覆蓋的種子層132的一部分維持不被蝕刻。在整份說明書中，導電特徵134和種子層132的其餘底層部分組合在一起被稱為通過集成扇出(InFO)互連通孔(TIV)130，其他則稱為通孔。儘管種子層132顯示出為自導電特徵134為分開的層，但當種子層132由與相應的導電特徵134相似或基本上相同的材料製成時，種子層132可以與導電特徵134合併，基本上他們之間沒有可區分的介面。在替代實施例中，種子層132與上覆的導電特徵134之間存在可區分的介面。
該方法延續到第1圖的區塊16。第8圖顯示出半導體裝置140在介電層110上的放置。半導體裝置140可以透過黏著劑142而被設置在介電層110上，其中半導體裝置140可以是邏輯半導體裝置包含邏輯電晶體。在一些實施例中，半導體裝置140被設計於可攜式裝置應用，並且為中央處理單元(CPU) 的芯片，感測芯片等。每個半導體裝置140包含半導體基板141(如矽基板)，該基板與黏著劑142接觸，意即其中半導體裝置的背面(即下表面)與黏著劑142接觸。
在一些實施例中，導電焊墊143(例如銅柱)形成為半導體裝置140的頂部，並且電耦合到半導體裝置140中的裝置如電晶體(未顯示)。在一些實施例中，一介電層144在各半導體裝置140的頂表面形成，而導電焊墊143在介電層144中至少具有下部分。在一些實施例中，導電焊墊143的頂表面可以與介電層144的頂表面實質上同水平。或者，不形成介電層144，且導電焊墊143從相應的半導體裝置140伸出(該佈置未顯示)。
該方法延續到第1圖的區塊17。參考第9圖，一第一塑模化合物150為了與半導體裝置140和互連通孔130接觸，在介電層110上形成。第一塑模化合物150為成型於半導體裝置140和互連通孔130周圍。第一塑模化合物150填充了半導體裝置140和互連通孔130之間的間隙，且可以與介電層110接觸。在一些實施例中，第一塑模化合物150可以包含一種基於聚合物的材料。「聚合物」可以代表熱固性聚合物，熱塑性聚合物，或其化合物。基於聚合物的材料可以包含如塑膠材料、環氧樹脂(epoxy resin)、聚亞醯胺(polyimide)、聚對苯二甲酸乙二醇酯(polyethylene terephthalate，PET)、聚氯乙烯(polyvinyl chloride，PVC)、聚甲基丙烯酸甲酯(polymethylmethacrylate，PMMA)、摻雜有纖維的填料的聚合物成分、黏土、陶瓷、無機粒子，或其化合物的組合。
在一些實施例中，成型加工為一暴露成型，其中半導體裝置140和互連通孔130的頂表面通過第一塑模化合物150露出。此外，可以使用傳遞成型來成型。在一些實施例中，使用模具(未顯示)進行成型以覆蓋半導體裝置140和互連通孔130的頂表面，使得所得到的第一塑模化合物150不會覆蓋半導體裝置140和互連通孔130的頂表面。在傳遞成型期間，模具的內部空間被抽真空，且成型材料被注入到模具的內部空間以形成第一塑模化合物150。
得到的結構如第9圖所示，其中第一塑模化合物150與半導體裝置140和互連通孔130的側壁接觸。由於為暴露成型，互連通孔130的頂端和導電焊墊143的頂端為和第一塑模化合物150的頂表面實質上同水平(共平面)。第一塑模化合物150的厚度H1和互連通孔130的厚度實質上相同，也就是說，互連通孔130延伸通過第一塑模化合物150。
該方法延續到第1圖的區塊18，其中具有重分佈層170的一介電層160，形成於半導體裝置140、第一塑模化合物150和互連通孔130上。參考第10圖，介電層160形成於第一塑模化合物150，半導體裝置140和互連通孔130上，使得半導體裝置140和互連通孔130位在介電層110和介電層160之間。此外，重分佈層170形成在介電層160中且設置在第一塑模化合物150上以電性連接到半導體裝置140和互連通孔130。換言之，介電層160具有重分佈層170，形成在半導體裝置140，第一塑模化合物150和互連通孔130上。在一些實施例中，重分佈層170一層的形成包含形成毯覆銅種子層，在毯覆銅種子層 上形成和圖案化遮罩層，進行電鍍以形成重分佈層170，移除遮罩層，並執行閃蝕以除去未被重分佈層170覆蓋的毯覆銅種子層。在替代實施例中，重分佈層170透過在金屬層沉積，在金屬層圖案化，以及填充重分佈層170和介電層160之間的間隙而形成。
重分佈層170可以包含一金屬或一金屬合金如鋁、銅、鎢和/或其合金。這些實施例中，介電層160可以包含聚亞醯胺(polyimide)，苯並環丁烯(benzocyclobutene，BCB)，聚苯并噁唑(polybenzoxazole，PBO)等聚合物。或者，介電層160可以包含無機介電材料如氧化矽，氮化矽，碳化矽，氮氧化矽等。
該方法延續到第1圖的區塊19，參考第11圖，半導體裝置140和第一塑模化合物150形成介電層160和重分佈層170在互連通孔130，一切割帶220黏著到介電層160上。接下來，第10圖中具有切割帶220的結構可以翻轉，而後將載體210自介電層110暫時解焊。
該方法延續到第1圖的區塊20。自從載體210自介電層110暫時解焊後，對於介電層110進行圖案化以形成開口111，以至少暴露部分重分佈層120，且得到的結果如第11圖所示。在一些實施例中，開口111可以使用光刻工藝或是透過雷射鑽孔形成於介電層110中。
該方法延續到第1圖的區塊21，其中開口111中形成焊料凸塊180和180a。參考第12圖，焊料凸塊180和180a形成在重分佈層120的暴露部分上。焊料凸塊180和180a可以透 過塗佈於露出的重分佈層120的錫膏印刷製程來形成。根據重分佈層120暴露的位置，可以使用模板將錫膏印刷在重分佈層120的頂部。應用回焊工藝，可以使得錫膏聚集在重分佈層120的頂部的焊料凸塊180和180a。在一些實施例中，焊料凸塊180與焊料凸塊180a的尺寸不同。例如，焊料凸塊180a比焊料凸塊180小。
該方法延續到第1圖的區塊22，其中第一塑模化合物150被切割通過。參考第12圖，在形成焊料凸塊180和180a之後，沿著切割線L1切割介電層110，第一塑模化合物150和介電層160進行分割處理，使得可以形成切割帶220上的多個芯片級封裝155。
該方法延續到第1圖的區塊23，其中介電層110附於載體210a。參考第13圖，在切割步驟之後，從切割帶220拾取芯片級封裝155，而後拾取的芯片級封裝155放置在載體210a的晶圓貼覆膜(die attach film，DAF)240上。因此，載體210上的晶圓貼覆膜240可以覆蓋焊料凸塊180，180a和介電層110以用於保護。換句話說，焊料凸塊180和180a嵌入在晶圓貼覆膜240中。第13圖所示拾取芯片級封裝155的數量是為了說明，且本揭露的各種實施例在這方面不受限制。在一些實施例中，載體210a可以與第2-10圖所示的載體210相同。在替代實施例中，載體210a不同於載體210，且本揭露的各種實施例在這方面不受限制。例如，載體210a可以是胚料玻璃載體，胚料陶瓷載體等。
該方法延續到第1圖的區塊24，其中第二塑模化合物190圍繞著第一塑模化合物150形成。參考第13圖，在芯片級封裝155被放置在的晶圓貼覆膜240後，第二塑模化合物190圍繞著芯片級封裝155成型。介電層110，介電層160和第一塑模化合物150都被第二塑模化合物190所包圍。介電層110的底表面實質上與第二塑模化合物190的底表面共平面，以及介電層160的頂表面實質上與第二塑模化合物190的頂表面共平面。第二塑模化合物190可以是聚合物、樹脂等。第二塑模化合物190與第一塑模化合物150可以由相同的材料或是不同的材料製成，且本揭露的各種實施例在這方面不受限制。在一些實施例中，第二塑模化合物190包含成型填料，可以做為成型化合物和底部填充物。因此，第二塑模化合物190被填充於兩個相鄰的芯片級封裝155之間的間隙，且可以接觸並圍繞芯片級封裝155。
在一些實施例中，成型為暴露成型，其中芯片級封裝155的頂表面透過第二塑模化合物190露出。此外，可以使用傳遞成型來進行成型。在一些實施例中，使用模具(未顯示)進行成型以覆蓋芯片級封裝155的頂表面，使得所得到的第二塑模化合物190不會覆蓋芯片級封裝155的頂表面。在傳遞成型的過程中，將模具的內部空間成真空，並將成型材料注入模具的內部空間以形成第二塑模化合物190。
由於為暴露成型，第二塑模化合物190的頂表面可以實質上與芯片級封裝155的頂表面同平面。在一些實施例中，第二塑模化合物190的頂表面實質上與芯片級封裝155的 頂表面共平面。在替代實施例中，第二塑模化合物190的頂表面比芯片級封裝155的頂表面稍微低一些，且本揭露的各種實施例在這方面不受限制。
第二塑模化合物190於介電層160，第一塑模化合物150，和介電層110周圍形成。此外，第二塑模化合物190的厚度H2與相應芯片級封裝155的第一塑模化合物150，介電層110和介電層160的總厚度H3實質上相同。
由於第二塑模化合物190成型芯片級封裝155，因此可以減小每一個芯片級封裝155的面積與相應的半導體裝置140的面積的比率。在芯片級封裝155的製造過程(如第2圖至第12圖)中，由於第一塑模化合物150的減少，可以預防芯片級封裝155的翹曲，因此提高了芯片級封裝155的製程良率和可靠產量。
該方法延續到第1圖的區塊25和26，參考第14圖，在第二塑模化合物190成型後，一切割帶220a黏附到第二塑模化合物190和介電層160上。接著，可以翻轉第13圖具有切割帶220a的結構，然後載體210a從晶圓貼覆膜240解焊，所得到的結構如第14圖所示。在一些實施例中，切割帶220a可以與第11圖和第12圖的切割帶220相同。在替代實施例中，切割帶220a不同於切割帶220，且本揭露的各種實施例在這方面不受限制。
該方法延續到第1圖的區塊27，其中晶圓貼覆膜240已經被去除。參考第15圖，在移除載體210a之後，將晶圓 貼覆膜240從芯片級封裝155清除，使得焊料凸塊180，180a和介電層110暴露。
該方法延續到區塊28，其中切割第二塑模化合物190至少產生一封裝結構100。參考第15圖，切割步驟為沿著切割線L2切割第15圖的結構。具有嵌入式芯片級封裝155的第二塑模化合物190被切割以形成多個獨立封裝，且每個封裝都具有半導體裝置140，第一塑模化合物150，和第二塑模化合物190。換句話說，在切割步驟後，從切割帶220a拾取至少一封裝結構100，獲得如第16和17圖的封裝結構100。在切割步驟中，封裝結構100的尺寸可以透過第二塑模化合物190的切割位置來決定，因此可以實現封裝結構100所需的尺寸。
第16圖為第17圖沿著第16-16線所截取的封裝結構100。由於第二塑模化合物190的厚度H2與第一塑模化合物150，介電層110和介電層160的總厚度H3實質上相同，第一塑模化合物150的厚度H1比第二塑模化合物190的厚度H2較小。此外，第一塑模化合物150與半導體裝置140的側壁145接觸。第二塑模化合物190與介電層110的側壁112，第一塑模化合物150的側壁152和介電層160的側壁162接觸。換句話說，介電層110和第二塑模化合物190具有介面，第一塑模化合物150和第二塑模化合物190具有介面，且介電層160和第二塑模化合物190具有介面。
第17圖為根據且本揭露的一些實施例的封裝結構100的俯視圖。半導體裝置140被第一塑模化合物150所包圍，且第一塑模化合物150被第二塑模化合物190所包圍。換 句話說，第一塑模化合物150位於半導體裝置140與第二塑模化合物190之間，因此第二塑模化合物190不含導電特徵134。由於在芯片級封裝155成型後形成第二塑模化合物190，第二塑模化合物190可以將芯片級封裝155擴展到所需的尺寸。
在前述的封裝結構中，利用兩種成型步驟來形成封裝結構。最終封裝結構的尺寸可以透過設置在第一塑模化合物的周圍的第二塑模化合物的不同區域來決定。換句話說，封裝來結構可以利用第二塑模化合物來實現多樣化的產品尺寸。此外，在第二塑模化合物中或其上沒有重分佈層和介電層。因此，可以降低製造封裝結構的成本。
根據一些實施例，封裝結構包括半導體裝置、第一塑模化合物、通孔、第一介電層、第一重分佈線，和第二塑模化合物。第一塑模化合物與半導體的側壁接觸。通孔位於第一塑模化合物，並電性連接到半導體裝置和通孔。第一介電層在半導體裝置上。第一重分佈線在第一介電層中並且電性連接到半導體裝置。第二塑模化合物與第一介電層的側壁接觸。
根據一些實施例，第一塑模化合物被第二塑模化合物所包圍。
根據一些實施例，第一塑模化合物與第二塑模化合物接觸。
根據一些實施例，第一介電層被第二塑模化合物所包圍。
根據一些實施例，第一塑模化合物的厚度小於第二塑模化合物的厚度。
根據一些實施例，封裝結構更包含第二介電層和第二重分佈線。半導體裝置設置在第一介電層第二介電層之間。第二重分佈線設置在第二介電層中，並電性連接半導體裝置。
根據一些實施例，第二塑模化合物與第二介電層的側壁接觸。
根據一些實施例，第二介電層的底表面與第二塑模化合物的底表面實質上共平面。
根據一些實施例，第一介電層的頂表面與第一塑模化合物的頂表面實質上共平面。
根據一些實施例，封裝結構包括半導體裝置、第一塑模化合物、通孔、第一介電層、第一重分佈線，和第二塑模化合物。第一塑模化合物與半導體的側壁接觸。通孔位於第一塑模化合物並且電性連接到半導體裝置。第一介電層在半導體裝置上。第一重分佈線在第一介電層中並且電性連接到半導體裝置和通孔。第二塑模化合物在第一塑模化合物的周圍，且第一塑模化合物和第二塑模化合物具有介面。
根據一些實施例，第二塑模化合物圍繞第一介電層。
根據一些實施例，第一介電層和第二塑模化合物間具有介面。
根據一些實施例，第二塑模化合物不具有導電特徵。
根據一些實施例，形成封裝結構的方法，包含在介電層上形成通孔，其中通孔與介電層中的重分佈線電性連接；在介電層上設置半導體裝置；在介電層上形成第一塑模化合物，其中半導體裝置和通孔嵌入第一塑模化合物；以及在第一塑模化合物周圍形成第二塑模化合物。
根據一些實施例，形成封裝結構的方法更包含切割至少通過第一塑模化合物。
根據一些實施例，第二塑模化合物是在切割步驟之後形成。
根據一些實施例，形成封裝結構的方法更包含將介電層圖案化以露出重分佈線，以及形成焊料凸塊電性連接到重分佈線。
根據一些實施例，第二塑模化合物是在形成焊料凸塊後形成。
根據一些實施例，形成封裝結構的方法更包含在形成第二塑模化合物之前，使用晶圓貼覆膜將介電層附著到載體上，其中焊料凸塊嵌入晶圓貼覆膜中。
根據一些實施例，形成封裝結構的方法更包含切割通過第二塑模化合物。
前面概述了數個實施例的特徵，使得本領域技術人員可以更好的理解本揭露的各個方面。本領域技術人員應該要理解，他們可以容易使用本揭露為基礎用於設計或修改用於執行其他程序或結構以完成相同的目的和/或實現本文所介紹實施例的相同的優點。本領域技術人員應該還要意識到，這樣 的等效架構不能脫離本揭露的精神和範圍，並且在不脫離本揭露的精神和範圍的情況下，他們可以進行各種變化、替換和改變。

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  1. 一種封裝結構，包含：一半導體裝置；一第一塑模化合物，與該半導體裝置的側壁接觸；一通孔，設置於該第一塑模化合物中，並電性連接該半導體裝置；一第一介電層，設置在該半導體裝置上；一第一重分佈線，設置在該第一介電層中，且電性連接該半導體裝置和該通孔；以及一第二塑模化合物，與該第一介電層的側壁接觸。
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