TW201838108A - 封裝結構 - Google Patents

封裝結構 Download PDF

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Publication number
TW201838108A
TW201838108A TW106130182A TW106130182A TW201838108A TW 201838108 A TW201838108 A TW 201838108A TW 106130182 A TW106130182 A TW 106130182A TW 106130182 A TW106130182 A TW 106130182A TW 201838108 A TW201838108 A TW 201838108A
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Taiwan
Prior art keywords
conductive
dielectric layer
layer
conductive bump
bump
Prior art date
Application number
TW106130182A
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English (en)
Inventor
林俊成
鄭禮輝
蔡柏豪
Original Assignee
台灣積體電路製造股份有限公司
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Publication of TW201838108A publication Critical patent/TW201838108A/zh

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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Abstract

一種封裝結構，此封裝結構包含一半導體元件、一第一重分佈線、一介電層、一第一導電凸塊與一第一密封結構。此介電層係位於此第一重分佈線上方且具有一第一開口於其中。此第一導電凸塊係部份地嵌入此第一開口且電性連接此第一重分佈線。此第一密封結構包圍此第一導電凸塊的一底部。此第一密封結構具有一曲面，此曲面從該第一導電凸塊的一底部的一外表面延伸至此介電層的一頂面。

Description

封裝結構
本揭露係關於半導體封裝。
半導體產業透過使最小特徵尺寸縮減以持續提升各種電子元件(例如電晶體、二極體、電阻及電容等)的積體密度，以在有限面積上結合更多元件。此些更小的電子元件亦需要比先前封裝使用較少面積的更小的封裝，用於半導體封裝的較小尺寸的類型包含四方封裝(quad flat pack；QFP)、插針網格陣列(Pin Grid Array，PGA)、球柵陣列封裝(ball grid array；BGA)、覆晶(flip chips；FC)、三維積體電路(three dimensional integrated circuits；3DICs)、晶圓級晶片尺寸封裝(wafer level packages；WLPs)、接合導線bond-on-trace；BOT)封裝及封裝層疊(package on package；PoP)結構。
根據本揭露之部份實施方式，一種封裝結構包含一半導體元件、一第一重分佈線、一介電層、一第一導電凸塊與一第一密封結構。此介電層係位於此第一重分佈線上 方且具有一第一開口於其中。此第一導電凸塊係部份地嵌入此第一開口且電性連接此第一重分佈線。此第一密封結構環繞此第一導電凸塊的一底部。此第一密封結構具有一曲面，此曲面從此第一導電凸塊的此底部的一外表面延伸至此介電層的一頂面。
100‧‧‧貫穿積體穿孔封裝
110‧‧‧緩衝層
120‧‧‧貫穿積體扇出通孔
123‧‧‧晶種層
125‧‧‧導電特徵
130‧‧‧第一半導體元件
131‧‧‧黏著層
132‧‧‧半導體基材
135‧‧‧成型材料
136‧‧‧導電柱
142‧‧‧介電層
144‧‧‧介電層
150‧‧‧重分佈線
160‧‧‧導電凸塊
160b‧‧‧底部
160t‧‧‧頂部
170‧‧‧密封結構
172‧‧‧外表面
174‧‧‧界面
180‧‧‧背側球墊
190‧‧‧第二半導體元件
191‧‧‧基材
192‧‧‧接觸墊
193‧‧‧貫穿基材通孔
194b‧‧‧半導體晶粒
194t‧‧‧半導體晶粒
195‧‧‧封裝膠
196‧‧‧打線
200‧‧‧底部填充
210‧‧‧單獨封裝結構
A‧‧‧黏著層
C‧‧‧載體
D‧‧‧密封材料液滴
DT‧‧‧切割膠帶
G‧‧‧間隙
O1‧‧‧開口
OP‧‧‧開口
P‧‧‧光阻
S‧‧‧位置
T1‧‧‧頂部
T2‧‧‧頂部
TK‧‧‧厚度
閱讀以下詳細敘述並搭配對應之圖式，可了解本揭露之多個樣態。需留意的是，圖式中的多個特徵並未依照該業界領域之標準作法繪製實際比例。事實上，所述之特徵的尺寸可以任意的增加或減少以利於討論的清晰性。
第1圖至第19圖繪示根據本揭露之部份實施方式來製造一封裝結構的方法。
以下將以圖式及詳細說明清楚說明本揭露之精神，任何所屬技術領域中具有通常知識者在瞭解本揭露之實施例後，當可由本揭露所教示之技術，加以改變及修飾，其並不脫離本揭露之精神與範圍。舉例而言，敘述「第一特徵形成於第二特徵上方或上」，於實施例中將包含第一特徵及第二特徵具有直接接觸；且也將包含第一特徵和第二特徵為非直接接觸，具有額外的特徵形成於第一特徵和第二特徵之間。此外，本揭露在多個範例中將重複使用元件標號以和/或文字。重複的目的在於簡化與釐清，而其本身並不會決定 多個實施例以和/或所討論的配置之間的關係。
此外，方位相對詞彙，如「在…之下」、「下面」、「下」、「上方」或「上」或類似詞彙，在本文中為用來便於描述繪示於圖式中的一個元件或特徵至另外的元件或特徵之關係。方位相對詞彙除了用來描述裝置在圖式中的方位外，其包含裝置於使用或操作下之不同的方位。當裝置被另外設置(旋轉90度或者其他面向的方位)，本文所用的方位相對詞彙同樣可以相應地進行解釋。
其他特徵及製程亦可被包含。舉例而言，測試結構可被包含以有助於三維封裝或三維積體電路元件的驗證測試。舉例而言，測試結構可包含形成於重分佈層中或於基材上的測試墊，以測試三維封裝或三維積體電路；探針及/或探針卡的使用；以及類似物。驗證測試不僅可執行於中間階段之結構，亦可執行於最終結構。此外，此處所揭露之結構及方法可與包含良率晶粒之中間驗證之測試方法一同使用，以提升產率及降低成本。
第1圖至第19圖為根據本揭露之部份實施方式繪示製造封裝結構的方法。參照第1圖，黏著層A係形成於載體C上。載體C可為玻璃載體、陶瓷載體或類似物。黏著層A可由黏著劑所形成，例如紫外光膠、光熱轉換(light-to-heat conversion；LTHC)膠或類似物，其他種類的黏著劑亦可做為使用。於部份實施方式中，黏著層A可由聚合物所形成，例如聚合樹脂。
參照第2圖，緩衝層110係形成於黏著層A上 方。緩衝層110係介電層且可為聚合物層，舉例而言，聚合物層可包含聚醯亞胺(polyimide)、聚苯并[口咢]唑(polybenzoxazole；PBO)、苯並環丁烯(benzocyclobutene；BCB)、ABF(ajinomoto buildup film)、阻焊(solder resist；SR)膜或類似物。緩衝層110實質上為平面層且具有實質上均等之厚度，緩衝層110之厚度為大於約2微米且可介於約2微米至約40微米。於部份實施方式中，緩衝層110之頂面與底面亦實質上係平面的。
晶種層123係形成於緩衝層110上，舉例而言，晶種層123可透過物理氣相沉積(physical vapor deposition；PVD)或金屬箔疊層(metal foil laminating)而形成。晶種層123可包含銅、銅合金、鋁、鈦、鈦合金、或以上之組合。於部份實施方式中，晶種層123包含鈦層與銅層，銅層係形成於鈦層上方。於其他實施方式中，晶種層123係銅層。於部份實施方式中，當無緩衝層110時，晶種層123係直接形成於黏著層A上。
參照第3圖，光阻P係施加於晶種層123上方並接著被圖案化。因此，開口O1係形成於光阻P中，晶種層123的一些部份係透過開口O1露出。
如第4圖所示，導電特徵125係透過電鍍或無電電鍍而形成於光阻P的開口O1中，導電特徵125係鍍覆於晶種層123的露出部份上。導電特徵125可包含銅、鋁、鎢、鎳、錫或以上之合金。導電特徵125的俯視形狀可為長方形、正方形、圓形或類似物。在導電特徵125的高度係高於 第一半導體元件130的厚度的本揭露之部份實施方式中，導電特徵125的高度係取決於接著鍍覆的第一半導體元件130(第7圖)的厚度。將導電特徵125鍍覆後，將光阻P移除，得到的結構如第5圖所示。將光阻P移除後，晶種層123的一些部份係露出。
參照第6圖，蝕刻步驟係執行以移除晶種層123的露出部份，其中蝕刻步驟可包含非等向性蝕刻。換句話說，被導電特徵125覆蓋的晶種層123的一些部份保持不被蝕刻。於本揭露中，導電特徵125與剩餘的晶種層123的下方部份的組合可稱為貫穿積體扇出(integrated fan-out；InFO)通孔(via)(TIVs)120，亦稱為通孔(through-via)。儘管晶種層123係顯示為與導電特徵125分隔的一層，當晶處層123由與所對應的下方的導電特徵125相似或實質上相同的材料所形成時，晶種層123可與導電特徵125合併，且兩者之間無可分辨的界面。於其他實施方式中，可分辨的界面係存在於晶種層123與下方的導電特徵125之間。
第7圖繪示將第一半導體元件130設置於緩衝層110上方。第一半導體元件130可透過黏著層131黏著於緩衝層110。於部份實施方式中，第一半導體元件130係未封裝的半導體元件，例如元件晶粒。舉例而言，第一半導體元件130可為包含邏輯電晶體的邏輯元件晶粒。於部份實施方式中，第一半導體元件130可被設計為用於行動式應用且可為中央處理器(central computing unit；CPU)晶粒、電源管理積體電路(power management IC；PMIC)晶粒、 收發器(transceiver；TRX)晶粒或類似物。各個第一半導體元件130包含接觸黏著層131的半導體基材132(例如矽基材)，其中半導體基材132的背面係接觸黏著層131。
於部份實施方式中，導電柱136(例如銅立柱)係形成為第一半導體元件130的頂部並與第一半導體元件130中的元件(例如電晶體)(未顯示)電性耦合。於部份實施方式中，介電層134係形成於所對應的第一半導體元件130的頂面上，導電柱136在介電層134中具有至少較低的部份。於部份實施方式中，導電柱136的頂面可與介電層134的頂面實質上齊平。或是，當介電層未形成，導電柱136從所對應的第一半導體元件130的頂介電層(未顯示)突出。
參照第8圖，成型材料135係成型於第一半導體元件130與貫穿積體通孔120上。成型材料135填充第一半導體元件130與貫穿積體通孔120之間的間隙且可直接接觸緩衝層110。此外，當導電柱136為突出的金屬柱(未顯示)，成型材料135係填充於複數導電柱136之間的間隙中。成型材料135的頂面係高於導電柱136與貫穿積體通孔120的頂端。
於部份實施方式中，成型材料135包含以聚合物為基礎的材料。用語「聚合物」可表示熱固化聚合物、熱塑化聚合物或任何以上之混合物。舉例而言，以聚合物為基礎之材料可包含塑膠材料、環氧樹脂(epoxy resin)、聚醯亞胺、聚對苯二甲酸乙二酯(polyethylene terephthalate；PET)、聚氯乙烯(polyvinyl chloride； PVC)、聚甲基丙烯酸甲酯(Polymethylmethacrylate；PMMA)、摻有包含纖維、黏土、陶瓷、無機粒子的填充物的聚合物成份或任何以上之組合。
接著，磨削步驟係執行以薄化成型材料135，直到導電柱136與貫穿積體通孔120係露出。得到的結構係顯示於第9圖，在第9圖中，成型材料135係接觸第一半導體元件130與貫穿積體通孔120的側壁。貫穿積體通孔120的頂端因磨削而實質上齊平(共平面)於導電柱136的頂端且實質上齊平(共平面)於成型材料135的頂面。由於磨削，導電殘留物(例如金屬粒子)可被產生並留在第9圖中的結構的頂面上。因此，在磨削後，清洗步驟可被執行(例如可透過濕式蝕刻)，以將導電殘餘物移除。
接著，參照第10圖，重分佈線150係形成於成型材料135上方，以連接導電柱136與貫穿積體通孔120，重分佈線150亦內連接導電柱136與貫穿積體通孔120。根據部份實施方式，介電層142及144係形成於第一半導體元件130、成型材料135與貫穿積體通孔120上方且具有重分佈線150形成於其中。於部份實施方式中，重分佈線150的一層的形成包含形成毯覆式晶種層(例如銅、鈦或以上之組合)；形成並圖案化遮罩層於毯覆式晶種層上方；執行鍍覆以形成重分佈線150；移除遮罩層；以及執行毛邊蝕刻，以移除未被重分佈線150覆蓋的毯覆式晶種層的複數部份。於部份實施方式中，在形成底介電層142與重分佈線150後，頂介電層144係形成於重分佈線150與底介電層142上方。 頂介電層144可由任何適合的方法所形成，像是旋轉塗佈或層疊以及固化步驟。頂介電層144係圖案化以形成複數開口OP，以露出重分佈線150的複數部份。開口OP係排列為複數行與複數列組成的陣列圖案，相當於接著形成的球柵陣列封裝。頂介電層144的圖案化可包含光微影技術。
於部份實施方式中，重分佈線150可為金屬或包含鋁、銅、鎢及/或以上金屬之合金。於本揭露中，包含緩衝層110、第一半導體元件130、貫穿積體通孔120、成型材料135、重分佈線150與介電層142及144的合併結構係稱為貫穿積體通孔封裝100，貫穿積體通孔封裝100可為複合物晶圓。
第10圖繪示兩層重分佈線150，取決於所對應的封裝的佈線設計，重分佈線150亦可為一層或多於兩層。於此些實施方式中，介電層142及144可包含聚合物，例如聚醯亞胺、苯並環丁烯、聚苯并[口咢]唑或類似物。此外，介電層142及144可包含非有機介電材料、例如氧化矽、氮化矽、碳化矽、氮氧化矽或類似物。
接著，參照第11圖，複數導電凸塊160係透過頂介電層144中的複數開口OP設置於複數重分佈線150上。換句話說，複數導電凸塊160係分別接觸複數重分佈線150，因此，導電凸塊160可電性連接重分佈線150。進一步地，複數導電凸塊160係分別部份地嵌入頂介電層144的複數開口OP。導電凸塊160可為包含共晶材料的球柵陣列封裝，例如焊錫，但本揭露不以此為限。於導電凸塊160係 焊錫球的部份實施方式中，導電凸塊160可由落球法所形成，例如直接落球製程。此外，焊錫球可由起初透過適合的方法(例如蒸鍍、電鍍、列印、焊錫轉移)形成一錫層，接著執行迴流，以將材料塑形成想要的凸塊形狀。一旦將導電凸塊160形成，可執行測試以確保結構係適合進一步的製程。
在部份實施方式中，導電凸塊160係接觸頂介電層144與重分佈線150。換句話說，凸塊下金屬(under bump metallization；UBM)結構係不存在於導電凸塊160之下，因此，形成凸塊下金屬結構的成本可被省去。因此，不具有凸塊下金屬結構有助於降低封裝結構的製造成本。然而，若導電凸塊160與頂介電層144之間不存在凸塊下金屬結構，則導電凸塊160的凸塊強度弱；重分佈線150由於應力緩衝能力弱而趨向裂開；以及頂介電層144從頂介電層144與重分佈線150之間的界面脫層。此外，頂介電層144的脫層導致導電凸塊160與頂介電層144之間或頂介電層144與重分佈線150之間產生間隙或空孔，使濕氣透過此些導電凸塊160與頂介電層144之間的間隙或空孔滲透，濕氣亦可透過此些頂介電層144與重分佈線150之間的間隙或空孔滲透。因此，本揭露之部份實施方式使用密封結構，以避免剝離(或脫層)與溼氣的滲透，亦阻擋應力傳遞至下方的重分佈線與介電質，如下所述。
第12圖繪示將密封結構170形成於頂介電層144上，第13圖係密封結構170之放大示意圖。如第12及13圖所示，密封結構170係形成於頂介電層144上，以密封導 電凸塊160與頂介電層144之間的間隙，像是第13圖中的間隙G。舉例而言，密封結構170的一部份填充導電凸塊160與頂介電層144之間的間隙G。換句話說，密封結構170的一部份係位於導電凸塊160與頂介電層144之間。於部份實施方式中，密封結構170可由點膠工具T來點膠，例如噴印工具。點膠工具T可點膠或噴射複數密封材料液滴D於各個導電凸塊160周圍，如第14圖所示。點膠工具T係定向的，以使密封材料液滴D直接朝向頂介電層144的頂面。密封材料液滴D可沿著導電凸塊160的邊緣與頂介電層144的頂面點膠。由於毛細管作用，導電凸塊160周圍的密封材料液滴D流入導電凸塊160與頂介電層144之間的間隙(例如第13圖所示的間隙G)，使導電凸塊160與頂介電層144之間的此些間隙可被密封材料液滴D密封。換句話說，導電凸塊160與頂介電層144之間的間隙可由毛細管作用而被密封材料液滴D填充，如第13圖所示。於部份實施方式中，密封材料液滴D可流入頂介電層114與重分佈線150之間的間隙。在密封材料液滴D係點膠後，固化製程係執行以硬化密封材料液滴D，以形成密封結構170，密封結構170延伸入導電凸塊160與頂介電層144之間的間隙G。
如第13圖所繪示，密封材料液滴D由於毛細管作用而爬到導電凸塊160的底部160b，因此，密封結構170係分別由環繞導電凸塊160的底部160b的固化的液滴D所形成。密封材料液滴D不爬上導電凸塊160的頂部160t上，因此，頂部160t不被密封結構170環繞。舉例而言，導電凸 塊160的頂部T1係位於高於密封結構170的頂部T2的位置。於部份實施方式中，密封結構170包含外表面172，外表面172從導電凸塊160的側壁160s(或稱外表面)延伸至頂介電層144的頂面。進一步而言，密封結構170的外表面172從導電凸塊160的側壁160s延伸至和導電凸塊160分隔的位置S，其中位置S係位於頂介電層144的頂面。換句話說，外表面172係接觸頂介電層144的頂面。此外，外表面172亦接觸導電凸塊160的側壁160s。於部份實施方式中，從密封結構170的頂端至重分佈線150的垂直距離係大於從頂介電層144的頂面至重分佈線150的垂直距離。於部份實施方式中，密封結構170的厚度TK介於約2微米至約80微米。
於部份實施方式中，由於毛細管作用，密封結構170的外表面172係彎曲的。換句話說，外表面172的斜率係高度的函數。於部份實施方式中，外表面172的彎曲從導電凸塊160的底部160b的側壁160s開始至位於頂介電層144的頂面的位置S。舉例而言，如第13圖所示，外表面172係凹面。換句話說，外表面172的斜率隨著密封結構170的厚度增加而增加。於部份實施方式中，外表面172的凹面曲率從導電凸塊160開始至頂介電層144。
於部份實施方式中，如第13圖所示，外表面172的曲率係不同於導電凸塊160的側壁160s的曲率。密封結構170與導電凸塊160的側壁160s形成界面174，因此，密封結構170與導電凸塊160的界面174係共形於導電凸塊160的側壁160s。因為密封結構170與導電凸塊160的界面174 係共形於導電凸塊160的側壁160s，界面174的曲率實質上相等於側壁160s的曲率。因此，外表面172與界面174具有不同的曲率。於部份實施方式中，外表面172與界面174共有一相同邊界。進一步而言，外表面172與界面174接合於導電凸塊160的側壁160s。
第13圖繪示兩相鄰導電凸塊160(例如一凸塊160在另一凸塊160旁邊)。密封結構170被安排於兩相鄰導電凸塊160之間。於部份實施方式中，密封材料液滴D係間隔地點膠，以使複數密封結構170彼此分隔。換句話說，位於複數相鄰導電凸塊160之間的複數密封結構170係彼此分隔。於部份實施方式中，因複數相鄰導電凸塊160之間的複數密封結構170係在相同點膠製程中點膠，密封結構170可具有相同材料，像是聚合物。舉例而言，聚合物可包含聚醯亞胺、聚苯并[口咢]唑、阻焊膜、鑄造成份、樹脂或其他適合的密封材料。於部份實施方式中，位於複數相鄰導電凸塊160之間的密封結構170不彼此分隔。
於部份實施方式中，如第14圖所繪示，一密封材料液滴D係點膠於另一密封材料液滴D上。換句話說，複數相鄰密封材料液滴D係部份地重疊於頂介電層144上方，因此，導電凸塊160周圍的密封材料液滴D係連接成圍繞導電凸塊160的環或環狀結構。這樣的設計有助於提升導電凸塊160與頂介電層144之間的間隙(例如第13圖所示的間隙G)的密封。換句話說，導電凸塊160周圍的複數密封結構170係彼此合併成為圍繞導電凸塊160的環或環狀結構，使 導電凸塊160與頂介電層144之間的間隙的密封可被提升。複數密封結構170的合併可透過控制一或多個點膠密封材料液滴D的參數來達成，例如複數密封材料液滴D的間距或類似物。
接著，貫穿積體穿孔封裝100係從載體C分離。貫穿積體穿孔封裝100中的黏著層A亦被清洗。由於黏著層A的移除，緩衝層110係露出，得到的結構係顯示於第15圖，參照第15圖，具有導電凸塊160的貫穿積體穿孔封裝100係進一步地黏著於切割膠帶DT(dicing tape)，其中導電凸塊160可接觸切割膠帶DT。於部份實施方式中，疊層膜(未顯示)係設置於露出的緩衝層110上方，其中疊層膜可包含阻焊膜、ABF、背側塗佈膠帶或類似物。於其他實施方式中，無疊層膜係設置於緩衝層110上方。
第16圖繪示緩衝層110的圖案化，以形成開口112並露出貫穿積體通孔120。於部份實施方式中，緩衝層110可由像是雷射鑽孔(laser drilling)法而被圖案化。於部份實施方式中，保護層(例如光熱轉換層)或水溶性保護膜(hogomax)層(未顯示)係先沉積於緩衝層110上方，一旦受到保護，雷射係指向想要移除的緩衝層110的此些部份，以露出底下的貫穿積體穿孔120。在雷射鑽孔後，後鑽孔清理製程係執行，以在雷射鑽孔期間移除殘餘物。於部份實施方式中，雷射鑽孔製程可創造鋸齒狀輪廓或粗糙輪廓，例如於開口112的側壁。換句話說，雷射鑽孔製程可使開口112的側壁露出，此些側壁的粗糙度大於未經雷射鑽孔製程的緩衝 層110的頂面的粗糙度。
於其他部份實施方式中，緩衝層110係由先施加光阻於緩衝層110再將光阻曝光於圖案化能源(例如圖案化的光源)而被圖案化，以引起化學反應，因而引起被圖案化光源曝光的光阻的此些部份中的物理變化。取決於想要的圖案，顯影劑接著被施加於被曝光的光阻，利用物理變化而選擇性移除任一光阻被曝光的部份或光阻未被曝光的部份，接著下方的緩衝層110的露出部份係由乾式蝕刻製程而被移除，但本揭露不以此為限。然而，任何其他適合的方法亦可用於圖案化緩衝層110。
第17圖繪示將背側球墊180設置於開口112中，以保護露出的貫穿積體通孔120。於部份實施方式中，背側球墊180可包含導電材料，例如錫膏(solder on paste；SOP)或氧焊錫保護物(oxygen solder protection；OSP)，但本揭露不以此為限。於部份實施方式中，背側球墊180可使用模板來施加，但本揭露不以此為限，接著背側球墊180被迴流，以形成凸塊形狀。
第18圖繪示將第二半導體元件190接合於背側球墊180。儘管在此實施方式中背側球墊180係焊錫球，但本揭露不以此為限。舉例而言，背側球墊180可為銅柱、銅栓、控制塌陷高度晶片連接(controlled collapse chip connectors；C4)或其他適合連接組件至下方的封裝或元件的連接器。進一步而言，在此描述中的用語「焊錫」不限於任何特定的種類與可包含或不包含鉛的焊錫。由鉛錫(鉛/ 錫)或鉛與額外的材料所形成的焊錫球亦可做為使用。此外，舉例而言，不含鉛的成份包含錫、銀銅(silver and coopper；SAC)可做為使用。背側球墊180可由共晶成份所形成。背側球墊180的形狀不限於「球」形，圓柱狀、柱狀、卵形、塔形、正方形、長方形及其他形狀亦可做為使用。
於部份實施方式中，第二半導體元件190可為封裝的半導體元件，舉例而言，第二半導體元件190可包含基材191、接觸墊192、半導體晶粒194b及194t及封裝膠195。於部份實施方式中，舉例而言，基材191可為包含內部內連接器(例如貫穿基材通孔193)的封裝基材，以將半導體晶粒194b及194t連接至背側球墊180。
此外，基材191可為中介層並做為連接半導體晶粒194b及194t至背側球墊180的中間基材。於部份實施方式中，舉例而言，基材191可為矽基材、已摻雜或未摻雜或絕緣體上覆矽(silicon-on-insulator；SOI)基材的主動層。然而，基材191亦可為玻璃基材、陶瓷基材、聚合物基材、或任何其他可以提供適合的保護及/或內連接功能的基材，此些或任何其他適合的材料亦可被使用於基材191。
底半導體晶粒194b可為像是邏輯晶粒、中央處理器晶粒、記憶體晶粒(例如動態隨機存取記憶體晶粒(Dynamic Random Access Memory die；DRAM die)、以上之組合或類似物的半導體元件。於部份實施方式中，底半導體晶粒194b包含積體電路元件，例如電晶體、電容、電感、電阻及類似物。
頂半導體晶粒194t可接合於底半導體晶粒194b。於部份實施方式中，頂半導體晶粒194t係與底半導體晶粒194b物理接合，例如使用黏著劑。於此實施方式中，頂半導體晶粒194t與底半導體晶粒194b可電性連接至基材191，舉例而言，可使用打線196，但本揭露不以此為限。此外，頂半導體晶粒194t可以物理方式或電性方式接合於底半島體晶粒194b。
接觸墊192可形成於基材191上，以形成電連接器於第二半導體元件190與背側球墊180之間。於部份實施方式中，接觸墊192可形成於基材191中的電性佈線(例如貫穿基材通孔193)上方並與電性佈線電性接觸。接觸墊192可包含鋁或其他材料，像是銅。接觸墊192可由沉積製程所形成，像是濺鍍，以形成一層材料(未顯示)，且此層材料的一些部份接著可透過適合的製程(例如光微影遮罩及蝕刻)而被移除，以形成接觸墊192。然而，任何其他適合的製程亦可用來形成接觸墊192。
封裝膠195可用來封裝或保護底半導體晶粒194b、頂半導體晶粒194t與基材191。於部份實施方式中，封裝膠195可為成型成份且可使用成型元件來設置。舉例而言，基材191、底半導體晶粒194b與頂半導體晶粒194t可設置於成型元件的腔體內，此腔體為密封的。封裝膠195於腔體被密封前被設置於腔體內，否則封裝膠195可透過注入口被注入腔體。於部份實施方式中，封裝膠195的材料可為成型成份樹脂，例如聚醯亞胺、聚苯硫醚(polyphenylene sulfide；PPS)、聚醚醚酮(polyetheretherketone；PEEK)、聚醚碸(polyethersulfone；PES)及耐熱晶體樹脂、環氧樹脂、以上之組合或類似物。
當封裝膠195被設置於腔體內而使封裝膠195封裝基材191、底半導體晶粒194b及頂半導體晶粒194t周圍的區域，封裝膠195接著被固化，使封裝膠195硬化達到理想的保護。固化製程係至少取決於用於封裝膠195的材料，於部份實施方式中，封裝膠195係成型材料，固化可透過像是加熱封裝膠195至約100℃至約130℃之間(例如約125℃)持續約60秒至約3000秒(例如約600秒)的製程來進行。此外，起始劑及/或催化劑可被包含於封裝膠195中，以更好控制固化製程。然而，本屬領域中具有通常知識者應可理解，上述固化製程僅為實施示例，並非用來限制目前的實施方式。其他固化製程，例如輻射或使封裝膠195被固化於常溫中亦有可能做為使用。任何適合的固化製程亦可作為使用並被包含於此處所討論的實施方式之範疇中。
底部填充物200可至少地形成於第二半導體元件190與背側球墊180之間。舉例而言，底部填充物200可做為一液體並由毛細底部填充法(capillary underfill；CUF)被點膠。樹脂或環氧液體係往第二半導體元件190下方流動並填充第二半導體元件190與背側球墊180之間的空間。底部填充200可過度填充複數背側球墊180之間的空間，並係存在於第二半導體元件190的側壁上，如第18圖所示。室溫固化、紫外光固化、或熱固化可用來固化底部填充 物200。底部填充物可提供機械強度與將應力釋放至第二半導體元件190。
接著，如第19圖所示，去框製程可被執行以鉅開貫穿積體通孔封裝100、第二半導體元件190與底部填充200的組合為複數個單獨封裝結構210。切割膠帶DT亦可被移除。
本揭露的實施方式可至少具有以下優點。凸塊下金屬結構係不存在於導電凸塊與介電層之間，因而省下形成凸塊下金屬結構的成本。此外，即使封裝結構因不具有凸塊下金屬結構而易有剝離的問題，環繞導電凸塊的底部的密封結構可避免剝離的問題，因此，推球表現與防水能力可被提升。此外，因密封結構係由點膠密封材料液滴至導電凸塊周圍的所選的位置所形成，可避免點膠製程的殘餘物位在導電凸塊的不想要的位置(例如導電凸塊的頂部)上。
以上概述數個實施方式或實施例的特徵，使所屬領域中具有通常知識者可以從各個方面更加瞭解本揭露。本技術領域中具有通常知識者應可理解，且可輕易地以本揭露為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到在此介紹的實施方式或實施例相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未悖離本揭露的揭露精神與範圍。在不悖離本揭露的精神與範圍之前提下，可對本揭露進行各種改變、置換或修改。

Claims (1)

  1. 一種封裝結構，包含：一半導體元件；一第一重分佈線，電性連接該半導體元件；一介電層，位於該第一重分佈線上方且具有一第一開口於其中；一第一導電凸塊，部份地嵌入該第一開口且與該第一重分佈線電性連接；以及一第一密封結構，環繞該第一導電凸塊的一底部，該第一密封結構具有一曲面，該曲面從該第一導電凸塊的該底部的一外表面延伸至該介電層的一頂面。
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