FR3104315B1 - Procédé de fabrication de puces électroniques - Google Patents

Procédé de fabrication de puces électroniques Download PDF

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Publication number
FR3104315B1
FR3104315B1 FR1913750A FR1913750A FR3104315B1 FR 3104315 B1 FR3104315 B1 FR 3104315B1 FR 1913750 A FR1913750 A FR 1913750A FR 1913750 A FR1913750 A FR 1913750A FR 3104315 B1 FR3104315 B1 FR 3104315B1
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France
Prior art keywords
resin
pillars
upper face
sacrificial
manufacturing process
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FR1913750A
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FR3104315A1 (fr
Inventor
Ludovic Fallourd
Christophe Serre
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STMicroelectronics Tours SAS
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STMicroelectronics Tours SAS
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Priority to FR1913750A priority Critical patent/FR3104315B1/fr
Priority to EP20209109.6A priority patent/EP3832704A1/fr
Priority to US17/111,198 priority patent/US11393786B2/en
Priority to CN202011409752.5A priority patent/CN112908934A/zh
Publication of FR3104315A1 publication Critical patent/FR3104315A1/fr
Application granted granted Critical
Publication of FR3104315B1 publication Critical patent/FR3104315B1/fr
Priority to US17/811,560 priority patent/US20220344303A1/en
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    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/06155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Procédé de fabrication de puces électroniques La présente description concerne un procédé de fabrication de puces électroniques, comprenant les étapes successives suivantes : former, du côté de la face supérieure d'un substrat semiconducteur (11), dans et sur lequel ont été préalablement formés une pluralité de circuits intégrés, au moins un pilier (35) de résine sacrificielle par circuit intégré, en contact avec la face supérieure du circuit intégré ; déposer, du côté de la face supérieure du substrat (11), une résine de protection (23), s'étendant entre les piliers (35) de résine sacrificielle ; retirer les piliers (35) de résine sacrificielle sélectivement par rapport à la résine de protection (23), de façon à former dans la résine de protection (23) des cavités de forme complémentaire à celle des piliers (35) de résine sacrificielle ; et remplir les cavités par du métal pour former des piliers métalliques de connexion en contact avec la face supérieure des circuits intégrés. Figure pour l'abrégé : Fig. 18
FR1913750A 2019-12-04 2019-12-04 Procédé de fabrication de puces électroniques Active FR3104315B1 (fr)

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FR1913750A FR3104315B1 (fr) 2019-12-04 2019-12-04 Procédé de fabrication de puces électroniques
EP20209109.6A EP3832704A1 (fr) 2019-12-04 2020-11-23 Procédé de fabrication de puces électroniques
US17/111,198 US11393786B2 (en) 2019-12-04 2020-12-03 Method for manufacturing electronic chips
CN202011409752.5A CN112908934A (zh) 2019-12-04 2020-12-04 用于制造电子芯片的方法
US17/811,560 US20220344303A1 (en) 2019-12-04 2022-07-08 Method for manufacturing electronic chips

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FR1913750A FR3104315B1 (fr) 2019-12-04 2019-12-04 Procédé de fabrication de puces électroniques
FR1913750 2019-12-04

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FR3104317A1 (fr) 2019-12-04 2021-06-11 Stmicroelectronics (Tours) Sas Procédé de fabrication de puces électroniques
US11729915B1 (en) * 2022-03-22 2023-08-15 Tactotek Oy Method for manufacturing a number of electrical nodes, electrical node module, electrical node, and multilayer structure

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US20220344303A1 (en) 2022-10-27
FR3104315A1 (fr) 2021-06-11
US20210175204A1 (en) 2021-06-10
EP3832704A1 (fr) 2021-06-09
US11393786B2 (en) 2022-07-19

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