FR3068507B1 - Realisation de regions semiconductrices dans une puce electronique - Google Patents

Realisation de regions semiconductrices dans une puce electronique Download PDF

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Publication number
FR3068507B1
FR3068507B1 FR1756181A FR1756181A FR3068507B1 FR 3068507 B1 FR3068507 B1 FR 3068507B1 FR 1756181 A FR1756181 A FR 1756181A FR 1756181 A FR1756181 A FR 1756181A FR 3068507 B1 FR3068507 B1 FR 3068507B1
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layer
region
semiconductor regions
realization
silicon nitride
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Expired - Fee Related
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FR1756181A
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FR3068507A1 (fr
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Franck Julien
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STMicroelectronics Rousset SAS
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STMicroelectronics Rousset SAS
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Priority to FR1756181A priority Critical patent/FR3068507B1/fr
Priority to US15/992,481 priority patent/US10672644B2/en
Priority to CN201821012891.2U priority patent/CN208548342U/zh
Priority to CN201810691907.5A priority patent/CN109216281B/zh
Publication of FR3068507A1 publication Critical patent/FR3068507A1/fr
Priority to US16/860,392 priority patent/US20200258773A1/en
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Publication of FR3068507B1 publication Critical patent/FR3068507B1/fr
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un procédé de fabrication de première (16P) et deuxième (16N) régions semiconductrices séparées par des tranchées isolantes (22), comprenant successivement : recouvrir un substrat semiconducteur (10) d'une première couche de nitrure de silicium et la première région d'une couche de protection ; recouvrir la structure d'une deuxième couche de nitrure de silicium ; graver puis remplir les tranchées d'un oxyde de remplissage jusqu'à un niveau situé au-dessus de la couche de protection ; retirer sélectivement la deuxième couche de nitrure et la partie de la première couche de nitrure située sur la deuxième région ; retirer la couche de protection, et graver sélectivement l'oxyde de remplissage par gravure humide, d'où il résulte des cuvettes (28) autour de la deuxième région (16N) ; et retirer sélectivement la partie de la première couche de nitrure de silicium située sur la première région (16P).
FR1756181A 2017-06-30 2017-06-30 Realisation de regions semiconductrices dans une puce electronique Expired - Fee Related FR3068507B1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FR1756181A FR3068507B1 (fr) 2017-06-30 2017-06-30 Realisation de regions semiconductrices dans une puce electronique
US15/992,481 US10672644B2 (en) 2017-06-30 2018-05-30 Production of semiconductor regions in an electronic chip
CN201821012891.2U CN208548342U (zh) 2017-06-30 2018-06-28 半导体器件
CN201810691907.5A CN109216281B (zh) 2017-06-30 2018-06-28 在电子芯片中的半导体区域的制作
US16/860,392 US20200258773A1 (en) 2017-06-30 2020-04-28 Production of semiconductor regions in an electronic chip

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US11569368B2 (en) * 2020-06-11 2023-01-31 Atomera Incorporated Method for making semiconductor device including a superlattice and providing reduced gate leakage
US11469302B2 (en) 2020-06-11 2022-10-11 Atomera Incorporated Semiconductor device including a superlattice and providing reduced gate leakage

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US20040065937A1 (en) * 2002-10-07 2004-04-08 Chia-Shun Hsiao Floating gate memory structures and fabrication methods
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US7282402B2 (en) * 2005-03-30 2007-10-16 Freescale Semiconductor, Inc. Method of making a dual strained channel semiconductor device
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US8563394B2 (en) * 2011-04-11 2013-10-22 International Business Machines Corporation Integrated circuit structure having substantially planar N-P step height and methods of forming
US8778772B2 (en) * 2012-01-11 2014-07-15 Globalfoundries Inc. Method of forming transistor with increased gate width
US8871586B2 (en) * 2012-10-18 2014-10-28 Globalfoundries Inc. Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor material
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US10672644B2 (en) 2020-06-02

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