CN208548342U - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN208548342U
CN208548342U CN201821012891.2U CN201821012891U CN208548342U CN 208548342 U CN208548342 U CN 208548342U CN 201821012891 U CN201821012891 U CN 201821012891U CN 208548342 U CN208548342 U CN 208548342U
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region
grid
groove
insulating materials
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F·朱利恩
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STMicroelectronics Rousset SAS
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Abstract

本申请涉及半导体器件。一种半导体器件包括：半导体衬底，所述半导体衬底具有由沟槽围绕的第一区域和第二区域；和对所述沟槽进行填充的绝缘材料；其中填充所述沟槽的所述绝缘材料在与所述第一区域的边缘相邻的位置处被填充到所述边缘之上的水平；和其中填充所述沟槽的所述绝缘材料在与所述第二区域的边缘相邻的位置处被填充到所述边缘之下的水平。由此提供性能改进的半导体器件。

Description

半导体器件
技术领域
本专利申请涉及半导体器件。
背景技术
在包括场效应晶体管的电子芯片中会出现各种问题。
具体而言，在这样的晶体管中的一个问题是：通常，晶体管越小，泄漏电流的相对值越高。这导致高能量消耗。
另一个问题是，被设计为是相同的晶体管实际上通常展现出不同的电气特性，特别是不同的阈值电压。当工作温度降低时，这些电气特性之间的差异通常趋向于变得更差。这在实际获得所设想的电气特性方面导致各种困难。这些困难尤其出现在芯片被提供用于例如在测量设备中的模拟操作和/或用于例如在负的环境温度下的冷操作的情况中。这通常会导致某些芯片在制造后的检查期间被抛弃。
此外，电子芯片可以包括由控制栅极覆盖的浮置栅极晶体管类型的存储器点。除了上述关于晶体管的问题之外，由于需要施加相对高的编程电压的事实，这样的存储器点展现出晶体管的栅极绝缘体的劣化的问题。
用于解决上述各种问题的各种已知方法，如果期望同时针对不同类型(N沟道和P沟道)的晶体管和/或存储器点实现上述问题的解决，则需要大量的制造步骤。
实用新型内容
本专利申请旨在提供改进的半导体器件，以克服上述问题。
本申请的一个方面涉及一种半导体器件。该半导体器件包括：半导体衬底，所述半导体衬底具有由沟槽围绕的第一区域和第二区域；和对所述沟槽进行填充的绝缘材料；其中填充所述沟槽的所述绝缘材料在与所述第一区域的边缘相邻的位置处被填充到所述边缘之上的水平；和其中填充所述沟槽的所述绝缘材料在与所述第二区域的边缘相邻的位置处被填充到所述边缘之下的水平。
在一个实施例中，该半导体器件还包括：覆盖在所述第一区域上方的第一栅极电介质层；覆盖在所述第二区域上方的第二栅极电介质层；第一栅极区域，所述第一栅极区域覆盖在所述第一区域上方并通过所述第一栅极电介质而与所述第一区域绝缘，所述第一栅极区域通过所述绝缘材料而与所述第一区域的边缘隔开；和第二栅极区域，所述第二栅极区域覆盖在所述第二区域上方并且与所述第二区域绝缘，所述第二栅极区域包括低于所述第二区域的上表面的水平而延伸的部分。
在一个实施例中，所述第一区域是p掺杂区域并且所述第一栅极区域是n沟道晶体管的栅极，并且其中所述第二区域是n掺杂区域并且所述第二栅极区域是p沟道晶体管的栅极。
在一个实施例中，所述半导体衬底是SOI结构的上半导体层。
本申请的另一方面涉及一种半导体器件。该半导体器件包括：半导体衬底，所述半导体衬底具有第一区域和通过沟槽与所述第一区域隔开的第二区域；在所述沟槽内的绝缘材料；其中所述第二区域周围的所述绝缘材料的表面具有凹坑形式的形状；和其中所述第一区域周围的所述绝缘材料的表面具有与所述第二区域周围的所述形状不同的形状。
在一个实施例中，所述第二区域周围的所述绝缘材料的表面低于所述第二区域的上表面；以及所述第一区域周围的所述绝缘材料的表面高于所述第二区域的上表面。
在一个实施例中，所述第一区域周围的所述绝缘材料不覆盖在所述第一区域上方。
一个实施例提供了一种包括通过填充有绝缘体的沟槽分离的第一半导体区域和第二半导体区域的器件。所述绝缘体的表面在所述第二区域周围具有凹坑形式的形状，并且在所述第一区域周围具有与在所述第二区域周围的所述形状不同的形状。
一个实施例提供了一种电子芯片，所述电子芯片包括上述器件、位于所述第一区域中和所述第一区域上的N沟道晶体管以及位于所述第二区域中和所述第二区域上的P沟道晶体管。
根据本申请的方案，可以提供性能改进的半导体器件。
附图说明
这些特征和优点以及其他优点将在以下对特定实施例的描述中被详细地呈现，以下对特定实施例的描述是在不受限制的情况下并且关于附图而提供的，在附图中：
图1A至图1E是图示了用于制造P沟道晶体管的方法的步骤的局部和示意性截面图；
图1F是图1E的结构的俯视示意图；
图2A至图2H是图示了用于制造N沟道晶体管和P沟道晶体管的方法的实施例的步骤的局部和示意性截面图；和
图2I是图2H的结构的俯视示意图。
具体实施方式
各个附图未按比例绘制，并且此外在各个附图中，相同的元件已由相同的参考标记引用。为了清楚起见，仅示出并详细描述了对所描述的实施例的理解有用的那些元件。具体而言，诸如间隔件之类的晶体管的各种元件未被示出。
在下面的描述中，当参考诸如“左”、“右”、“之上”、“上”、“下”等的位置限定符或参考诸如术语“水平”或“垂直”等的方位限定符时，参考所考虑的附图中所涉及的元件的定向，可以理解，在实践中，所描述的器件可以被不同地定向。
图1A至图1E是图示了用于制造P沟道晶体管的方法的步骤的局部和示意性截面图。
在图1A的步骤中，半导体衬底10包括例如n型掺杂阱12N。在阱12n的上部，形成了N型掺杂区域16N，并且其掺杂水平已根据晶体管的期望电气特性来选择。作为变型，阱12N和区域16N将在该方法的后续步骤中被掺杂。衬底用精细氧化硅层14覆盖，其厚度通常在2nm和20nm之间。然后在结构上沉积氮化硅层20，然后蚀刻穿过氮化硅的沟槽22(在图中沟槽只有一半可见)。沟槽穿透到衬底并界定区域16n的部分。
在图1B的步骤中，沟槽填充有绝缘体，例如氧化硅，然后执行平坦化直到氮化硅20的上层。
在图1C的步骤中，相对于氮化硅20选择性地蚀刻沟槽22的绝缘体，例如到位于区域16N之上的水平。
在图1D的步骤中，通过相对于沟槽22的绝缘体选择性蚀刻来去除氮化硅。然后清洁该结构，以消除仍存在于该区域16N上的层14的氧化物。这种清洁例如是在基于氢氟酸的溶液中进行。该清洁导致在区域16N周围的沟槽的绝缘体的表面上形成环形凹坑28。
在图1E的步骤中，在区域16N中和区域16N上形成P沟道MOS晶体管。具体而言，形成栅极绝缘层30和栅极32。
图1F是图1E的结构的俯视图。绝缘层30未被示出。从上面看，栅极32在区域16N的宽度上延伸。漏极和源极区域34已经形成在栅极的每一侧上。
上文的方法(特别是在图1C的步骤中对沟槽22的绝缘体的蚀刻以及在图1D的步骤中的清洁)的参数已被调整，以优化晶体管的电气特性，例如以最小化其泄漏电流。例如，这种调整是通过试验来执行的。事实上，由于各种边缘效应，诸如阈值电压和泄漏电流之类的电气特性在晶体管的边缘处和中心处是不同的。调整该方法的参数使得可以获得减少这些边缘效应的凹坑形状。
上文已经描述了使得可以获得最佳电气特性的P沟道晶体管的方法。但是，该方法不适用于获得最佳电气特性的N沟道晶体管。事实上，在N沟道晶体管和P沟道晶体管中的边缘效应是不同的。具体地说，当用P型区域16P代替N型区域16N时，掺杂剂原子倾向于在该方法中提供的各种退火过程中在沟槽的绝缘体中迁移，特别是当处理硼原子和填充有氧化硅的沟槽时。由此得出，区域16P的掺杂水平在晶体管的边缘处比在晶体管的中心处低。因此，在P沟道晶体管中获得的凹坑形状不是能够使得可以将N沟道晶体管的边缘效应最小化的形状。
图2A至图2H是图示了用于制造在这些图的左侧的N沟道晶体管和在右侧的P沟道晶体管的方法的实施例的步骤的局部和示意性截面图。该方法使得可以优化P沟道晶体管和N沟道晶体管的电气特性。
在图2A的步骤中，已经提供了衬底10。举例而言，衬底10例如在这里是硅的体半导体衬底。所示出的衬底部分的左侧部分是P型掺杂阱12P。所示出的衬底部分的右侧部分是N型掺杂阱12N。作为变型，衬底可以是在支撑件上覆盖了绝缘层的半导体层，也就是说SOI(“绝缘体上硅”)结构的上半导体层。
优选地，在左侧上的P型掺杂层16P’以及在右侧上的N型掺杂层16N’注入到衬底中。层16P’和层16N’的掺杂水平例如大于1017原子/cm3。在其中衬底是覆盖SOI结构的绝缘层的单晶硅薄层的变型中，层16P’和16N’可以遍及薄单晶硅层的整个厚度延伸。
作为变型，阱12P、阱12N、层16P’和/或层16N’可以在该方法的后续步骤中被掺杂，而不是从图2A的步骤开始被掺杂。
优选地，衬底用厚度例如在2nm和20nm之间的氧化硅层14覆盖。
此后，形成覆盖该结构的氮化硅层20。层20的厚度例如在30nm和100nm之间。
此后，仅在层16P’上形成可以相对于氮化硅被选择性蚀刻的材料的层40，例如氧化硅。层40优选地具有2nm至20nm之间的厚度。随后层40的功能将是保护氮化硅层20。
在图2B的步骤中，该结构用氮化硅层42覆盖。层42的厚度例如在30nm和100nm之间。由此得出，氮化硅层20和42在区域16N’侧上彼此直接相互叠置，并且在区域16P’侧上由层40分离。
在图2C的步骤中，沟槽22被蚀刻，在左侧上一直穿过两个氮化硅层20和42以及区域16P’，并且在右侧上穿过层20、40和42以及区域16N’。沟槽22界定层16P’中的半导体区域16P和层16N’中的半导体区域16N。沟槽22围绕区域16P和16N。
在图2D的步骤中，沟槽22填充有绝缘体，例如氧化硅。举例来说，整个结构被该绝缘体覆盖到位于氮化硅层42之上的水平，并且此后实行化学机械抛光。该抛光去除了位于覆盖区域16N的氮化硅的上层之上或位于氮化硅层42中的水平之上的结构部分。抛光之后，层42的氮化硅与沟槽的绝缘体的表面平齐，并且层42在区域16P侧上具有例如30nm至100nm之间的厚度。
在图2E的步骤中，将沟槽22的绝缘体选择性地蚀刻到位于保护层40之上的水平，例如通过氢氟酸溶液或基于氢氟酸的溶液。举例来说，蚀刻之后沟槽的绝缘体的表面位于保护层40的上表面之上2nm至15nm之间。
在图2F的步骤中，例如通过磷酸溶液或基于磷酸的溶液来执行氮化硅的选择性蚀刻。在区域16N侧上，去除两个层20和42的氮化硅。在区域16P侧上，去除层42的氮化硅，但不去除层20的氮化硅，因为其被层40保护。
此后例如通过氢氟酸溶液或基于氢氟酸的溶液，蚀刻沟槽的绝缘体并且去除保护层40。继续蚀刻直至沟槽的绝缘体的水平(取决于晶体管的期望特性)例如在区域16N和16P的低至20nm到高至30nm之间。在该步骤中，在区域16N侧上去除可能的层14。该蚀刻在区域16N周围的沟槽的绝缘体的表面上形成环形凹坑28。由于在区域16P之上的层20的氮化硅的存在，所以蚀刻没有伴随着区域16P周围的凹坑形成。
在图2G的步骤中，例如通过基于磷酸的溶液在区域16P上选择性地去除层20的氮化硅。此后例如通过氢氟酸溶液或基于氢氟酸的溶液进行清洁。因此在区域16P侧上去除可能的层14。该步骤进一步挖出区域16N周围的凹坑28。围绕区域16P，沟槽22的绝缘体的表面具有与凹坑28的形状不同的形状。作为示例，从区域16P的边缘开始，表面经由斜面50而与沟槽的绝缘体的上层相遇。
在图2H的步骤中，制作分别在区域16P和16N中和区域16P和16N上的N沟道晶体管和P沟道晶体管。具体而言，形成栅极绝缘层30和栅极32。作为示例，栅极绝缘体30通过热氧化和/或通过沉积形成。栅极绝缘体可以包括具有高介电常数的材料，例如氧化铪。作为示例，栅极绝缘体以顺应性方式沉积，并且因此在区域16P侧上位于斜面50(与区域16P的边缘大致垂直)上的部分52中，垂直地取得的栅极绝缘体的厚度大于水平部分中的栅极绝缘体(即位于区域16P的中心部分之上的中心部分)的厚度。
图2I是图2H的结构的俯视示意图，其中未示出栅极绝缘体。栅极32跨过漏极和源极区域34之间的区域16P和16N延伸。在并排形成的晶体管的情况下，栅极可以是两个晶体管共用的。作为示例，已经在区域16P和16N中的每一个区域中和每一个区域上示出了单个晶体管，但是可以例如通过形成若干平行的栅极来在区域16P和16N中的每一个区域上形成若干晶体管。
如前所指示的，当晶体管的沟道区域是P型区域16P时，与沟槽22接触的区域16P的外围部分的掺杂水平可以低于区域16P的中心处的掺杂水平——特别是当掺杂剂原子是硼并且当沟槽的绝缘体是氧化硅时。这些更轻度掺杂的外围区域由图2H中的附图标记54来指示。这导致晶体管在这些外围区域中的阈值电压低于在具有均匀掺杂的中心区域中的阈值电压。这部分地或全部地由以下事实补偿：由于当栅极绝缘体的厚度增加时阈值电压增加，所以栅极绝缘体30在越过区域54的区域52中比在中央区域中更厚。而且，在被设计为相同的晶体管中，区域54的性质通常不相同，并且这导致各种晶体管的外围区域的阈值电压之间的差异。区域52使得可以部分地补偿这些差异。
该方法的参数，特别是层20、40和42的厚度以及可能的层14的厚度以及蚀刻图2E、图2F的沟槽的绝缘体和图2G的清洁的步骤，可以被定制，以便同时获得针对P沟道晶体管和针对N沟道晶体管的最佳电气特性，和/或获得被设计为相同的晶体管之间的特别减小的差异。可选地，在图2F的步骤中，在去除未被层40保护的氮化硅之后并且在蚀刻层40和沟槽的绝缘体之前，可以进一步进行热氧化(未示出)，使其能够以仅在区域16N侧上获得层14，或者在区域16N上获得比在区域16P上更厚的层14。然后将该热氧化与该方法的其他参数一起进行定制，以便优化晶体管的电气特性和/或减小被设计为相同的晶体管之间的差异。
根据一个优点，以简单的方式并且以特别减少的步骤数目同时获得优化的N沟道晶体管和P沟道晶体管。此外，在提供区域52的情况下，保留了图1A至图1F的方法的可靠性的优点，这与区域52被自动对齐的事实相关。
根据另一个优点，同时获得即使对于小型晶体管也展现出特别低的泄漏电流的N沟道晶体管和P沟道晶体管。这导致特别低的能量消耗——特别是对于包括这种晶体管的芯片。
根据另一个优点，当除了P沟道晶体管之外使用该方法还制作被设计为相同的若干个N沟道晶体管时，获得其电气特性是准相同(包括在冷操作下)的N沟道晶体管。因此，该方法在旨在使用在测量设备中的晶体管的制作方面展现出特别的关注。此外，这特别是导致高制造效率。
已经描述了特定实施例。对于本领域技术人员而言，各种变型和修改将是显而易见的。具体而言，该方法可以适用于同时制作例如通过其栅极绝缘体厚度和/或通过其栅极绝缘体材料而不同的晶体管。为此目的，在图2H的步骤中形成的栅极绝缘体层30可以具有在各个晶体管的位置处不同的厚度和/或由在各个晶体管的位置处不同的材料制成。因此可以获得根据它们的阈值电压和/或它们的使用电压而不同的晶体管。此外，尽管已经描述了P沟道晶体管和N沟道晶体管的制作，但是晶体管继而可以具有相同的沟道类型。
而且，尽管上文描述的实施例涉及晶体管的制造，但是所描述的方法可适用于其他组件的制造，例如用于存储器点的制造。因此，在图2H的步骤中，晶体管的栅极用未示出的绝缘层覆盖，该绝缘层包括例如在两个氧化硅层之间的氮化硅层，并且栅极(未示出)形成在该绝缘层上。该栅极由此构成用于存储器点的控制栅极，栅极32构成存储器点的浮置栅极。作为变型，还可以同时形成晶体管和另一个组件，例如存储器点。这两个组件可以具有相同的沟道类型或不同的沟道类型。

Claims (7)

1.一种半导体器件，其特征在于，包括：
半导体衬底，所述半导体衬底具有由沟槽围绕的第一区域和第二区域；和
对所述沟槽进行填充的绝缘材料；
其中填充所述沟槽的所述绝缘材料在与所述第一区域的边缘相邻的位置处被填充到所述边缘之上的水平；和
其中填充所述沟槽的所述绝缘材料在与所述第二区域的边缘相邻的位置处被填充到所述边缘之下的水平。
2.根据权利要求1所述的器件，其特征在于，还包括：
覆盖在所述第一区域上方的第一栅极电介质层；
覆盖在所述第二区域上方的第二栅极电介质层；
第一栅极区域，所述第一栅极区域覆盖在所述第一区域上方并通过所述第一栅极电介质而与所述第一区域绝缘，所述第一栅极区域通过所述绝缘材料而与所述第一区域的边缘隔开；和
第二栅极区域，所述第二栅极区域覆盖在所述第二区域上方并且与所述第二区域绝缘，所述第二栅极区域包括低于所述第二区域的上表面的水平而延伸的部分。
3.根据权利要求2所述的器件，其特征在于，所述第一区域是p掺杂区域并且所述第一栅极区域是n沟道晶体管的栅极，并且其中所述第二区域是n掺杂区域并且所述第二栅极区域是p沟道晶体管的栅极。
4.根据权利要求1所述的器件，其特征在于，所述半导体衬底是SOI结构的上半导体层。
5.一种半导体器件，其特征在于，包括：
半导体衬底，所述半导体衬底具有第一区域和通过沟槽与所述第一区域隔开的第二区域；
在所述沟槽内的绝缘材料；
其中所述第二区域周围的所述绝缘材料的表面具有凹坑形式的形状；和
其中所述第一区域周围的所述绝缘材料的表面具有与所述第二区域周围的所述形状不同的形状。
6.根据权利要求5所述的器件，其特征在于，所述第二区域周围的所述绝缘材料的表面低于所述第二区域的上表面；和
其中所述第一区域周围的所述绝缘材料的表面高于所述第二区域的上表面。
7.根据权利要求6所述的器件，其特征在于，所述第一区域周围的所述绝缘材料不覆盖在所述第一区域上方。
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