CN205177843U - 集成电路 - Google Patents
集成电路 Download PDFInfo
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- CN205177843U CN205177843U CN201520967415.6U CN201520967415U CN205177843U CN 205177843 U CN205177843 U CN 205177843U CN 201520967415 U CN201520967415 U CN 201520967415U CN 205177843 U CN205177843 U CN 205177843U
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Abstract
一种集成电路,包括第一区,包括绝缘体上硅型的衬底,所述绝缘体上硅型的衬底包括在掩埋绝缘层上的半导体膜,所述掩埋绝缘层在载体衬底上;第二区,包括所述载体衬底和所述掩埋绝缘层但是不存在所述半导体膜;第一晶体管,在所述第二区中,包括置于所述载体衬底上并且由所述掩埋绝缘层的一部分形成的第一栅极电介质区域。
Description
技术领域
本实用新型涉及集成电路,并且更具体地涉及从绝缘体上硅(SOI)并且更具体地从完全耗尽绝缘体上硅(FDSOI)型衬底制造能够保持高电压(例如2至5伏特或者更多)的晶体管,其中这些示例不是限制性的。
背景技术
绝缘体上硅型的衬底包括位于掩埋绝缘层(通常由首字母缩略词“BOX”(用于掩埋氧化物)指定)上的例如由硅或硅合金(例如,硅锗合金)制成的半导体膜,BOX自己在载体衬底(例如,半导体阱)上。
在完全耗尽SOI(FDSOI)技术中,半导体膜被完全耗尽,即,它由本征半导体组成。其厚度通常约若干纳米,例如7纳米。此外,掩埋绝缘层本身通常具有约二十纳米的小的厚度。
由于半导体膜的小的厚度,晶体管的源极和漏极区域包括相对于半导体膜抬升的部分,以便确保在这些区域与晶体管的沟道区域之间的充足的电连接。
通常通过外延获得这类抬升源极和漏极区域(本领域中通常由首字母缩略词“RSD”指定:用于抬升源极和漏极)。
此外,制造通常能够承受约多个伏特的高电压的晶体管,诸如例如延伸漏极MOS晶体管(本领域中已知为首字母缩略词“DRiftMOS”),需要形成厚的栅极氧化物。
然而,由于半导体膜的小的厚度,这证明,在SOI上并且特别是在FDSOI型衬底上进行实现是复杂的。
具体地,半导体膜将在制造这些厚氧化物期间被部分地消耗。此外,因为需要维持半导体膜的初始厚度(例如,7纳米),那么需要以较厚的半导体膜开始,由于半导体膜的预期消耗,该半导体膜的厚度必须被调整以获得精细的所述初始厚度。
实用新型内容
根据一种实施方式,提出从绝缘体上硅型的衬底制造具有厚栅极氧化物的晶体管而不增加半导体膜的初始厚度。
此外,就这点而言,有利地提出了使用绝缘体上硅型的衬底的掩埋绝缘层(BOX)的至少一部分来形成晶体管的栅极电介质区域的至少一部分,例如MOS晶体管或者甚至具有双栅极(浮置栅极和控制栅极)的晶体管,诸如合并在FLASH和EEPROM型存储器单元中的晶体管的类型。
根据一个方面,提供了一种集成电路,包括:第一区,包括绝缘体上硅型的衬底,所述绝缘体上硅型的衬底包括在掩埋绝缘层上的半导体膜,所述掩埋绝缘层在载体衬底上;第二区,包括所述载体衬底和所述掩埋绝缘层但是不存在所述半导体膜;第一晶体管,在所述第二区中,包括置于所述载体衬底上并且由所述掩埋绝缘层的一部分形成的第一栅极电介质区域。
可选地,进一步包括在所述第一区中的第二晶体管,所述第二晶体管包括置于所述半导体膜上的第二栅极电介质区域,所述第二栅极电介质区域比所述第一栅极电介质区域更薄。
可选地,所述掩埋绝缘层的所述一部分的厚度比所述绝缘体上硅型的衬底的所述掩埋绝缘层的厚度更薄。
可选地,所述第二栅极电介质区域由至少一层第一电介质材料形成,并且其中所述第一晶体管进一步包括位于所述掩埋绝缘层的所述一部分上的所述至少一层第一电介质。
可选地,所述第一电介质材料是高相对介电常数的材料。
可选地,进一步包括:在所述第二区中,具有置于所述载体衬底上并且由所述掩埋绝缘层的另一部分形成的第二栅极电介质区域的第二晶体管,用于所述第一晶体管的所述掩埋绝缘层的所述一部分和用于所述第二晶体管的所述掩埋绝缘层的所述另一部分具有不同的厚度。
可选地,位于所述第二区中的所述第一晶体管是双栅极晶体管,包括:通过所述掩埋绝缘层的所述一部分与所述载体衬底分离的浮置栅极第一区域;以及通过栅极电介质区域与所述浮置栅极第一区域分离的控制栅极第二区域。
根据本公开的另一方面,提供一种集成电路,包括:绝缘体上硅型的衬底,包括在掩埋绝缘层上的半导体膜,所述掩埋绝缘层在载体衬底上;所述衬底的第一区域,包括用于第一晶体管栅极绝缘层的在所述衬底的第一区域中的电介质层,所述电介质层置于所述半导体膜的顶上;所述衬底的第二区域,缺少所述半导体膜并且包括用于第二晶体管栅极绝缘层的所述掩埋绝缘层的一部分,所述掩埋绝缘层的所述一部分置于所述载体衬底的顶上;用于第一晶体管的第一栅极电极,在所述第一晶体管栅极绝缘层之上;以及用于第二晶体管的第二栅极电极,在所述第二晶体管栅极绝缘层之上。
可选地,进一步包括:用于所述第一晶体管的源极-漏极区域,包括在所述半导体膜上的抬升外延结构;以及用于所述第二晶体管的源极-漏极区域,包括在所述载体衬底中的注入剂。
可选地,所述电介质层被定位在所述第二栅极电极与所述第二晶体管栅极绝缘层之间。
附图说明
在检查了对实施方法和实施例的完全非限制性方法的详细描述以及附图之后,本实用新型的其它特征和优点将变得显而易见,其中:
图1至图8示意性地图示了本实用新型的实施方法和实施例。
具体实施方式
在图1中,基准IC指代一种集成电路,在第一区Z1中,该集成电路包括完全耗尽绝缘体上硅(FDSOI)衬底,其包括在掩埋绝缘层2(BOX)(例如具有25纳米的厚度)上的半导体膜3(例如具有7纳米的厚度),掩埋绝缘层2本身由载体衬底1支撑,载体衬底1可以例如是半导体阱。
第一MOS晶体管T1例如以28纳米CMOS技术节点在半导体膜3中和上制造,并且通过隔离区域RIS与集成电路的其它部件隔离,隔离区域RIS例如包括浅沟槽隔离(STI)和深沟槽隔离(DTI)。
晶体管T1包括通过第一栅极电介质区域OX1与半导体膜3绝缘的第一栅极区域RG1,第一栅极电介质区域OX1在这里包括高相对介电常数K(通常高于15)的电介质材料的层。通过指示的方式,层OX1的厚度是约4纳米。
栅极区域RG1的侧翼为绝缘横向区域ESP1,在本领域中通常称为“间隔体”。
晶体管T1还包括源极S和漏极D区域,包括通常通过外延获得的抬升部分。
在载体衬底1中和上制造的第二MOS晶体管T2位于集成电路IC的第二区Z2中。
更确切地,晶体管T2包括通过第二栅极电介质区域与载体衬底1绝缘的第二栅极区域RG2,第二栅极电介质区域在这里包括电介质层OX1和掩埋绝缘层2的一部分200。因此,晶体管T2的第二栅极电介质区域的厚度大于晶体管T1的栅极电介质OX1的第一区域的厚度。
通常,为了制造能够承受3至5伏特的电压的晶体管,第二栅极电介质区域的总厚度约8纳米,其中层200的厚度约4纳米。
常规地,第二晶体管T2还包括在栅极区域RG2的侧翼上制造的间隔体ESP2以及在载体衬底1中注入的源极S和漏极D区域。
FDSOI衬底的掩埋绝缘层2的剩余部分因此允许非常简单地并且在不消耗半导体膜3的情况下制造具有厚栅极电介质区域的晶体管T2。
此外,如图2所示,还可以在区Z2上制造具有不同厚度的栅极电介质区域的多个晶体管T2、T3,所述栅极电介质区域通常利用具有不同厚度的掩埋绝缘层的剩余部分获得。
因此,如图2所示,晶体管T3具有栅极电介质区域,其包括具有大于晶体管T2的栅极电介质区域的一部分200的厚度的掩埋绝缘层部分201。
现在更确切地参考图3至图7,以便图示根据本实用新型的工艺的一种实施方法。
在图3中,工艺开始于绝缘体上硅衬底,其包括由掩埋绝缘层2(BOX)支撑的半导体膜3,掩埋绝缘层2本身由载体衬底1支撑。
在这里,集成电路的区Z1和Z2以本身已知的常规方式已经被隔离区域RIS界定。
此外,常规情况下,半导体膜3由本领域中通常称为“PADOX”的钝化层4所覆盖,钝化层4旨在在先前操作(例如,阱注入)期间保护半导体膜3的表面。
接着,第一区Z1由抗蚀剂掩模50保护,然后在集成电路的区Z2中执行刻蚀GV1,以便去除位于区Z2中的下面的钝化层4和半导体膜3,而留下掩埋绝缘层2的剩余部分20(在实施例中,其厚度小于例如在区Z1中的BOX2的厚度)。
在去除在区Z1中的掩模50和钝化层4之后,获得图4中所图示的结构。
接着,以本身已知的常规方式,沉积栅极电介质材料(例如,高相对介电常数的材料)的至少一层4,并且然后沉积栅极材料(例如,多晶硅和/金属)的层5,其中这些示例不是限制性的(图5)。
接着,如图6所示,使用本身已知的常规刻蚀GV2来图案化栅极区域RG1和RG2以及栅极电介质OX1,从而限定栅极堆叠。
接着,以本身已知的常规方式在栅极堆叠的每一侧上形成绝缘横向区域ESP1和ESP2,并且使用刻蚀GV3去除掩埋绝缘层的剩余部分20的位于间隔体ESP2的外部的那部分,以便形成掩埋绝缘层部分200。
就区Z2的晶体管的源极和漏极区域的制造而言,多个变形是可能的。
根据第一变形,源极和漏极区域通过同时外延来制造,从而制造区Z1的晶体管的抬升的源极区域和漏极区域,这意味着区Z2的晶体管的源极和漏极区域也被抬升。
既然如此,特别是当区Z2的晶体管是高电压晶体管时,抬升源极和漏极区域的存在在大部分情况下是不需要的,这是因为在栅极区域与这些抬升源极和漏极区域之间的绝缘间隔体ESP2的击穿的风险,这具有限制器件的电压承受能力的风险。
因此,根据第二变形,在刻蚀掩埋绝缘层的所述剩余部分20之前,通过外延制造区Z1的晶体管的抬升源极和漏极区域。具体地,随后覆盖了区Z2中的整个载体衬底的该剩余掩埋绝缘层部分阻挡了区Z2中的源极和漏极区域的生长。
接着,在区Z1中形成抬升源极和漏极区域之后,使用刻蚀GV3去除掩埋绝缘层的剩余部分20的位于间隔体ESP2外部的那部分,从而形成掩埋绝缘层部分200,并且然后在载体衬底1中注入源极和漏极区域。
作为变形,还可以通过调整注入能量而穿过掩埋绝缘层的剩余部分20位于间隔体ESP2外部的那部分来注入源极和漏极区域。因此,并不绝对地需要在注入之前刻蚀GV3源极和漏极区域。
本实用新型不限于已经描述的实施方法和实施例而是包含其任何变形。
因此,如图8所示,可以在集成电路的区Z2中制造包括浮置栅极的晶体管T4,诸如在诸如FLASH或EEPROM单元之类的非易失性存储器单元中所使用的那些。
更确切地,如图8所示,存储器单元的晶体管T4包括通过作为掩埋绝缘层2的剩余部分的第一栅极氧化物204与载体衬底1分离的浮置栅极FG。
此外,晶体管T4包括通过电介质区域RD1(例如,氧化物-氮化物-氧化物多层)与浮置栅极FG分离的控制栅极CG。
两个栅极和电介质区域RD1和204的侧翼为横向间隔体ESP4。
使用通过刻蚀获得的掩埋绝缘层的剩余层使得可以精确且简单地调整栅极氧化物204的厚度,而不具有消耗半导体膜3的风险,例如以便获得约12纳米的厚度,该厚度非常适于使用FowlerNordheim效应进行擦除。
Claims (10)
1.一种集成电路,其特征在于,包括:
第一区,包括绝缘体上硅型的衬底,所述绝缘体上硅型的衬底包括在掩埋绝缘层上的半导体膜,所述掩埋绝缘层在载体衬底上;
第二区,包括所述载体衬底和所述掩埋绝缘层但是不存在所述半导体膜;
第一晶体管,在所述第二区中,包括置于所述载体衬底上并且由所述掩埋绝缘层的一部分形成的第一栅极电介质区域。
2.根据权利要求1所述的集成电路,其特征在于,进一步包括在所述第一区中的第二晶体管,所述第二晶体管包括置于所述半导体膜上的第二栅极电介质区域,所述第二栅极电介质区域比所述第一栅极电介质区域更薄。
3.根据权利要求1所述的集成电路,其特征在于,所述掩埋绝缘层的所述一部分的厚度比所述绝缘体上硅型的衬底的所述掩埋绝缘层的厚度更薄。
4.根据权利要求2所述的集成电路,其特征在于,所述第二栅极电介质区域由至少一层第一电介质材料形成,并且其中所述第一晶体管进一步包括位于所述掩埋绝缘层的所述一部分上的所述至少一层第一电介质。
5.根据权利要求4所述的集成电路,其特征在于,所述第一电介质材料是高相对介电常数的材料。
6.根据权利要求1所述的集成电路,其特征在于,进一步包括:在所述第二区中,具有置于所述载体衬底上并且由所述掩埋绝缘层的另一部分形成的第二栅极电介质区域的第二晶体管,用于所述第一晶体管的所述掩埋绝缘层的所述一部分和用于所述第二晶体管的所述掩埋绝缘层的所述另一部分具有不同的厚度。
7.根据权利要求1所述的集成电路,其特征在于,位于所述第二区中的所述第一晶体管是双栅极晶体管,包括:
通过所述掩埋绝缘层的所述一部分与所述载体衬底分离的浮置栅极第一区域;以及
通过栅极电介质区域与所述浮置栅极第一区域分离的控制栅极第二区域。
8.一种集成电路,其特征在于,包括:
绝缘体上硅型的衬底,包括在掩埋绝缘层上的半导体膜,所述掩埋绝缘层在载体衬底上;
所述衬底的第一区域,包括用于第一晶体管栅极绝缘层的在所述衬底的第一区域中的电介质层,所述电介质层置于所述半导体膜的顶上;
所述衬底的第二区域,缺少所述半导体膜并且包括用于第二晶体管栅极绝缘层的所述掩埋绝缘层的一部分,所述掩埋绝缘层的所述一部分置于所述载体衬底的顶上;
用于第一晶体管的第一栅极电极,在所述第一晶体管栅极绝缘层之上;以及
用于第二晶体管的第二栅极电极,在所述第二晶体管栅极绝缘层之上。
9.根据权利要求8所述的集成电路,其特征在于,进一步包括:
用于所述第一晶体管的源极-漏极区域,包括在所述半导体膜上的抬升外延结构;以及
用于所述第二晶体管的源极-漏极区域,包括在所述载体衬底中的注入剂。
10.根据权利要求8所述的集成电路,其特征在于,所述电介质层被定位在所述第二栅极电极与所述第二晶体管栅极绝缘层之间。
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CN105990374B (zh) * | 2015-03-18 | 2019-07-16 | 意法半导体(克洛尔2)公司 | 集成电路和用于制造晶体管的方法 |
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