TWI515859B - 內連線結構和其製作方法 - Google Patents

內連線結構和其製作方法 Download PDF

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Publication number
TWI515859B
TWI515859B TW102137864A TW102137864A TWI515859B TW I515859 B TWI515859 B TW I515859B TW 102137864 A TW102137864 A TW 102137864A TW 102137864 A TW102137864 A TW 102137864A TW I515859 B TWI515859 B TW I515859B
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Taiwan
Prior art keywords
substrate
pad
forming
hole
interconnect structure
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TW102137864A
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English (en)
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TW201419487A (zh
Inventor
蔡欣昌
李嘉炎
李芃昕
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台達電子工業股份有限公司
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Publication of TW201419487A publication Critical patent/TW201419487A/zh
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    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Description

內連線結構和其製作方法
本發明係有關於一種積體電路裝置及其製作方法，特別是有關於一種內連線結構和其製作方法。
半導體構件包括外部連接，使得電連接可從外部連接至半導體構件中的積體電路。例如，一半導體晶粒包括形成在晶粒表面之接合墊圖案，而晶片尺寸封裝(chip scale package)之半導體封裝體亦包括外部連接。一般來說，構件在其表面側(電路側)或背面側包括外部連接，且構件有時於表面側和背面側均需有外部連接。
在半導體技術中，穿基底導孔(through substrate via)是形成在半導體基底(晶圓或晶粒)中的導電圖樣，以電性連接基底兩側之外部連接。TSV垂直穿過半導體基底，提供堆疊的晶圓/晶粒之封裝方法，使得分隔晶圓或晶粒之電路間可形成電性連接。形成TSV之方法包括許多種，一般來說，其包括對半導體基底進行蝕刻，形成孔洞，且孔洞有時可穿過內連線結構。孔洞中可包括絕緣層及/或金屬層。孔洞後續填入一般為銅之導電材料，形成TSV之主要部分。
傳統的技術使用電鍍法形成填入TSV孔洞中的導電填充材料，而電鍍技術之晶種層(seeding layer)使用如 物理氣相沉積之真空技術在填入導電填充材料之前形成。然而，真空技術為高價的設備，因此增加元件的成本。
根據上述，本發明於一實施例提供一種內連線結構，包括：一基底，具有至少一電子元件和一穿過基底之通孔，其中至少一電子元件鄰近基底之第一側，通孔具有一第一開口，鄰近基底之第一側一導孔結構，位於通孔中，其中導孔結構不超過第一開口；一第一墊，位於基底之第一側且覆蓋通孔，其中第一墊鄰接導孔結構且電性連接至少一電子元件。
本發明於一實施例提供一種內連線結構之製作方法，包括：提供一基底，具有一第一側和一相對於第一側之一第二側；形成一通孔，穿過基底，其中通孔具有一第一開口和一第二開口，第一開口鄰近基底之第一側，第二開口鄰近基底之第二側；形成一第一墊，覆蓋第一開口；在形成第一墊之後，形成一導孔結構於通孔中，其中導孔結構包括導電材料，且鄰接第一墊。
本發明於一實施例提供一種內連線結構之製作方法，包括：提供一基底；形成一通孔，穿過基底；及於基底之一第一側進行一網印製程，填入一導電材料於通孔中，以於通孔中形成一導孔結構和位於基底之一第一側之第一墊，其中第一墊鄰接導孔結構。
102‧‧‧基底
104‧‧‧緩衝層
106‧‧‧第一側
108‧‧‧第二側
110‧‧‧通道層
111‧‧‧第一開口
112‧‧‧阻障層
113‧‧‧第二開口
114‧‧‧電子元件
116‧‧‧閘電極
118‧‧‧源極電極
120‧‧‧汲極電極
122‧‧‧鈍化層
124‧‧‧感光層
126‧‧‧通孔
128‧‧‧絕緣層
130‧‧‧第一墊
132‧‧‧導孔結構
134‧‧‧第二墊
202‧‧‧第一墊
302‧‧‧基底
304‧‧‧緩衝層
306‧‧‧第一側
308‧‧‧第二側
310‧‧‧通道層
311‧‧‧第二開口
312‧‧‧阻障層
314‧‧‧電子元件
316‧‧‧閘電極
318‧‧‧源極電極
320‧‧‧汲極電極
324‧‧‧感光層
326‧‧‧通孔
328‧‧‧絕緣層
330‧‧‧第一墊
332‧‧‧導孔結構
334‧‧‧第二墊
第1A圖~第1F圖顯示本發明一實施例形成內連線結構之方法中間階段的剖面圖。
第2圖顯示本發明另一實施例形成內連線結構之方法中間階段的剖面圖。
第3A圖~第3F圖顯示本發明另一實施例形成內連線結構之方法中間階段的剖面圖。
以下詳細討論實施本發明之實施例。可以理解的是，實施例提供許多可應用的發明概念，其可以較廣的變化實施。所討論之特定實施例僅用來發明使用實施例的特定方法，而不用來限定發明的範疇。為讓本發明之特徵能更明顯易懂，下文特舉實施例，並配合所附圖式，作詳細說明如下：
以下配合第1A圖~第1F圖描述本發明一實施例形成內連線結構之方法。首先，請參照第1A圖，提供一基底102，包括第一側106和相對於第一側106之第二側108。基底102可包括任何適合之半導體材料。例如基底102可包括Si、SiC、Ge、SiGe、GaAs、InAs、InP或GaN。後續，形成一緩衝層104於基底102上。在本發明一實施例中，緩衝層104是氮化物材料，以提供後續形成於其上層良好的粘著性，且亦可解決晶格不協調的問題。然而，本發明不限定於上述材料，緩衝層104可以任何適合的材料形成。在本發明一實施例中，緩衝層104可以是氮化鋁。
後續，形成一通道層110和一阻障層112於緩衝 層104上。在一實施例中，通道層110可以是GaN，阻障層112可以是AlGaN。接著，形成一第一金屬層(未繪示)於通道層110上，並對第一金屬層進行微影和蝕刻之圖案化步驟，形成一源極電極118和一汲極電極120。在本發明一實施例中，第一金屬層是Ti、Al、Ni及/或Au的堆疊層。在形成第一金屬層之後，可對其進行快速熱退火之步驟。接著，沉積一第二金屬層(未繪示)於通道層110上，對第二金屬層進行微影和蝕刻之圖案化步驟，以形成閘電極116。後續，形成例如氮化矽或氧化矽之鈍化層122(passivation layer)，以保護其下的元件。
通道層110、阻障層112、閘電極116、源極電極118和汲極電極120構成鄰近基底102第一側106之電子元件114。本發明在一實施例中係將電子元件114設置為鄰近基底102之第一側106，但本發明不限於此，電子元件114可設置於基底102之第二側108。在一實施例中，電子元件114為氮化物半導體元件，然而，本發明不限定電子元件為氮化物半導體元件，電子元件可以為任何適合之半導體元件，例如矽基元件、III-V族元件及/或絕緣層上有矽(SOI)元件。
接著，請參照第1B圖，形成一感光層124於基底102上方。後續，請參照第1C圖，進行一微影製程，圖案化感光層124，且使用圖案化之感光層124作為蝕刻罩幕，蝕刻基底102，形成穿過基底102之通孔126(via)。在一實施例中，可使用雷射光束形成通孔126。
請參照第1D圖，形成一絕緣層128於通孔126之側壁上，以作為保護和隔離之用途。在一實施例中，絕緣層128可以是氧化矽，其可以熱氧化法或液相沈積法(Liquid phase deposition，簡稱LPD)形成。請參照第1E圖，形成第一墊130於基底102之第一側106上，且覆蓋通孔126之第一開口111。第一墊130可電性連接電子元件114和後續步驟形成之第二墊134，且包括一凸出部分，延伸至通孔126中。在一實施例中，第一墊130可包括銀膠，且可使用網印法形成。請參照第1F圖，以第一墊130作為晶種層，進行一電鍍製程，成長一導電材料以填入通孔126中，而形成一導孔結構132。在一實施例中，導孔結構132和第一墊130包括相同的材料。在另一實施例中，導孔結構132和第一墊130包括不同的材料。例如，第一墊130和導孔結構132皆可包括銅或銀。
如第1F圖所示，由於導孔結構132在形成第一墊130之後形成，導孔結構132不延伸超過通孔126之鄰近基底102之第一側106的第一開口111，但可延伸超過通孔126之鄰近基底102之第二側108的第二開口113。後續，形成第二墊134於基底102之第二側108上。在一實施例中，第二墊134可包括銀膠，且可使用網印法形成。雖然圖式中未繪示，本發明可包括另一半導體基底，其具有另一電子元件，且該另一電子元件電性連接第二墊。
在本發明之一實施例中，電子元件114是高移動率電晶體(high electron mobility transistor，簡稱 HEMT)，且基底102包括半導體基底。電子元件114可經由導孔結構132電性連接至半導體基底另一側其他電子元件(未繪示)。
以下以第2圖描述本發明另一實施例形成內連線結構之方法。第2圖之內連線結構的形成方法類似第1E圖~第1F圖之內連線結構的形成方法，為簡潔，相同的部分在此不重複描述。第2圖之內連線結構的形成方法與第1E圖~第1F圖之內連線結構的形成方法不同處在於第一墊202和導孔結構204以單一步驟形成。在一實施例中，通孔126之深度不深(例如20μm~50μm)，如第2圖所示，形成第一墊202之網印法亦可填滿通孔126，所以可以單一網印步驟形成第一墊202和導孔結構204。
以下配合第3A圖~第3F圖描述本發明另一實施例形成內連線結構之方法。第3A圖~第3F圖與第1A圖~第1F圖實施例不同處為在形成導孔結構前，形成墊於基底與第一側(鄰近電子元件)相對之第二側。首先，請參照第3A圖，提供一基底302，包括第一側306和一第二側308。基底302可包括任何適合之半導體材料。例如基底302可包括Si、SiC、Ge、SiGe、GaAs、InAs、InP或GaN。後續，形成一緩衝層304於基底302上。在本發明一實施例中，緩衝層304可以是氮化鋁。後續，形成一通道層310和一阻障層312於緩衝層304上。在一實施例中，通道層310可以是GaN，阻障層312可以是AlGaN。接著，形成一第一金屬層(未繪示)於通道層310上，且對第一金屬層進行微影和蝕刻之圖案化 步驟，形成一源極電極318和一汲極電極320。在本發明一實施例中，第一金屬層是Ti、Al、Ni及/或Au的堆疊層。在形成第一金屬層之後，可對其進行快速熱退火之步驟。接著，沉積一第二金屬層(未繪示)於通道層310上，對第二金屬層進行微影和蝕刻之圖案化步驟，以形成閘電極316。後續，形成例如氮化矽或氧化矽之鈍化層322(passivation layer)，以保護其下的元件。
通道層310、阻障層312、閘電極316、源極電極318和汲極電極320構成鄰近基底302第一側306之電子元件314。在一實施例中，電子元件314為氮化物半導體元件，然而，本發明不限定電子元件為氮化物半導體元件，電子元件可為任何適合之半導體元件，例如矽基元件、III-V族元件及/或絕緣層上有矽(SOI)元件。
接著，請參照第3B圖，形成一感光層324於基底302上方，以保護電子元件314。後續，請參照第3C圖，進行一微影製程，圖案化感光層324，且使用圖案化之感光層324作為蝕刻罩幕，蝕刻基底302，形成穿過基底302之通孔326(via)。在一實施例中，可使用雷射光束形成通孔326。
請參照第3D圖，形成一絕緣層328於通孔326之側壁上，以作為保護和隔離之用途。在一實施例中，絕緣層328可以是氧化矽，其可以熱氧化法或液相沈積法(LPD)形成。請參照第3E圖，形成第一墊330於基底302之第二側308上，且覆蓋通326之第二開口311。在一實施例中，第一墊330可包括銀膠，且可使用網印法形成。請參照第3F圖， 以第一墊330作為晶種層，進行一電鍍製程，形成填入通孔326中之導孔結構332。在一實施例中，導孔結構332和第一墊330包括相同的材料。在另一實施例中，導孔結構332和第一墊330包括不同的材料。例如，第一墊330和導孔結構332皆可包括銅或銀。如第3F圖所示，由於導孔結構332在形成第一墊330之後形成，導孔結構332不延伸超過通孔326之鄰近基底302之第二側308的第二開口311，但可延伸超過通孔326之鄰近基底302之第一側306的第一開口313。後續，形成例如銀膠之第二墊334於基底302之第一側306上。
本發明實施例形成內連線結構之方法具有以下優點：由於本發明形成內連線結構之方法在使用導孔結構之電鍍製程中使用第一墊作為晶種層，在形成內連線的過程中不需使用真空製程，因此可以較低的成本製作半導體元件。
雖然本發明之較佳實施例說明如上，然其並非用以限定本發明，任何熟習此領域之技術者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
102‧‧‧基底
104‧‧‧緩衝層
106‧‧‧第一側
108‧‧‧第二側
110‧‧‧通道層
111‧‧‧第一開口
112‧‧‧阻障層
113‧‧‧第二開口
114‧‧‧電子元件
116‧‧‧閘電極
118‧‧‧源極電極
120‧‧‧汲極電極
122‧‧‧鈍化層
126‧‧‧通孔
128‧‧‧絕緣層
130‧‧‧第一墊
132‧‧‧導孔結構
134‧‧‧第二墊

Claims (20)

  1. 一種內連線結構，包括：一基底，具有至少一電子元件和一穿過該基底之通孔，其中該至少一電子元件鄰近該基底之第一側，該通孔具有一第一開口，鄰近該基底之該第一側；一導孔結構，位於該通孔中，其中該導孔結構不超過該第一開口；及一第一墊，位於該基底之第一側且覆蓋該通孔之該第一開口，其中該第一墊鄰接該導孔結構且電性連接該至少一電子元件。
  2. 如申請專利範圍第1項所述之內連線結構，其中該第一墊包括一凸出部分，延深至該通孔。
  3. 如申請專利範圍第1項所述之內連線結構，更包括一第二墊，位於該基底之第二側，且鄰接該導孔結構。
  4. 如申請專利範圍第1項所述之內連線結構，更包括一絕緣層，位於該通孔之側壁上，且圍繞該導孔結構。
  5. 如申請專利範圍第1項所述之內連線結構，其中該第一墊和該導孔結構包括不同的材料。
  6. 如申請專利範圍第1項所述之內連線結構，其中該第一墊和該導孔結構包括相同的材料。
  7. 如申請專利範圍第1項所述之內連線結構，其中該導孔結構包括銅。
  8. 如申請專利範圍第1項所述之內連線結構，其中該第一墊包括銀膠。
  9. 一種內連線結構之製作方法，包括：提供一基底，具有一第一側和一相對於該第一側之一第二側；形成一通孔，穿過該基底，其中該通孔具有一第一開口和一第二開口，該第一開口鄰近該基底之該第一側，該第二開口鄰近該基底之該第二側；形成一第一墊，覆蓋該通孔之該第一開口；及在形成該第一墊之後，形成一導孔結構於該通孔中，其中該導孔結構包括導電材料，且鄰接該第一墊，且該導孔結構不超過該第一開口。
  10. 如申請專利範圍第9項所述之內連線結構之製作方法，更包括：形成至少一電子元件於該基底上；及在形成該通孔前，形成一感光層於該基底上，覆蓋該至少一電子元件。
  11. 如申請專利範圍第9項所述之內連線結構之製作方法，其中在形成該導孔結構前，更包括形成一絕緣層於該通孔之側壁上。
  12. 如申請專利範圍第9項所述之內連線結構之製作方法，其中形成該第一墊之步驟包括進行一第一金屬網印製程，形成該第一墊，覆蓋該第一開口。
  13. 如申請專利範圍第9項所述之內連線結構之製作方法，其中在形成該導孔結構後，更包括形成一第二墊，覆蓋該導孔結構。
  14. 如申請專利範圍第9項所述之內連線結構之製作方法，其中形成該通孔穿過該基底之步驟包括使用雷射光束對該基底進行鑽孔。
  15. 如申請專利範圍第9項所述之內連線結構之製作方法，其中形成該導孔結構係為使用以該第一墊作為晶種層之電鍍製程。
  16. 一種內連線結構之製作方法，包括：提供一基底；形成一通孔，穿過該基底，其中該通孔具有一第一開口；及於該基底之一第一側進行一網印製程，填入一導電材料於該通孔中，以於該通孔中形成一導孔結構和位於該基底之一第一側之第一墊，其中該第一墊鄰接該導孔結構，且該導孔結構不超過該第一開口，該第一墊覆蓋該通孔之該第一開口。
  17. 如申請專利範圍第16項所述之內連線結構之製作方法，更包括：形成至少一電子元件於該基底上；及在形成該通孔前，形成一感光層於該基底上，覆蓋該至少一電子元件。
  18. 如申請專利範圍第17項所述之內連線結構之製作方法，其中該電子元件位於該基底之第一側。
  19. 如申請專利範圍第17項所述之內連線結構之製作方法，其中該電子元件位於該基底之第二側，該第二側相 對於該第一側。
  20. 如申請專利範圍第16項所述之內連線結構之製作方法，其中在形成該導孔結構前，更包括形成一絕緣層於該通孔之側壁上。
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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140073163A (ko) * 2012-12-06 2014-06-16 삼성전자주식회사 반도체 장치 및 그의 형성방법
US9659851B2 (en) * 2014-02-07 2017-05-23 Marvell World Trade Ltd. Method and apparatus for improving the reliability of a connection to a via in a substrate
FR3028095B1 (fr) 2014-11-04 2018-01-26 Commissariat A L'energie Atomique Et Aux Energies Alternatives Dispositif electronique de puissance a cellule de commutation 3d verticale
KR20170011366A (ko) * 2015-07-22 2017-02-02 삼성전자주식회사 반도체 칩 및 이를 가지는 반도체 패키지
CN109671773B (zh) * 2017-10-16 2020-05-05 苏州能讯高能半导体有限公司 半导体器件及其制造方法
US10366982B2 (en) 2017-11-30 2019-07-30 Taiwan Semiconductor Manufacturing Co., Ltd. Structure with embedded memory device and contact isolation scheme
DE112018007009T5 (de) * 2018-02-01 2020-11-05 Mitsubishi Electric Corporation Halbleitervorrichtung und Herstellungsverfahren für diese
US11004794B2 (en) 2018-06-27 2021-05-11 Taiwan Semiconductor Manufacturing Co., Ltd. Partial barrier free vias for cobalt-based interconnects and methods of fabrication thereof
CN109300947B (zh) * 2018-09-28 2021-09-07 京东方科技集团股份有限公司 柔性显示基板及其制造方法、显示装置
EP3783663A1 (en) * 2019-08-21 2021-02-24 Infineon Technologies AG Semiconductor device and method
FR3122036A1 (fr) * 2021-04-14 2022-10-21 Exagan Dispositif bidirectionnel pourvu d’un empilement de deux transistors a haute mobilite electronique connectes tete-beche
US11967519B2 (en) 2021-05-11 2024-04-23 Innoscience (suzhou) Semiconductor Co., Ltd. Integrated semiconductor device and method for manufacturing the same
TWI813100B (zh) * 2021-12-17 2023-08-21 世界先進積體電路股份有限公司 半導體結構與其製造方法

Family Cites Families (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5447871A (en) * 1993-03-05 1995-09-05 Goldstein; Edward F. Electrically conductive interconnection through a body of semiconductor material
US6620731B1 (en) 1997-12-18 2003-09-16 Micron Technology, Inc. Method for fabricating semiconductor components and interconnects with contacts on opposing sides
TWI244571B (en) * 2002-01-30 2005-12-01 Sanyo Electric Co Semiconductor display device
WO2003071843A1 (fr) * 2002-02-22 2003-08-28 Fujikura Ltd. Tableau de connexions multicouche, base pour tableau de connexions multicouche, tableau de connexions imprime et son procede de production
US7045861B2 (en) * 2002-03-26 2006-05-16 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device, liquid-crystal display device and method for manufacturing same
JP2004095849A (ja) * 2002-08-30 2004-03-25 Fujikura Ltd 貫通電極付き半導体基板の製造方法、貫通電極付き半導体デバイスの製造方法
JP3937993B2 (ja) * 2002-10-02 2007-06-27 日立電線株式会社 配線板の製造方法
US6828512B2 (en) * 2002-10-08 2004-12-07 Intel Corporation Apparatus and methods for interconnecting components to via-in-pad interconnects
JP2004146748A (ja) * 2002-10-28 2004-05-20 Alps Electric Co Ltd 薄膜キャパシタ素子
CN1759492B (zh) * 2003-03-10 2010-04-28 丰田合成株式会社 固体元件装置的制造方法
US6897148B2 (en) * 2003-04-09 2005-05-24 Tru-Si Technologies, Inc. Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby
JP3891299B2 (ja) * 2003-05-06 2007-03-14 セイコーエプソン株式会社 半導体装置の製造方法、半導体装置、半導体デバイス、電子機器
GB0311251D0 (en) * 2003-05-16 2003-06-18 Koninkl Philips Electronics Nv Method of manufacture recyclable electronic products and electronic products obtained by the method
US7919787B2 (en) * 2003-06-27 2011-04-05 Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. Semiconductor device with a light emitting semiconductor die
KR100493063B1 (ko) * 2003-07-18 2005-06-02 삼성전자주식회사 스택 반도체 칩 비지에이 패키지 및 그 제조방법
US8084866B2 (en) * 2003-12-10 2011-12-27 Micron Technology, Inc. Microelectronic devices and methods for filling vias in microelectronic devices
JP2005303258A (ja) * 2004-03-16 2005-10-27 Fujikura Ltd デバイス及びその製造方法
JP4327644B2 (ja) * 2004-03-31 2009-09-09 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
US7498647B2 (en) * 2004-06-10 2009-03-03 Micron Technology, Inc. Packaged microelectronic imagers and methods of packaging microelectronic imagers
KR100594716B1 (ko) * 2004-07-27 2006-06-30 삼성전자주식회사 공동부를 구비한 캡 웨이퍼, 이를 이용한 반도체 칩, 및그 제조방법
JP4803993B2 (ja) * 2004-11-09 2011-10-26 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US7476918B2 (en) * 2004-11-22 2009-01-13 Panasonic Corporation Semiconductor integrated circuit device and vehicle-mounted radar system using the same
EP1920459A4 (en) * 2005-08-12 2012-07-25 Semiconductor Energy Lab PROCESS FOR PRODUCING A SEMICONDUCTOR COMPONENT
JP4758712B2 (ja) * 2005-08-29 2011-08-31 新光電気工業株式会社 半導体装置の製造方法
US7772116B2 (en) * 2005-09-01 2010-08-10 Micron Technology, Inc. Methods of forming blind wafer interconnects
KR100704915B1 (ko) * 2005-09-15 2007-04-09 삼성전기주식회사 미세 패턴을 가지는 인쇄회로기판 및 그 제조방법
US7633167B2 (en) * 2005-09-29 2009-12-15 Nec Electronics Corporation Semiconductor device and method for manufacturing same
TW200733336A (en) * 2006-02-17 2007-09-01 Advanced Semiconductor Eng Ball grid array package structure with identification marks and substrate thereof
US7741218B2 (en) * 2007-02-27 2010-06-22 Freescale Semiconductor, Inc. Conductive via formation utilizing electroplating
JP2008305938A (ja) * 2007-06-07 2008-12-18 Toshiba Corp 半導体装置および半導体装置の製造方法
WO2009023462A1 (en) * 2007-08-10 2009-02-19 Spansion Llc Semiconductor device and method for manufacturing thereof
JP2009070966A (ja) * 2007-09-12 2009-04-02 Toshiba Corp 半導体装置とその製造方法
JP5536322B2 (ja) * 2007-10-09 2014-07-02 新光電気工業株式会社 基板の製造方法
US8779570B2 (en) * 2008-03-19 2014-07-15 Stats Chippac Ltd. Stackable integrated circuit package system
WO2010011177A1 (en) * 2008-07-24 2010-01-28 Agency For Science, Technology And Research A substrate arrangement and a method of manufacturing a substrate arrangement
US7843072B1 (en) 2008-08-12 2010-11-30 Amkor Technology, Inc. Semiconductor package having through holes
KR101002680B1 (ko) * 2008-10-21 2010-12-21 삼성전기주식회사 반도체 패키지 및 그 제조 방법
JP2010103236A (ja) * 2008-10-22 2010-05-06 Panasonic Corp 窒化物半導体装置
JP5268618B2 (ja) * 2008-12-18 2013-08-21 株式会社東芝 半導体装置
JP5308145B2 (ja) * 2008-12-19 2013-10-09 ルネサスエレクトロニクス株式会社 半導体装置
JP5471268B2 (ja) * 2008-12-26 2014-04-16 大日本印刷株式会社 貫通電極基板及びその製造方法
US7932608B2 (en) * 2009-02-24 2011-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via formed with a post passivation interconnect structure
KR101573934B1 (ko) * 2009-03-02 2015-12-11 엘지전자 주식회사 태양 전지 및 그 제조 방법
CN101847597B (zh) * 2009-03-27 2013-12-04 台湾积体电路制造股份有限公司 集成电路结构
US8329578B2 (en) * 2009-03-27 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Via structure and via etching process of forming the same
CN102185580A (zh) * 2010-01-18 2011-09-14 精工爱普生株式会社 电子装置、基板的制造方法以及电子装置的制造方法
US8518746B2 (en) * 2010-09-02 2013-08-27 Stats Chippac, Ltd. Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die
KR101688006B1 (ko) * 2010-11-26 2016-12-20 삼성전자주식회사 반도체 장치
US20120146111A1 (en) * 2010-12-14 2012-06-14 Shu-Ming Chang Chip package and manufacturing method thereof
CN102569144B (zh) * 2010-12-22 2015-05-13 中芯国际集成电路制造(上海)有限公司 一种通孔刻蚀方法
KR20120071921A (ko) * 2010-12-23 2012-07-03 한국전자통신연구원 실리콘 관통 홀(ｔｓｖ) 충진용 조성물, ｔｓｖ 충진방법 및 상기 조성물을 이용하여 형성된 ｔｓｖ 충진물을 포함하는 기판
JP5595524B2 (ja) * 2010-12-28 2014-09-24 京セラ株式会社 光モジュールおよび光配線基板
KR101801137B1 (ko) * 2011-02-21 2017-11-24 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR101780423B1 (ko) * 2011-03-18 2017-09-22 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US8546900B2 (en) * 2011-06-09 2013-10-01 Optiz, Inc. 3D integration microelectronic assembly for integrated circuit devices

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EP2731132A3 (en) 2017-05-17
US9159699B2 (en) 2015-10-13
CN103811465A (zh) 2014-05-21
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US10424508B2 (en) 2019-09-24

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