TW201419470A - 封裝結構和其製作方法 - Google Patents

封裝結構和其製作方法 Download PDF

Info

Publication number
TW201419470A
TW201419470A TW102137865A TW102137865A TW201419470A TW 201419470 A TW201419470 A TW 201419470A TW 102137865 A TW102137865 A TW 102137865A TW 102137865 A TW102137865 A TW 102137865A TW 201419470 A TW201419470 A TW 201419470A
Authority
TW
Taiwan
Prior art keywords
semiconductor
component
semiconductor component
package structure
electronic component
Prior art date
Application number
TW102137865A
Other languages
English (en)
Other versions
TWI532130B (zh
Inventor
Chia-Yen Lee
Hsin-Chang Tsai
Peng-Hsin Lee
Original Assignee
Delta Electronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Delta Electronics Inc filed Critical Delta Electronics Inc
Publication of TW201419470A publication Critical patent/TW201419470A/zh
Application granted granted Critical
Publication of TWI532130B publication Critical patent/TWI532130B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/033—Manufacturing methods by local deposition of the material of the bonding area
    • H01L2224/0331—Manufacturing methods by local deposition of the material of the bonding area in liquid form
    • H01L2224/0332—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16147—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16148—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73255—Bump and strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一種封裝結構，包括：一第一半導體元件，包括一第一半導體基底和一第一電子元件，第一半導體元件具有一第一側和相對第一側之第二側，其中至少部分第一電子元件鄰近第一側，且其中第一半導體元件具有一通孔，穿過第一半導體元件，其中通孔具有一第一開口，鄰近第一側；一內連線結構，設置於第一半導體元件中，其中內連線結構包括：一導孔結構，設置於通孔中，且導孔結構不超過第一開口；一第一金屬墊，設置於第一半導體元件之第一側上，且覆蓋通孔，其中第一金屬墊鄰接導孔結構，且電性連接第一電子元件；及一第二半導體元件，與第一半導體元件垂直整合，其中第二半導體元件包括一第二電子元件，電性連接第一電子元件。

Description

封裝結構和其製作方法
本發明係有關於一種半導體元件，特別是有關於一種封裝結構和其製作方法。
半導體構件包括外部連接，使得電連接可從外部連接至半導體構件中的積體電路。例如，一半導體晶粒包括形成在晶粒表面之接合墊圖案，而晶片尺寸封裝(chip scale package)之半導體封裝體亦包括外部連接。一般來說，構件在其表面側(電路側)或背面側包括外部連接，且構件有時於表面側和背面側均需有外部連接。
在半導體技術中，穿基底導孔(through substrate via)是形成在半導體基底(晶圓或晶粒)中的導電圖樣，以電性連接基底兩側之外部連接。TSV垂直穿過半導體基底，提供堆疊的晶圓/晶粒之封裝方法，使得分隔晶圓或晶粒之電路間可形成電性連接。形成TSV之方法包括許多種，一般來說，其包括對半導體基底進行蝕刻，形成孔洞，且孔洞有時可穿過內連線結構。孔洞中可包括絕緣層及/或金屬層。孔洞後續填入一般為銅之導電材料，形成TSV之主要部分。
傳統的技術使用電鍍法形成填入TSV孔洞中的導電填充材料，而電鍍技術之晶種層(seed layer)使用如物 理或化學氣相沉積之真空技術在填入導電填充材料之前形成。然而，真空技術為高價的設備，因此增加元件的成本。
根據上述，本發明提供一種封裝結構，包括：一第一半導體元件，包括一第一半導體基底和一第一電子元件，第一半導體元件具有一第一側和相對第一側之第二側，其中至少部分第一電子元件鄰近第一側，且其中第一半導體元件具有一通孔，穿過第一半導體元件，其中通孔具有一第一開口，鄰近第一側；一內連線結構，設置於第一半導體元件中，其中內連線結構包括：一導孔結構，設置於通孔中，且導孔結構不超過第一開口；一第一金屬墊，設置於第一半導體元件之第一側上，且覆蓋通孔，其中第一金屬墊鄰接導孔結構，且電性連接第一電子元件；及一第二半導體元件，與第一半導體元件垂直整合，其中第二半導體元件包括一第二電子元件，電性連接第一電子元件。
本發明提供一種封裝結構之製作方法，包括：提供一第一半導體元件，具有一第一側和相對於該第一側之第二側；形成一通孔，穿過該第一半導體元件，其中該通孔具有一第一開口和一第二開口，該第一開口鄰近該第一側，該第二開口鄰近該第二側；形成一第一金屬墊，覆蓋該第一開口；在形成該第一金屬墊之後，形成一導孔結構於該通孔中，其中該導孔結構包括導電材料且鄰接該第一金屬墊；及將該第一半導體元件大體上與該第二半導體 元件垂直整合。
100‧‧‧第一半導體元件
102‧‧‧基底
102a‧‧‧第一半導體基底
102b‧‧‧第二半導體基底
104‧‧‧緩衝層
106‧‧‧第一側
108‧‧‧第二側
110‧‧‧通道層
110a‧‧‧通道層
110b‧‧‧通道層
111‧‧‧第一開口
111b‧‧‧第一開口
112‧‧‧阻障層
112a‧‧‧阻障層
112b‧‧‧阻障層
113‧‧‧第二開口
113b‧‧‧第二開口
114‧‧‧電子元件
114a‧‧‧第一電子元件
114b‧‧‧第二電子元件
116‧‧‧閘電極
116a‧‧‧閘電極
116b‧‧‧閘電極
118‧‧‧源極電極
118a‧‧‧源極電極
118b‧‧‧源極電極
120‧‧‧汲極電極
120a‧‧‧汲極電極
120b‧‧‧汲極電極
122‧‧‧鈍化層
122a‧‧‧鈍化層
122b‧‧‧鈍化層
124‧‧‧感光層
126‧‧‧通孔
126a‧‧‧通孔
126b‧‧‧通孔
128‧‧‧絕緣層
130‧‧‧第一金屬墊
130a‧‧‧第一金屬墊
130b‧‧‧第一金屬墊
132‧‧‧導孔結構
132a‧‧‧導孔結構
132b‧‧‧導孔結構
134‧‧‧第二金屬墊
134a‧‧‧第二金屬墊
134b‧‧‧第二金屬墊
202‧‧‧第一金屬墊
204‧‧‧導孔結構
300‧‧‧第一半導體元件
302‧‧‧基底
304‧‧‧緩衝層
306‧‧‧第一側
308‧‧‧第二側
310‧‧‧通道層
311‧‧‧第二開口
312‧‧‧阻障層
313‧‧‧第一開口
314‧‧‧電子元件
316‧‧‧閘電極
318‧‧‧源極電極
320‧‧‧汲極電極
322‧‧‧鈍化層
324‧‧‧感光層
326‧‧‧通孔
328‧‧‧絕緣層
330‧‧‧第一金屬墊
332‧‧‧導孔結構
334‧‧‧第二金屬墊
400‧‧‧封裝結構
410‧‧‧內連線結構
420a‧‧‧重分配層
420b‧‧‧重分配層
430‧‧‧凸塊
430a‧‧‧凸塊
430b‧‧‧凸塊
432a‧‧‧金屬層
432b‧‧‧金屬層
510‧‧‧載板
512‧‧‧墊
520‧‧‧凸塊
600‧‧‧封裝結構
700‧‧‧封裝結構
710‧‧‧內連線結構
800‧‧‧封裝結構
900‧‧‧封裝結構
1000‧‧‧封裝結構
1100‧‧‧封裝結構
1110‧‧‧導線架
1112‧‧‧部分
1114‧‧‧部分
1116‧‧‧部分
1118‧‧‧部分
1119‧‧‧部分
1120‧‧‧夾鉗結構
1130‧‧‧引線
A‧‧‧主動層
D‧‧‧汲極電極層
G‧‧‧閘電極
K1‧‧‧第一半導體元件
K2‧‧‧第二半導體元件
S‧‧‧源電極層
S3‧‧‧第三側
S4‧‧‧第四側
第1A圖~第1F圖顯示本發明一實施例形成具有內連線結構之第一半導體元件方法中間階段的剖面圖。
第2圖顯示本發明另一實施例形成第一半導體元件之中間階段的剖面圖。
第3A圖~第3F圖顯示本發明一實施例具有內連線結構之第一半導體元件的製作方法中間階段的剖面圖。
第4A-4B圖顯示本發明一實施例形成封裝結構方法之中間階段的剖面圖。
第5圖顯示本發明一實施例形成封裝結構方法之中間階段的剖面圖。
第6圖顯示本發明一實施例封裝結構之剖面圖。
第7A-7B圖顯示本發明一實施例形成封裝結構方法之中間階段的剖面圖。
第8圖顯示本發明一實施例封裝結構的剖面圖。
第9A-9B圖顯示本發明一實施例形成封裝結構方法之中間階段的剖面圖。
第10A-10B圖顯示本發明一實施例形成封裝結構方法之中間階段的剖面圖。
第11A圖顯示本發明一實施例封裝結構之立體圖。
第11B圖顯示第11A圖封裝結構之等效電路圖。
以下詳細討論實施本發明之實施例。可以理解的是，實施例提供許多可應用的發明概念，其可以較廣的變化實施。所討論之特定實施例僅用來發明使用實施例的特定方法，而不用來限定發明的範疇。
以下配合第1A圖~第1F圖描述本發明一實施例具有內連線結構之第一半導體元件100的製作方法。首先，請參照第1A圖，提供一第一半導體元件100。第一半導體元件100包括第一側106和相對於第一側106之第二側108。第一半導體元件100包括一基底102，基底102可包括任何適合之半導體材料。例如基底可包括Si、SiC、Ge、SiGe、GaAs、InAs、InP或GaN。後續，形成一緩衝層104於基底102上。在本發明一實施例中，緩衝層104是氮化物材料，以提供後續形成於其上層良好的粘著性，且亦可解決晶格不協調的問題。然而，本發明不限定於上述材料，緩衝層104可以任何適合的材料形成。在本發明一實施例中，緩衝層104可以是氮化鋁。
後續，形成一通道層110和一阻障層112於緩衝層104上。在一實施例中，通道層110可以是GaN，阻障層112可以是AlGaN。接著，形成一第一金屬層(未繪示)於通道層110上，對第一金屬層進行微影和蝕刻之圖案化步驟，形成一源極電極118和一汲極電極120。在本發明一實施例中，第一金屬層是Ti、Al、Ni及/或Au的堆疊層。在形成第一金屬層之後，可對其進行快速熱退火之步驟。沉積一第二金屬層(未繪示)於通道層110上，且對第二金屬層進行微 影和蝕刻之圖案化步驟，以形成閘電極116。後續，形成例如氮化矽或氧化矽層之鈍化層122(passivation layer)，以保護其下的元件。
通道層110、阻障層112、閘電極116、源極電極118和汲極電極120構成鄰近第一半導體元件100之第一側106的電子元件114。本發明在一實施例中係將電子元件114設置為鄰近第一半導體元件100之第一側106，但本發明不限於此，電子元件114可設置於第一半導體元件100之第二側108。更甚者，在一實施例中，電子元件114為氮化物半導體元件，然而，本發明不將電子元件限定於氮化物半導體元件，電子元件可以為任何適合之半導體元件，例如矽基元件、III-V族元件及/或絕緣層上有矽(SOI，Silicon on Insulator)元件。
接著，請參照第1B圖，形成一感光層124於基底102和電子元件114上方。後續，請參照第1C圖，進行一微影製程，圖案化感光層124，使用圖案化之感光層124作為蝕刻罩幕，蝕刻基底102，形成穿過基底102之通孔126(via-hole)。在一實施例中，可使用雷射光束形成通孔126。
請參照第1D圖，移除光阻層124。在一實施例中，視需要地形成一絕緣層128於通孔126之側壁上，以作為保護之用途。在一實施例中，絕緣層128可以是氧化矽，其可以熱氧化法或液相沈積法(Liquid phase deposition，簡稱LPD)形成。通孔126具有鄰近第一側106之第一開口111 和鄰近第二側108之第二開口113。
請參照第1E~1F圖，形成第一金屬墊130於第一半導體元件100之第一側106上，且覆蓋通孔126之第一開口111。第一金屬墊130可電性連接電子元件114和後續步驟形成之第二金屬墊134，且可包括一凸出部分，延伸至通孔126中。在一實施例中，第一金屬墊130可包括銀膠，且可使用網印法形成。請參照第1F圖，以第一金屬墊130作為晶種層，進行一電鍍製程，成長一導電材料以填入通孔126中，而形成一導孔結構132。在一實施例中，導孔結構132和第一金屬墊130包括相同的材料，例如，導孔結構132可包括銀。在另一實施例中，導孔結構132和第一金屬墊130包括不同的材料。例如，導孔結構132可包括銅。
如第1F圖所示，由於導孔結構132係在形成第一金屬墊130之後形成，導孔結構132不延伸超過通孔126之鄰近第一半導體元件之第一側106的第一開口111，但可延伸超過通孔126之鄰近第一半導體元件之第二側108的第二開口113。後續，形成第二金屬墊134於第一半導體元件100之第二側108上。在一實施例中，第二金屬墊134可包括銀膠，且可使用網印法形成。
在第1F圖中，第一半導體元件100包括一半導體基底102和一電子元件114。第一半導體元件100具有一第一側106和相對第一側106之第二側108。至少部分的電子元件114鄰近第一側106。第一半導體元件100具有一通孔126，穿過第一半導體元件100，其中通孔126具有鄰近第一 側106之第一開口111。
一內連線結構C設置於第一半導體元件100中，其中內連線結構C包括導孔結構132和第一金屬墊130。導孔結構132設置於通孔126中，且不超出第一開口111。第一金屬墊130設置於第一半導體元件100之第一側106上，且覆蓋通孔126，其中第一金屬墊130接合導孔結構132，且電性連接電子元件114。
在本發明之一實施例中，電子元件114是高移動率電晶體(high electron mobility transistor，簡稱HEMT)，且基底102包括半導體基底。源極電極118經由導孔結構132電性連接至半導體基底。
以下以第2圖描述本發明另一實施例形成第一半導體元件之方法。第2圖之第一半導體元件的形成方法類似第1E圖~第1F圖之第一半導體元件的形成方法，為簡潔，相同的部分在此不重複描述。第2圖之第一半導體元件的形成方法與第1E圖~第1F圖之第一半導體元件的形成方法不同處在於第一金屬墊202和導孔結構204以單一步驟形成。在一實施例中，通孔126之深度不深(例如10μm~200μm)，因此可如第2圖所示，形成第一金屬墊202之網印法亦可填滿通孔126，所以可以單一網印步驟形成第一202和導孔結構204。
以下配合第3A圖~第3F圖描述本發明另一實施例第一半導體元件之製作方法。第3A圖~第3F圖與第1A圖~第1F圖之實施例不同處為在形成導孔結構前，形成墊於基 底與第一側(鄰近電子元件)相對之第二側。首先，請參照第3A圖，提供一第一半導體元件300。第一半導體元件300包括第一側306和一第二側308。第一半導體元件300包括一基底302，基底302可包括任何適合之半導體材料。例如基底302可包括Si、SiC、Ge、SiGe、GaAs、InAs、InP或GaN。後續，形成一緩衝層304於基底302上。在本發明一實施例中，在本發明一實施例中，緩衝層304可以是氮化鋁。後續，形成一通道層310和一阻障層312於緩衝層304上。在一實施例中，通道層310可以是GaN，阻障層312可以是AlGaN。接著，形成一第一金屬層(未繪示)於通道層310上，對第一金屬層進行微影和蝕刻之圖案化步驟，形成一源極電極318和一汲極電極320。在本發明一實施例中，第一金屬層是Ti、Al、Ni及/或Au的堆疊層。在形成第一金屬層之後，可對其進行快速熱退火之步驟。沉積一第二金屬層(未繪示)於通道層上，對第二金屬層進行微影和蝕刻之圖案化步驟，以形成閘電極316。後續，形成例如氮化矽或氧化矽之鈍化層322(passivation layer)，以保護其下的元件。
通道層310、阻障層312、閘電極316、源極電極318和汲極電極320構成鄰接基底302第一側306之電子元件314。在一實施例中，電子元件314為氮化物半導體元件，然而，本發明不將電子元件限定於氮化物半導體元件，電子元件可以為任何適合之半導體元件，例如矽基元件、III-V族元件及/或絕緣層上有矽(SOI)元件。
接著，請參照第3B圖，形成一感光層324於基 底302上方，以保護電子元件314。後續，請參照第3C圖，進行一微影製程，圖案化感光層324，使用圖案化之感光層324作為蝕刻罩幕，蝕刻基底302，形成穿過基底302之通孔326(via)。在一實施例中，可使用雷射光束形成通孔326。
請參照第3D圖，移除光阻層324。在一實施例中，視需要地形成一絕緣層328於通孔326之側壁上，以作為保護之用途。在一實施例中，絕緣層328可以是氧化矽，其可以熱氧化法或液相沈積法(LPD)形成。請參照第3E圖，形成第一金屬墊330於基底302之第二側308上，且覆蓋通孔326之第二開口311。在一實施例中，第一金屬墊330可包括銀膠，且可使用網印法形成。請參照第3F圖，以用第一金屬墊330作為晶種層，進行一電鍍製程，形成填入通孔326中之導孔結構332。在一實施例中，導孔結構332和第一金屬墊330包括相同的材料。在另一實施例中，導孔結構332和第一金屬墊330包括不同的材料。例如，導孔結構332可包括銅。如第3F圖所示，由於導孔結構332在形成第一金屬墊330之後形成，導孔結構332不延伸超過通孔326之鄰近基302之第二側308的第二開口311，但可延伸超過通孔326之鄰近基底302之第一側306的第一開口313。後續，形成例如銀膠之第二金屬墊334於基底302之第一側306上。
在第3F圖中，半導體元件300包括半導體基底302和電子元件314。半導體元件300具有第一側306和與第一側306相對之第二側308。至少部分的電子元件314鄰接第一側306。半導體元件300具有穿過半導體元件300之通孔 326，其中通孔326具有第一開口313和第二開口311，第一開口鄰接第一側306，第二開口311鄰接第二側308。
一內連線結構C1位於半導體元件300中，其中內連線結構包括導孔結構332和第一金屬墊330。導孔結構332設置於通孔326中，但不超過第一開口311。第一金屬墊330設置於半導體元件300之第二側308上且覆蓋通孔326，其中第一金屬墊330接合導孔結構332，且電性連接電子元件314。
以下的描述將會揭示本發明實施例採用第1F圖、第2圖和第3F圖之半導體元件的封裝結構。
第4A-4B圖顯示本發明一實施例形成封裝結構方法之中間階段的剖面圖。
值得注意的是，與第1A-3F圖單元相似或相同之第4A-4B圖的單元具有類似的材料、結構及/或製作方法。因此，上述單元的細節在此不重複描述。
請參照第4A圖，提供一第一半導體元件K1和一第二半導體元件K2。第一半導體元件K1具有一第一側106和與第一側106相對之一第二側108。第一半導體元件K1具有一第一半導體基底102a和複數個第一電子元件114a。第一半導體基底102a與第1A圖所示的基底102相同。在本實施例中，第一半導體基底102a可以是一晶粒或一晶圓。
第一電子元件114a位於第一側106。複數個通孔126a穿過第一半導體基底102a，其中各通孔126a具有一第一開口111和一第二開口113，第一開口111鄰近第一側 106，第二開口113鄰近第二側108。第一電子元件114a可以是一電晶體，且包括通道層110a、阻障層112a、閘電極116a、源極電極118a和汲極電極120a。
內連線結構410位於第一半導體基底102a中，其中各內連線結構410包括一導孔結構132a和一第一金屬墊130。特別是，導孔結構132a位於通孔126a中，而不超出第一開口111，且第一金屬墊130a係設置於第一半導體基底102a之第一側106並覆蓋通孔126a。第一金屬墊130a鄰接導孔結構132a且電性連接第一電子元件114a。在一實施例中，部分的第一金屬墊130a延伸至通孔126a。內連線結構410可更包括一第二金屬墊134a，覆蓋第二開口113且接合導孔結構132a。
特別是，可形成一重分配層420a於第一側106上，以電性連接第一金屬墊130a和第一電子元件114a。複數個凸塊430a可形成於第一金屬墊130a上，且可經由重分配層420a電性連接第一金屬墊130a和第一電子元件114a。凸塊430a包括銅、錫或其他適合的材料。可形成一凸塊下金屬層432a(under bump metallurgy，簡稱UMB)於凸塊430a和通道層110a間。形成一鈍化層122a(例如氮化矽和氧化矽)以保護其下之第一電子元件114a。
第二半導體元件K2具有一第三側S3和一相對於第三側S3之第四側S4。第二半導體元件K2包括一第二半導體基底102b(與第1A圖所示之基底102相同)和第二電子元件114b，位於第二半導體基底102b上。第二電子元件114b 鄰近第三側S3。
在本實施例中，第二半導體基底102b可以是一晶粒。第二電子元件114b可以是一電晶體且包括通道層110b、阻障層112b、閘電極116b、源極電極118b和汲極電極120b。
特別是，可形成複數個凸塊430b於第三側S3。可形成一凸塊下金屬層432b於凸塊430b和通道層110b間。形成一重分配層420b於第三側S3上，以電性連接凸塊430b和第二電子元件114b。形成一鈍化層122b(例如氮化矽和氧化矽)以保護其下之第二電子元件114b。凸塊430b包括銅、錫或其他適合的材料。
後續，請參照第4B圖，將第一半導體元件K1(或第一半導體基底102a)藉由連接凸塊430b和凸塊430a，大體上與第二半導體元件K2(或第二半導體基底102b)整合，以構成封裝結構。凸塊430b和凸塊430a之連接包括迴焊(reflow)製程。凸塊430b和凸塊430a連接以形成凸塊430。
第一電子元件114a經由重分配層420a、凸塊430和重分配層420b電性連接第二電子元件114b。第一電子元件114a和第二電子元件114b皆電性內連線結構410。
在本實施例中，第一半導體基底102a之第一側106和第二半導體基底102b之第三側S3彼此面對。換句話說，第一半導體基底102a之第一側106鄰近第二半導體基底102b之第三側S3。
在第4B圖中，形成封裝結構400，其中封裝結 構400包括第一半導體元件K1、內連線結構410和第二半導體元件K2。
第一半導體元件K1包括第一半導體基底102a和第一電子元件114a。第一半導體元件K1具有第一側106和與第一側106相對之第二側108。第一電子元件114a鄰近第一側106。第一半導體元件K1具有通孔126a，穿過第一半導體元件K1，其中各通孔126a具有第一開口111，鄰近第一側106。
內連線結構410位於第一半導體元件K1中，其中內連線結構410包括導孔結構132a和第一金屬墊130a。導孔結構132a位於通孔126a中，而不超出第一開口111。第一金屬墊130a係設置於第一半導體元件K1之第一側106並覆蓋通孔126a，其中第一金屬墊130a鄰接導孔結構132a且電性連接電子元件114a。
將第二半導體元件K2垂直整合第一半導體元件K1，其中第二半導體元件K2包括電性連接第一電子元件114a之第二電子元件114b。
值得注意的是，使用內連線結構410取代傳統的引線(未繪式)，且內連線結構410之電效能較傳統的引線佳，因此可提供封裝結構400更佳的效能。
第5圖顯示本發明一實施例形成封裝結構方法之中間階段的剖面圖。請參照第5圖，提供一載板510，其中載板510可以是印刷電路板、晶圓或晶粒。載板510具有複數個墊512位於其上。後續，將第4B圖之封裝結構400經 由凸塊520大體上與載板510垂直整合。第一電子元114a和第二電子元件114b均經由內連線結構410電性連接載板510之墊512。
第6圖顯示本發明一實施例封裝結構之剖面圖。請參照第6圖，本實施例的封裝結構600類似於第4B圖的封裝結構400，除了封裝結構600之第二半導體基底102b是晶圓。特別是，第一半導體基底102a和第二半導體基底102b均是晶圓。
第7A-7B圖顯示本發明一實施例形成封裝結構方法之中間階段的剖面圖。
值得注意的是，第7A-7B圖之方法類似於第4A-4B圖之方法，除了第7A-7B圖第二半導體元件K2(或第二半導體基底102b)相較於第4A-4B圖第二半導體元件K2(或第二半導體基底102b)是倒置。特別是，第二半導體元件K2之第三側S3(其上形成有第二電子元件114b)遠離第一電子元件K1，且第二半導體元件K2之第四側S4面對第一半導體元件K1。
請參照第7A圖，提供一第一半導體元件K1和一第二半導體元件K2，其中第一半導體元件K1具有第一半導體基底102a，第二半導體元件K2具有第二半導體基底102b。在本實施例中，第一半導體基底102a可以是晶粒或晶圓。內連線結構710設置於第二半導體元件K2中，其中各內連線結構710包括導孔結構132b和第一金屬墊130b。
特別是，導孔結構132b設置於通孔126b中，而 不超出第一開口111b，且第一金屬墊130b設置於第二半導體基底102b之第三側S3上且覆蓋通孔126b，其中第一金屬墊130b鄰接導孔結構132b，且經由重分配層420b電性連接第二電子元件114b。在一實施例中，部分的第一金屬墊130b延伸至通孔126b。內連線結構710可更包括一第二金屬墊134b，覆蓋第二開口113b，且接合導孔結構132b。凸塊430b係設置於第二金屬墊134b上，且電性連接第二金屬墊134b。
後續，請參照第7B圖，藉由將凸塊430b與凸塊430a連接，將第一半導體元件K1大體上與第二半導體元件K2整合，以構成封裝結構700。凸塊430b與凸塊430a係連接以形成凸塊430。
第一電子元件114a係經由重分配層420a、凸塊430、內連線結構710和重分配層420b電性連接第二電子元件114b。第一電子元件114a和第二電子元件114b均電性連接內連線結構410、710。
在本實施例中，第一半導體元件K1之第一側106和第二半導體元件K2之第四側S4彼此面對。換句話說，第一半導體元件K1之第一側106鄰近第二半導體元件K2之第四側S4。
第8圖顯示本發明一實施例封裝結構的剖面圖。請參照第8圖，本實施例的封裝結構800類似於第7B圖的封裝結構700，除了封裝結構700之第二半導體基底102b是晶圓。特別是，封裝結構800之第一半導體基底102a和第二半導體基底102b均是晶圓。更甚者，內連線結構410和710 可彼此對準，且凸塊430可夾設於內連線結構410和710間，且連接至兩者。
第9A-9B圖顯示本發明一實施例形成封裝結構方法之中間階段的剖面圖。
值得注意的是，與第9A-9B圖單元相似或相同之第1A-8圖的單元具有類似的材料、結構及/或製作方法。因此，上述單元的細節在此不重複描述。
值得注意的是，第9A-9B圖之方法類似於第7A-7B圖的封裝結構，除了第9A-9B圖之第二半導體元件K2包括一源極電極層S、一汲極電極層D和一夾設於兩者間之主動層A。此外，第二半導體元件K2鄰近第三側S3之第二電子元件114b是閘電極。
特別是，第二電子元件114b(亦即閘電極)穿過源電極層S，其中一絕緣層(未繪示)係設置於第二電子元件114b和源電極層S間，且設置於第二電子元件114b和主動層A間，以使第二電子元件114b與源電極層S和主動層A電性隔離。
請參照第9A圖，提供第一半導體元件K1和第二半導體元件K2，其中第一半導體元件K1具有第一半導體基底102a，第二半導體元件K2具有第二半導體基底102b。在本實施例中，第一半導體基底102a可以是晶粒或晶圓，且第二半導體基底102b可以是晶粒。將凸塊430b設置於第二半導體元件K2之第四側S4，且電性連接至汲極電極層D。
後續，請參照第9B圖，藉由連接凸塊430b和凸 塊430a將第一半導體元件K1大體上與第二半導體元件K2垂直整合，以構成封裝結構900。凸塊430b和凸塊430a係連接以形成凸塊430。
第一電子元件114a經由重分配層420a和凸塊430電性連接第二半導體元件K2。第一電子元件114a和第二半導體元件K2均電性連接內連線結構410。
在本實施例中，第一半導體元件K1之第一側106和第二半導體元件K2之第四側S4彼此面對。換句話說，第一半導體元件K1之第一側106鄰近第二半導體元件K2之第四側S4。
第10A-10B圖顯示本發明一實施例形成封裝結構方法之中間階段的剖面圖。
值得注意的是，與第10A-10B圖單元相似或相同之第1A-9B圖的單元具有類似的材料、結構及/或製作方法。因此，上述單元的細節在此不重複描述。
值得注意的是，第10A-10B圖之方法類似於第9A-9B圖的方法，除了第10A-10B圖之第一半導體元件K1相較於第9A-9B圖之第一半導體元件K1係倒置。特別是，第一半導體元件K1之第一側106(該側設置有第一電子元件114a)遠離第二半導體元件K2，且第一半導體元件K1之第二側108面向第二半導體元件K2。
請參照第10A圖，提供一第一半導體元件K1和一第二半導體元件K2，其中第一半導體元件K1具有第一半導體基底102a，第二半導體元件K2具有第二半導體基底 102b。在本實施例中，第一半導體基底102a可以是晶粒或晶圓，且第二半導體基底102b可以是晶粒。將凸塊430a設置於第二金屬墊134a上，且電性連接至第二金屬墊134a。
後續，請參照第10B圖，藉由連接凸塊430b和凸塊430a將第一半導體元件K1大體上與第二半導體元件K2垂直整合，以構成封裝結構1000。凸塊430b和凸塊430a係連接以形成凸塊430。
第一電子元件114a經由重分配層420a、內連線結構410和凸塊430電性連接第二半導體元件K2。第一電子元件114a和第二半導體元K2均電性連接內連線結構410。
在本實施例中，第一半導體元件K1之第二側108和第二半導體元件K2之第四側S4彼此面對。換句話說，第一半導體元件K1之第二側108鄰近第二半導體元件K2之第四側S4。
值得注意的是，在上述實施例中，為示範性的說明，第一電子元件114a和第一金屬墊130a形成在相同側(亦即第一側)，但其不用來限制本發明。在其他的實施例中(例如第3F圖之實施例)，第一電子元件314和第一金屬墊330形成在不同側。例如，第一電子元件314和第一金屬墊330可分別形成在側306和側308。此外，鈍化層322可形成在側306上，以保護其下之第一電子元件314。
第11A圖顯示本發明一實施例封裝結構之立體圖。第11B圖為第11A圖封裝結構之等效電路圖。
值得注意的是，第11A圖之封裝結構1100類似 於第10B圖的封裝結構1000，除了第11A圖之封裝結構1100更包括導線架1110。
特別是，如第11A圖和第11B圖所示，第一半導體元件K1包括具有氮化物半導體材料之HEMT元件，第二半導體元件K2包括具有氮化物半導體材料之垂直電晶體。第一和第二半導體元件K1、K2堆疊於導線架1110上。
導線架1110具有許多彼此分隔之部分1112、1114、1116、1118和1119。第一半導體元件K1設置於第一電子元件114a上。在此實施例中，第一電子元件114a是HEMT元件，設置於第一半導體元件K1之主動區上。第一半導體元件K1更包括一鈍化層，覆蓋部分的主動區、閘電極116a、源極電極118a和汲極電極120a。汲極電極120a設至於部分1112上，且電性連接部分1112。閘電極116a設至於部分1114上，且電性連接部分1114。源極電極118a設至於部分1116上，且電性連接部分1116。部分1112或部分1114可選擇性的覆蓋部分鈍化層，以依產品設計的需要增加場板效應(field plate effect)。
內連線結構410係設置於第一半導體基底102a中。第二半導體元件K2係設置於第一半導體元件K1上。第二半導體元件K2包括第二電子元件114b。在此實施例中，第二電子元件114b是一垂直電晶體，包括源極電極S、閘電極G和汲極電極D，其中第二電子元件114b之汲極電極D經由內連線結構410電性連接第一電子元件114a之源極電極S。源極電極S經由夾鉗結構1120(例如金屬片)電性連接部 分1118。特別是，第二電子元件114b之源極電極S經由夾鉗結構1120和導線架1110中的導電路徑(未繪示)電性連接第一電子元件114a之閘電極116a。閘電極116a經由兩者間的接合引線1130電性連接部分1119。
根據上述，本發明使用內連線結構取代傳統的引線，內連線結構相較於傳統的引線具有較佳的電效能，使得封裝結構有較好的表現。此外，本發明形成內連線結構之方法再電鍍時使用第一金屬墊作為晶種層，而不需要使用真空設備。因此，本發明之方法可以較低的成本製作半導體元件。
雖然本發明之較佳實施例說明如上，然其並非用以限定本發明，任何熟習此領域技術者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
A‧‧‧主動層
D‧‧‧汲極電極層
G‧‧‧閘電極
K1‧‧‧第一半導體元件
K2‧‧‧第二半導體元件
S‧‧‧源電極層
102a‧‧‧第一半導體基底
114a‧‧‧第一電子元件
114b‧‧‧第二電子元件
116a‧‧‧閘電極
118a‧‧‧源極電極
120a‧‧‧汲極電極
410‧‧‧內連線結構
1100‧‧‧封裝結構
1110‧‧‧導線架
1112‧‧‧部分
1114‧‧‧部分
1116‧‧‧部分
1118‧‧‧部分
1119‧‧‧部分
1120‧‧‧夾鉗結構
1130‧‧‧引線

Claims (20)

  1. 一種封裝結構，包括：一第一半導體元件，包括一第一半導體基底和一第一電子元件，該第一半導體元件具有一第一側和相對該第一側之第二側，其中至少部分該第一電子元件鄰近該第一側，且其中該第一半導體元件具有一通孔，穿過該第一半導體元件，其中該通孔具有一第一開口，鄰近該第一側；一內連線結構，設置於該第一半導體元件中，其中該內連線結構包括：一導孔結構，設置於該通孔中，且該導孔結構不超過該第一開口；一第一金屬墊，設置於該第一半導體元件之該第一側上，且覆蓋該通孔，其中該第一金屬墊鄰接該導孔結構，且電性連接該第一電子元件；及一第二半導體元件，與該第一半導體元件垂直整合，其中該第二半導體元件包括一第二電子元件，電性連接該第一電子元件。
  2. 如申請專利範圍第1項所述之封裝結構，其中該第一半導體基底包括一晶粒或一晶圓，且該第二半導體元件包括一第二半導體基底，其中該第二半導體基底包括一晶粒或一晶圓。
  3. 如申請專利範圍第1項所述之封裝結構，其中該第二半導體元件具有一第三側和與該第三側相對之第四側，且其中該第二半導體元件包括第二半導體基底，鄰近該第四 側，且至少部分該第二電子元件鄰近該第三側。
  4. 如申請專利範圍第3項所述之封裝結構，其中該第一半導體元件之第一側和該第二半導體元件之第三側彼此面對。
  5. 如申請專利範圍第3項所述之封裝結構，其中該第一半導體元件之第二側和該第二半導體元件之第三側彼此面對。
  6. 如申請專利範圍第3項所述之封裝結構，其中該第一半導體元件之第一側和該第二半導體元件之第四側彼此面對。
  7. 如申請專利範圍第3項所述之封裝結構，其中該第一半導體元件之第二側和該第二半導體元件之第四側彼此面對。
  8. 如申請專利範圍第1項所述之封裝結構，其中該第一電子元件和該第二電子元件之至少一者是電晶體。
  9. 如申請專利範圍第1項所述之封裝結構，更包括：一載板，其中該第一半導體元件和該第二半導體元件係堆疊於該載板上；且該第一電子元件和該第二電子元件經由該內連線結構電性連接該載板。
  10. 如申請專利範圍第1項所述之封裝結構，其中該第一金屬墊之一部分延深入該通孔中。
  11. 一種封裝結構之製作方法，包括：提供一第一半導體元件，具有一第一側和相對於該第一側之第二側； 形成一通孔，穿過該第一半導體元件，其中該通孔具有一第一開口和一第二開口，該第一開口鄰近該第一側，該第二開口鄰近該第二側；形成一第一金屬墊，覆蓋該第一開口；在形成該第一金屬墊之後，形成一導孔結構於該通孔中，其中該導孔結構包括導電材料且鄰接該第一金屬墊；及將該第一半導體元件大體上與該第二半導體元件垂直整合。
  12. 如申請專利範圍第11項所述之封裝結構之製作方法，更包括：形成一第二金屬墊，覆蓋該第二開口，且鄰接該導孔結構。
  13. 如申請專利範圍第11項所述之封裝結構之製作方法，其中該第一半導體元件包括：一第一半導體基底；一第一電子元件，設置於該第一半導體基底上，至少部分該第一電子元件鄰近該第一半導體元件之該第一側；及一鈍化層，設置於該第一半導體基底和該第一電子元件上。
  14. 如申請專利範圍第13項所述之封裝結構之製作方法，其中該第二半導體元件具有一第三側和相對該第三側之第四側，且該第二半導體元件包括一第二半導體基底和 一二電子元件，設置於該第二半導體基底上，至少部分該第二電子元件鄰近該第三側。
  15. 如申請專利範圍第14項所述之封裝結構之製作方法，其中該第一半導體元件垂直整合該第二半導體元件，且該第一半導體元件之第一側與該第二半導體元件之第三側彼此面對。
  16. 如申請專利範圍第14項所述之封裝結構之製作方法，其中該第一半導體元件垂直整合該第二半導體元件，且該第一半導體元件之第二側與該第二半導體元件之第三側彼此面對。
  17. 如申請專利範圍第14項所述之封裝結構之製作方法，其中該第一半導體元件垂直整合該第二半導體元件，且該第一半導體元件之第二側與該第二半導體元件之第四側彼此面對。
  18. 如申請專利範圍第14項所述之封裝結構之製作方法，其中該第一半導體元件垂直整合該第二半導體元件，而該第一半導體元件之第一側與該第二半導體元件之第四側彼此面對。
  19. 如申請專利範圍第11項所述之封裝結構之製作方法，其中形成該第一金屬墊之步驟包括進行一網印製程，形成該第一金屬墊，覆蓋該第一開口。
  20. 如申請專利範圍第11項所述之封裝結構之製作方法，其中該第一半導體元件包括：一第一半導體基底； 一第一電子元件，設置於該第一半導體基底上，且至少部分該第一電子元件鄰近該第一半導體元件之該第二側；及一鈍化層，設置於該第一半導體基底和該第一電子元件上。
TW102137865A 2012-11-13 2013-10-21 封裝結構和其製作方法 TWI532130B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/675,297 US9159699B2 (en) 2012-11-13 2012-11-13 Interconnection structure having a via structure

Publications (2)

Publication Number Publication Date
TW201419470A true TW201419470A (zh) 2014-05-16
TWI532130B TWI532130B (zh) 2016-05-01

Family

ID=49510038

Family Applications (2)

Application Number Title Priority Date Filing Date
TW102137865A TWI532130B (zh) 2012-11-13 2013-10-21 封裝結構和其製作方法
TW102137864A TWI515859B (zh) 2012-11-13 2013-10-21 內連線結構和其製作方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW102137864A TWI515859B (zh) 2012-11-13 2013-10-21 內連線結構和其製作方法

Country Status (4)

Country Link
US (2) US9159699B2 (zh)
EP (2) EP2731133A3 (zh)
CN (3) CN110085563A (zh)
TW (2) TWI532130B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI813100B (zh) * 2021-12-17 2023-08-21 世界先進積體電路股份有限公司 半導體結構與其製造方法

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140073163A (ko) * 2012-12-06 2014-06-16 삼성전자주식회사 반도체 장치 및 그의 형성방법
US9659851B2 (en) * 2014-02-07 2017-05-23 Marvell World Trade Ltd. Method and apparatus for improving the reliability of a connection to a via in a substrate
FR3028095B1 (fr) 2014-11-04 2018-01-26 Commissariat A L'energie Atomique Et Aux Energies Alternatives Dispositif electronique de puissance a cellule de commutation 3d verticale
KR20170011366A (ko) * 2015-07-22 2017-02-02 삼성전자주식회사 반도체 칩 및 이를 가지는 반도체 패키지
CN109671773B (zh) * 2017-10-16 2020-05-05 苏州能讯高能半导体有限公司 半导体器件及其制造方法
US10366982B2 (en) 2017-11-30 2019-07-30 Taiwan Semiconductor Manufacturing Co., Ltd. Structure with embedded memory device and contact isolation scheme
DE112018007009T5 (de) * 2018-02-01 2020-11-05 Mitsubishi Electric Corporation Halbleitervorrichtung und Herstellungsverfahren für diese
US11004794B2 (en) * 2018-06-27 2021-05-11 Taiwan Semiconductor Manufacturing Co., Ltd. Partial barrier free vias for cobalt-based interconnects and methods of fabrication thereof
CN109300947B (zh) * 2018-09-28 2021-09-07 京东方科技集团股份有限公司 柔性显示基板及其制造方法、显示装置
EP3783663A1 (en) 2019-08-21 2021-02-24 Infineon Technologies AG Semiconductor device and method
FR3122036A1 (fr) * 2021-04-14 2022-10-21 Exagan Dispositif bidirectionnel pourvu d’un empilement de deux transistors a haute mobilite electronique connectes tete-beche
WO2022236712A1 (en) * 2021-05-11 2022-11-17 Innoscience (suzhou) Semiconductor Co., Ltd. Integrated semiconductor device and method for manufacturing the same

Family Cites Families (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5447871A (en) * 1993-03-05 1995-09-05 Goldstein; Edward F. Electrically conductive interconnection through a body of semiconductor material
US6620731B1 (en) 1997-12-18 2003-09-16 Micron Technology, Inc. Method for fabricating semiconductor components and interconnects with contacts on opposing sides
TWI244571B (en) * 2002-01-30 2005-12-01 Sanyo Electric Co Semiconductor display device
WO2003071843A1 (fr) * 2002-02-22 2003-08-28 Fujikura Ltd. Tableau de connexions multicouche, base pour tableau de connexions multicouche, tableau de connexions imprime et son procede de production
US7045861B2 (en) * 2002-03-26 2006-05-16 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device, liquid-crystal display device and method for manufacturing same
JP2004095849A (ja) * 2002-08-30 2004-03-25 Fujikura Ltd 貫通電極付き半導体基板の製造方法、貫通電極付き半導体デバイスの製造方法
JP3937993B2 (ja) * 2002-10-02 2007-06-27 日立電線株式会社 配線板の製造方法
US6828512B2 (en) * 2002-10-08 2004-12-07 Intel Corporation Apparatus and methods for interconnecting components to via-in-pad interconnects
JP2004146748A (ja) * 2002-10-28 2004-05-20 Alps Electric Co Ltd 薄膜キャパシタ素子
WO2004082036A1 (ja) * 2003-03-10 2004-09-23 Toyoda Gosei Co., Ltd. 固体素子デバイスおよびその製造方法
US6897148B2 (en) * 2003-04-09 2005-05-24 Tru-Si Technologies, Inc. Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby
JP3891299B2 (ja) * 2003-05-06 2007-03-14 セイコーエプソン株式会社 半導体装置の製造方法、半導体装置、半導体デバイス、電子機器
GB0311251D0 (en) * 2003-05-16 2003-06-18 Koninkl Philips Electronics Nv Method of manufacture recyclable electronic products and electronic products obtained by the method
US7919787B2 (en) * 2003-06-27 2011-04-05 Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. Semiconductor device with a light emitting semiconductor die
KR100493063B1 (ko) * 2003-07-18 2005-06-02 삼성전자주식회사 스택 반도체 칩 비지에이 패키지 및 그 제조방법
US8084866B2 (en) * 2003-12-10 2011-12-27 Micron Technology, Inc. Microelectronic devices and methods for filling vias in microelectronic devices
JP2005303258A (ja) * 2004-03-16 2005-10-27 Fujikura Ltd デバイス及びその製造方法
JP4327644B2 (ja) * 2004-03-31 2009-09-09 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
US7498647B2 (en) * 2004-06-10 2009-03-03 Micron Technology, Inc. Packaged microelectronic imagers and methods of packaging microelectronic imagers
KR100594716B1 (ko) * 2004-07-27 2006-06-30 삼성전자주식회사 공동부를 구비한 캡 웨이퍼, 이를 이용한 반도체 칩, 및그 제조방법
JP4803993B2 (ja) * 2004-11-09 2011-10-26 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US7476918B2 (en) * 2004-11-22 2009-01-13 Panasonic Corporation Semiconductor integrated circuit device and vehicle-mounted radar system using the same
EP1920459A4 (en) * 2005-08-12 2012-07-25 Semiconductor Energy Lab PROCESS FOR PRODUCING A SEMICONDUCTOR COMPONENT
JP4758712B2 (ja) * 2005-08-29 2011-08-31 新光電気工業株式会社 半導体装置の製造方法
US7772116B2 (en) * 2005-09-01 2010-08-10 Micron Technology, Inc. Methods of forming blind wafer interconnects
KR100704915B1 (ko) * 2005-09-15 2007-04-09 삼성전기주식회사 미세 패턴을 가지는 인쇄회로기판 및 그 제조방법
US7633167B2 (en) * 2005-09-29 2009-12-15 Nec Electronics Corporation Semiconductor device and method for manufacturing same
TW200733336A (en) * 2006-02-17 2007-09-01 Advanced Semiconductor Eng Ball grid array package structure with identification marks and substrate thereof
US7741218B2 (en) * 2007-02-27 2010-06-22 Freescale Semiconductor, Inc. Conductive via formation utilizing electroplating
JP2008305938A (ja) * 2007-06-07 2008-12-18 Toshiba Corp 半導体装置および半導体装置の製造方法
WO2009023462A1 (en) * 2007-08-10 2009-02-19 Spansion Llc Semiconductor device and method for manufacturing thereof
JP2009070966A (ja) * 2007-09-12 2009-04-02 Toshiba Corp 半導体装置とその製造方法
JP5536322B2 (ja) * 2007-10-09 2014-07-02 新光電気工業株式会社 基板の製造方法
US8779570B2 (en) * 2008-03-19 2014-07-15 Stats Chippac Ltd. Stackable integrated circuit package system
US20120126419A1 (en) * 2008-07-24 2012-05-24 Vaidyanathan Kripesh Substrate Arrangement and a Method of Manufacturing a Substrate Arrangement
US7843072B1 (en) 2008-08-12 2010-11-30 Amkor Technology, Inc. Semiconductor package having through holes
KR101002680B1 (ko) * 2008-10-21 2010-12-21 삼성전기주식회사 반도체 패키지 및 그 제조 방법
JP2010103236A (ja) * 2008-10-22 2010-05-06 Panasonic Corp 窒化物半導体装置
JP5268618B2 (ja) * 2008-12-18 2013-08-21 株式会社東芝 半導体装置
JP5308145B2 (ja) * 2008-12-19 2013-10-09 ルネサスエレクトロニクス株式会社 半導体装置
JP5471268B2 (ja) * 2008-12-26 2014-04-16 大日本印刷株式会社 貫通電極基板及びその製造方法
US7932608B2 (en) * 2009-02-24 2011-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via formed with a post passivation interconnect structure
KR101573934B1 (ko) * 2009-03-02 2015-12-11 엘지전자 주식회사 태양 전지 및 그 제조 방법
US8329578B2 (en) * 2009-03-27 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Via structure and via etching process of forming the same
CN101847597B (zh) * 2009-03-27 2013-12-04 台湾积体电路制造股份有限公司 集成电路结构
CN102185580A (zh) * 2010-01-18 2011-09-14 精工爱普生株式会社 电子装置、基板的制造方法以及电子装置的制造方法
US8518746B2 (en) * 2010-09-02 2013-08-27 Stats Chippac, Ltd. Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die
KR101688006B1 (ko) * 2010-11-26 2016-12-20 삼성전자주식회사 반도체 장치
US20120146111A1 (en) * 2010-12-14 2012-06-14 Shu-Ming Chang Chip package and manufacturing method thereof
CN102569144B (zh) * 2010-12-22 2015-05-13 中芯国际集成电路制造(上海)有限公司 一种通孔刻蚀方法
KR20120071921A (ko) * 2010-12-23 2012-07-03 한국전자통신연구원 실리콘 관통 홀(ｔｓｖ) 충진용 조성물, ｔｓｖ 충진방법 및 상기 조성물을 이용하여 형성된 ｔｓｖ 충진물을 포함하는 기판
JP5595524B2 (ja) * 2010-12-28 2014-09-24 京セラ株式会社 光モジュールおよび光配線基板
KR101801137B1 (ko) * 2011-02-21 2017-11-24 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR101780423B1 (ko) * 2011-03-18 2017-09-22 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US8546900B2 (en) * 2011-06-09 2013-10-01 Optiz, Inc. 3D integration microelectronic assembly for integrated circuit devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI813100B (zh) * 2021-12-17 2023-08-21 世界先進積體電路股份有限公司 半導體結構與其製造方法

Also Published As

Publication number Publication date
US9159699B2 (en) 2015-10-13
US20150294910A1 (en) 2015-10-15
CN103811461A (zh) 2014-05-21
EP2731133A2 (en) 2014-05-14
EP2731133A3 (en) 2017-11-01
CN103811465B (zh) 2019-07-16
TWI515859B (zh) 2016-01-01
CN110085563A (zh) 2019-08-02
EP2731132A3 (en) 2017-05-17
US10424508B2 (en) 2019-09-24
TWI532130B (zh) 2016-05-01
CN103811465A (zh) 2014-05-21
TW201419487A (zh) 2014-05-16
EP2731132A2 (en) 2014-05-14
US20140131871A1 (en) 2014-05-15

Similar Documents

Publication Publication Date Title
TWI532130B (zh) 封裝結構和其製作方法
US10867957B2 (en) Mechanisms for forming hybrid bonding structures with elongated bumps
US10141280B2 (en) Mechanisms for forming package structure
US10157885B2 (en) Package structure having magnetic bonding between substrates
US10014218B1 (en) Method for forming semiconductor device structure with bumps
JP6076020B2 (ja) 半導体装置及び半導体装置の製造方法
KR20090002644A (ko) 관통전극을 구비하는 반도체 장치 및 이를 제조하는 방법
US10879161B2 (en) Semiconductor packages having a seed layer structure protruding from an edge of metal structure
US9768135B2 (en) Semiconductor device having conductive bump with improved reliability
US20170040298A1 (en) Package-on-Package Method
KR102634695B1 (ko) 링 구조물을 갖는 칩 패키지 구조물 및 이의 형성 방법
CN105470235A (zh) 中介板及其制法
US9275982B2 (en) Method of forming interconnection structure of package structure
US20240363589A1 (en) Method of fabricating stacked die structure
US20240120277A1 (en) Chip structure
TWI599007B (zh) 電子單體及其製法
JP6018672B1 (ja) 半導体装置とその製造方法
JP2007073826A (ja) ３次元半導体集積回路装置、その製造方法、それを用いたパッケージ化３次元半導体集積回路装置及びその実装方法。
US9570430B2 (en) Articles including bonded metal structures and methods of preparing the same
JP2013239756A (ja) 半導体装置