CN103811465A - 封装结构和其制作方法 - Google Patents

封装结构和其制作方法 Download PDF

Info

Publication number
CN103811465A
CN103811465A CN201310552017.3A CN201310552017A CN103811465A CN 103811465 A CN103811465 A CN 103811465A CN 201310552017 A CN201310552017 A CN 201310552017A CN 103811465 A CN103811465 A CN 103811465A
Authority
CN
China
Prior art keywords
semiconductor element
electronic component
semiconductor
hole
metal gasket
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201310552017.3A
Other languages
English (en)
Other versions
CN103811465B (zh
Inventor
李嘉炎
蔡欣昌
李芃昕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anchorage Semiconductor Co ltd
Original Assignee
Delta Optoelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Delta Optoelectronics Inc filed Critical Delta Optoelectronics Inc
Publication of CN103811465A publication Critical patent/CN103811465A/zh
Application granted granted Critical
Publication of CN103811465B publication Critical patent/CN103811465B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/033—Manufacturing methods by local deposition of the material of the bonding area
    • H01L2224/0331—Manufacturing methods by local deposition of the material of the bonding area in liquid form
    • H01L2224/0332—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16147—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16148—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73255—Bump and strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明公开了一种封装结构和其制作方法，封装结构包括：一第一半导体元件，包括一第一半导体基底和一第一电子元件，第一半导体元件具有一第一侧和相对第一侧的第二侧，其中至少部分第一电子元件邻近第一侧，且其中第一半导体元件具有一通孔，穿过第一半导体元件，其中通孔具有一第一开口，邻近第一侧；一内连线结构，设置于第一半导体元件中，其中内连线结构包括：一导孔结构，设置于通孔中，且导孔结构不超过第一开口；一第一金属垫，设置于第一半导体元件的第一侧上，且覆盖通孔，其中第一金属垫邻接导孔结构，且电性连接第一电子元件；及一第二半导体元件，与第一半导体元件垂直整合，其中第二半导体元件包括一第二电子元件，电性连接第一电子元件。

Description

封装结构和其制作方法
技术领域
本发明有关于一种半导体元件，特别是有关于一种封装结构和其制作方法。
背景技术
半导体构件包括外部连接，使得电连接可从外部连接至半导体构件中的集成电路。例如，一半导体晶粒包括形成在晶粒表面的接合垫图案，而晶片尺寸封装(chip scale package)的半导体封装体亦包括外部连接。一般来说，构件在其表面侧(电路侧)或背面侧包括外部连接，且构件有时于表面侧和背面侧均需有外部连接。
在半导体技术中，穿基底导孔(through substrate via)是形成在半导体基底(晶片或晶粒)中的导电图样，以电性连接基底两侧的外部连接。TSV垂直穿过半导体基底，提供堆叠的晶片/晶粒的封装方法，使得分隔晶片或晶粒的电路间可形成电性连接。形成TSV的方法包括许多种，一般来说，其包括对半导体基底进行蚀刻，形成孔洞，且孔洞有时可穿过内连线结构。孔洞中可包括绝缘层及/或金属层。孔洞后续填入一般为铜的导电材料，形成TSV的主要部分。
传统的技术使用电镀法形成填入TSV孔洞中的导电填充材料，而电镀技术的晶种层(seed layer)使用如物理或化学气相沉积的真空技术在填入导电填充材料之前形成。然而，真空技术为高价的设备，因此增加元件的成本。
发明内容
本发明的目的在于提供一种封装结构，用以解决上述的问题或其他问题。
根据上述，本发明提供一种封装结构，包括：一第一半导体元件，包括一第一半导体基底和一第一电子元件，第一半导体元件具有一第一侧和相对第一侧的第二侧，其中至少部分第一电子元件邻近第一侧，且其中第一半导体元件具有一通孔，穿过第一半导体元件，其中通孔具有一第一开口，邻近第一侧；一内连线结构，设置于第一半导体元件中，其中内连线结构包括：一导孔结构，设置于通孔中，且导孔结构不超过第一开口；一第一金属垫，设置于第一半导体元件的第一侧上，且覆盖通孔，其中第一金属垫邻接导孔结构，且电性连接第一电子元件；及
一第二半导体元件，与第一半导体元件垂直整合，其中第二半导体元件包括一第二电子元件，电性连接第一电子元件。
本发明提供一种封装结构的制作方法，包括：提供一第一半导体元件，具有一第一侧和相对于该第一侧的第二侧；形成一通孔，穿过该第一半导体元件，其中该通孔具有一第一开口和一第二开口，该第一开口邻近该第一侧，该第二开口邻近该第二侧；形成一第一金属垫，覆盖该第一开口；在形成该第一金属垫之后，形成一导孔结构于该通孔中，其中该导孔结构包括导电材料且邻接该第一金属垫；及将该第一半导体元件大体上与该第二半导体元件垂直整合。
附图说明
图1A～图1F显示本发明一实施例形成具有内连线结构的第一半导体元件方法中间阶段的剖面图。
图2显示本发明另一实施例形成第一半导体元件的中间阶段的剖面图。
图3A～图3F显示本发明一实施例具有内连线结构的第一半导体元件的制作方法中间阶段的剖面图。
图4A-4B显示本发明一实施例形成封装结构方法的中间阶段的剖面图。
图5显示本发明一实施例形成封装结构方法的中间阶段的剖面图。
图6显示本发明一实施例封装结构的剖面图。
图7A-7B显示本发明一实施例形成封装结构方法的中间阶段的剖面图。
图8显示本发明一实施例封装结构的剖面图。
图9A-9B显示本发明一实施例形成封装结构方法的中间阶段的剖面图。
图10A-10B显示本发明一实施例形成封装结构方法的中间阶段的剖面图。
图11A显示本发明一实施例封装结构的立体图。图11B显示图11A封装结构的等效电路图。
其中，附图标记说明如下：
100～第一半导体元件；   102～基底；
102a～第一半导体基底；   102b～第二半导体基底；
104～缓冲层；   106～第一侧；
108～第二侧；   110～通道层；
110a～通道层；   110b～通道层；
111～第一开口；   111b～第一开口；
112～阻障层；   112a～阻障层；
112b～阻障层；   113～第二开口；
113b～第二开口；   114～电子元件；
114a～第一电子元件；   114b～第二电子元件；
116～栅电极；   116a～栅电极；
116b～栅电极；   118～源极电极；
118a～源极电极；   118b～源极电极；
120～漏极电极；   120a～漏极电极；
120b～漏极电极；   122～钝化层；
122a～钝化层；   122b～钝化层；
124～感光层；   126～通孔；
126a～通孔；   126b～通孔；
128～绝缘层；   130～第一金属垫；
130a～第一金属垫；   130b～第一金属垫；
132～导孔结构；   132a～导孔结构；
132b～导孔结构；   134～第二金属垫；
134a～第二金属垫；   134b～第二金属垫；
202～第一金属垫；   204～导孔结构；
300～第一半导体元件；   302～基底；
304～缓冲层；   306～第一侧；
308～第二侧；   310～通道层；
311～第二开口；   312～阻障层；
313～第一开口；   314～电子元件；
316～栅电极；   318～源极电极；
320～漏极电极；   322～钝化层；
324～感光层；   326～通孔；
328～绝缘层；   330～第一金属垫；
332～导孔结构；   334～第二金属垫；
400～封装结构；   410～内连线结构；
420a～重分配层；   420b～重分配层；
430～凸块；   430a～凸块；
430b～凸块；   432a～金属层；
432b～金属层；   510～载板；
512～垫；   520～凸块；
600～封装结构；   700～封装结构；
710～内连线结构；   800～封装结构；
900～封装结构；   1000～封装结构；
1100～封装结构；   1110～导线架；
1112～部分；   1114～部分；
1116～部分；   1118～部分；
1119～部分；   1120～夹钳结构；
1130～引线；   A～主动层；
D～漏极电极层；   G～栅电极；
K1～第一半导体元件；   K2～第二半导体元件；
S～源电极层；   S3～第三侧；
S4～第四侧。
具体实施方式
以下详细讨论实施本发明的实施例。可以理解的是，实施例提供许多可应用的发明概念，其可以较广的变化实施。所讨论的特定实施例仅用来发明使用实施例的特定方法，而不用来限定发明的范畴。
以下配合图1A～图1F描述本发明一实施例具有内连线结构的第一半导体元件100的制作方法。首先，请参照图1A，提供一第一半导体元件100。第一半导体元件100包括第一侧106和相对于第一侧106的第二侧108。第一半导体元件100包括一基底102，基底102可包括任何适合的半导体材料。例如基底可包括Si、SiC、Ge、SiGe、GaAs、InAs、InP或GaN。后续，形成一缓冲层104于基底102上。在本发明一实施例中，缓冲层104是氮化物材料，以提供后续形成于其上层良好的粘着性，且亦可解决晶格不协调的问题。然而，本发明不限定于上述材料，缓冲层104可以任何适合的材料形成。在本发明一实施例中，缓冲层104可以是氮化铝。
后续，形成一通道层110和一阻障层112于缓冲层104上。在一实施例中，通道层110可以是GaN，阻障层112可以是AlGaN。接着，形成一第一金属层(未绘示)于通道层110上，对第一金属层进行微影和蚀刻的图案化步骤，形成一源极电极118和一漏极电极120。在本发明一实施例中，第一金属层是Ti、Al、Ni及/或Au的堆叠层。在形成第一金属层之后，可对其进行快速热退火的步骤。沉积一第二金属层(未绘示)于通道层110上，且对第二金属层进行微影和蚀刻的图案化步骤，以形成栅电极116。后续，形成例如氮化硅或氧化硅层的钝化层122(passivation layer)，以保护其下的元件。
通道层110、阻障层112、栅电极116、源极电极118和漏极电极120构成邻近第一半导体元件100的第一侧106的电子元件114。本发明在一实施例中将电子元件114设置为邻近第一半导体元件100的第一侧106，但本发明不限于此，电子元件114可设置于第一半导体元件100的第二侧108。更甚者，在一实施例中，电子元件114为氮化物半导体元件，然而，本发明不将电子元件限定于氮化物半导体元件，电子元件可以为任何适合的半导体元件，例如硅基元件、III-V族元件及/或绝缘层上有硅(SOI，Silicon on Insulator)元件。
接着，请参照图1B，形成一感光层124于基底102和电子元件114上方。后续，请参照图1C，进行一微影工艺，图案化感光层124，使用图案化的感光层124作为蚀刻罩幕，蚀刻基底102，形成穿过基底102的通孔126(via-hole)。在一实施例中，可使用雷射光束形成通孔126。
请参照图1D，移除光阻层124。在一实施例中，视需要地形成一绝缘层128于通孔126的侧壁上，以作为保护的用途。在一实施例中，绝缘层128可以是氧化硅，其可以热氧化法或液相沈积法(Liquid phase deposition，简称LPD)形成。通孔126具有邻近第一侧106的第一开口111和邻近第二侧108的第二开口113。
请参照图1E～1F，形成第一金属垫130于第一半导体元件100的第一侧106上，且覆盖通孔126的第一开口111。第一金属垫130可电性连接电子元件114和后续步骤形成的第二金属垫134，且可包括一凸出部分，延伸至通孔126中。在一实施例中，第一金属垫130可包括银胶，且可使用网印法形成。请参照图1F，以第一金属垫130作为晶种层，进行一电镀工艺，成长一导电材料以填入通孔126中，而形成一导孔结构132。在一实施例中，导孔结构132和第一金属垫130包括相同的材料，例如，导孔结构132可包括银。在另一实施例中，导孔结构132和第一金属垫130包括不同的材料。例如，导孔结构132可包括铜。
如图1F所示，由于导孔结构132在形成第一金属垫130之后形成，导孔结构132不延伸超过通孔126的邻近第一半导体元件的第一侧106的第一开口111，但可延伸超过通孔126的邻近第一半导体元件的第二侧108的第二开口113。后续，形成第二金属垫134于第一半导体元件100的第二侧108上。在一实施例中，第二金属垫134可包括银胶，且可使用网印法形成。
在图1F中，第一半导体元件100包括一半导体基底102和一电子元件114。第一半导体元件100具有一第一侧106和相对第一侧106的第二侧108。至少部分的电子元件114邻近第一侧106。第一半导体元件100具有一通孔126，穿过第一半导体元件100，其中通孔126具有邻近第一侧106的第一开口111。
一内连线结构C设置于第一半导体元件100中，其中内连线结构C包括导孔结构132和第一金属垫130。导孔结构132设置于通孔126中，且不超出第一开口111。第一金属垫130设置于第一半导体元件100的第一侧106上，且覆盖通孔126，其中第一金属垫130接合导孔结构132，且电性连接电子元件114。
在本发明的一实施例中，电子元件114是高移动率晶体管(high electronmobility transistor，简称HEMT)，且基底102包括半导体基底。源极电极118经由导孔结构132电性连接至半导体基底。
以下以图2描述本发明另一实施例形成第一半导体元件的方法。图2的第一半导体元件的形成方法类似图1E～图1F的第一半导体元件的形成方法，为简洁，相同的部分在此不重复描述。图2的第一半导体元件的形成方法与图1E～图1F的第一半导体元件的形成方法不同处在于第一金属垫202和导孔结构204以单一步骤形成。在一实施例中，通孔126的深度不深(例如10μm～200μm)，因此可如图2所示，形成第一金属垫202的网印法亦可填满通孔126，所以可以单一网印步骤形成第一202和导孔结构204。
以下配合图3A～图3F描述本发明另一实施例第一半导体元件的制作方法。图3A～图3F与图1A～图1F的实施例不同处为在形成导孔结构前，形成垫于基底与第一侧(邻近电子元件)相对的第二侧。首先，请参照图3A，提供一第一半导体元件300。第一半导体元件300包括第一侧306和一第二侧308。第一半导体元件300包括一基底302，基底302可包括任何适合的半导体材料。例如基底302可包括Si、SiC、Ge、SiGe、GaAs、InAs、InP或GaN。后续，形成一缓冲层304于基底302上。在本发明一实施例中，在本发明一实施例中，缓冲层304可以是氮化铝。后续，形成一通道层310和一阻障层312于缓冲层304上。在一实施例中，通道层310可以是GaN，阻障层312可以是AlGaN。接着，形成一第一金属层(未绘示)于通道层310上，对第一金属层进行微影和蚀刻的图案化步骤，形成一源极电极318和一漏极电极320。在本发明一实施例中，第一金属层是Ti、Al、Ni及/或Au的堆叠层。在形成第一金属层之后，可对其进行快速热退火的步骤。沉积一第二金属层(未绘示)于通道层上，对第二金属层进行微影和蚀刻的图案化步骤，以形成栅电极316。后续，形成例如氮化硅或氧化硅的钝化层322(passivation layer)，以保护其下的元件。
通道层310、阻障层312、栅电极316、源极电极318和漏极电极320构成邻接基底302第一侧306的电子元件314。在一实施例中，电子元件314为氮化物半导体元件，然而，本发明不将电子元件限定于氮化物半导体元件，电子元件可以为任何适合的半导体元件，例如硅基元件、III-V族元件及/或绝缘层上有硅(SOI)元件。
接着，请参照图3B，形成一感光层324于基底302上方，以保护电子元件314。后续，请参照图3C，进行一微影工艺，图案化感光层324，使用图案化的感光层324作为蚀刻罩幕，蚀刻基底302，形成穿过基底302的通孔326(via)。在一实施例中，可使用雷射光束形成通孔326。
请参照图3D，移除光阻层324。在一实施例中，视需要地形成一绝缘层328于通孔326的侧壁上，以作为保护的用途。在一实施例中，绝缘层328可以是氧化硅，其可以热氧化法或液相沈积法(LPD)形成。请参照图3E，形成第一金属垫330于基底302的第二侧308上，且覆盖通孔326的第二开口311。在一实施例中，第一金属垫330可包括银胶，且可使用网印法形成。请参照图3F，以用第一金属垫330作为晶种层，进行一电镀工艺，形成填入通孔326中的导孔结构332。在一实施例中，导孔结构332和第一金属垫330包括相同的材料。在另一实施例中，导孔结构332和第一金属垫330包括不同的材料。例如，导孔结构332可包括铜。如图3F所示，由于导孔结构332在形成第一金属垫330之后形成，导孔结构332不延伸超过通孔326的邻近基302的第二侧308的第二开口311，但可延伸超过通孔326的邻近基底302的第一侧306的第一开口313。后续，形成例如银胶的第二金属垫334于基底302的第一侧306上。
在图3F中，半导体元件300包括半导体基底302和电子元件314。半导体元件300具有第一侧306和与第一侧306相对的第二侧308。至少部分的电子元件314邻接第一侧306。半导体元件300具有穿过半导体元件300的通孔326，其中通孔326具有第一开口313和第二开口311，第一开口邻接第一侧306，第二开口311邻接第二侧308。
一内连线结构C1位于半导体元件300中，其中内连线结构包括导孔结构332和第一金属垫330。导孔结构332设置于通孔326中，但不超过第一开口311。第一金属垫330设置于半导体元件300的第二侧308上且覆盖通孔326，其中第一金属垫330接合导孔结构332，且电性连接电子元件314。
以下的描述将会揭示本发明实施例采用图1F、图2和图3F的半导体元件的封装结构。
图4A-4B显示本发明一实施例形成封装结构方法的中间阶段的剖面图。
值得注意的是，与图1A-3F单元相似或相同的图4A-4B的单元具有类似的材料、结构及/或制作方法。因此，上述单元的细节在此不重复描述。
请参照图4A，提供一第一半导体元件K1和一第二半导体元件K2。第一半导体元件K1具有一第一侧106和与第一侧106相对的一第二侧108。第一半导体元件K1具有一第一半导体基底102a和多个个第一电子元件114a。第一半导体基底102a与图1A所示的基底102相同。在本实施例中，第一半导体基底102a可以是一晶粒或一晶片。
第一电子元件114a位于第一侧106。多个通孔126a穿过第一半导体基底102a，其中各通孔126a具有一第一开口111和一第二开口113，第一开口111邻近第一侧106，第二开口113邻近第二侧108。第一电子元件114a可以是一晶体管，且包括通道层110a、阻障层112a、栅电极116a、源极电极118a和漏极电极120a。
内连线结构410位于第一半导体基底102a中，其中各内连线结构410包括一导孔结构132a和一第一金属垫130。特别是，导孔结构132a位于通孔126a中，而不超出第一开口111，且第一金属垫130a设置于第一半导体基底102a的第一侧106并覆盖通孔126a。第一金属垫130a邻接导孔结构132a且电性连接第一电子元件114a。在一实施例中，部分的第一金属垫130a延伸至通孔126a。内连线结构410可还包括一第二金属垫134a，覆盖第二开口113且接合导孔结构132a。
特别是，可形成一重分配层420a于第一侧106上，以电性连接第一金属垫130a和第一电子元件114a。多个凸块430a可形成于第一金属垫130a上，且可经由重分配层420a电性连接第一金属垫130a和第一电子元件114a。凸块430a包括铜、锡或其他适合的材料。可形成一凸块下金属层432a(under bump metallurgy，简称UMB)于凸块430a和通道层110a间。形成一钝化层122a(例如氮化硅和氧化硅)以保护其下的第一电子元件114a。
第二半导体元件K2具有一第三侧S3和一相对于第三侧S3的第四侧S4。第二半导体元件K2包括一第二半导体基底102b(与图1A所示的基底102相同)和第二电子元件114b，位于第二半导体基底102b上。第二电子元件114b邻近第三侧S3。
在本实施例中，第二半导体基底102b可以是一晶粒。第二电子元件114b可以是一晶体管且包括通道层110b、阻障层112b、栅电极116b、源极电极118b和漏极电极120b。
特别是，可形成多个凸块430b于第三侧S3。可形成一凸块下金属层432b于凸块430b和通道层110b间。形成一重分配层420b于第三侧S3上，以电性连接凸块430b和第二电子元件114b。形成一钝化层122b(例如氮化硅和氧化硅)以保护其下的第二电子元件114b。凸块430b包括铜、锡或其他适合的材料。
后续，请参照图4B，将第一半导体元件K1(或第一半导体基底102a)通过连接凸块430b和凸块430a，大体上与第二半导体元件K2(或第二半导体基底102b)整合，以构成封装结构。凸块430b和凸块430a的连接包括回焊(reflow)工艺。凸块430b和凸块430a连接以形成凸块430。
第一电子元件114a经由重分配层420a、凸块430和重分配层420b电性连接第二电子元件114b。第一电子元件114a和第二电子元件114b皆电性内连线结构410。
在本实施例中，第一半导体基底102a的第一侧106和第二半导体基底102b的第三侧S3彼此面对。换句话说，第一半导体基底102a的第一侧106邻近第二半导体基底102b的第三侧S3。
在图4B中，形成封装结构400，其中封装结构400包括第一半导体元件K1、内连线结构410和第二半导体元件K2。
第一半导体元件K1包括第一半导体基底102a和第一电子元件114a。第一半导体元件K1具有第一侧106和与第一侧106相对的第二侧108。第一电子元件114a邻近第一侧106。第一半导体元件K1具有通孔126a，穿过第一半导体元件K1，其中各通孔126a具有第一开口111，邻近第一侧106。
内连线结构410位于第一半导体元件K1中，其中内连线结构410包括导孔结构132a和第一金属垫130a。导孔结构132a位于通孔126a中，而不超出第一开口111。第一金属垫130a设置于第一半导体元件K1的第一侧106并覆盖通孔126a，其中第一金属垫130a邻接导孔结构132a且电性连接电子元件114a。
将第二半导体元件K2垂直整合第一半导体元件K1，其中第二半导体元件K2包括电性连接第一电子元件114a的第二电子元件114b。
值得注意的是，使用内连线结构410取代传统的引线(未绘式)，且内连线结构410的电效能较传统的引线佳，因此可提供封装结构400更佳的效能。
图5显示本发明一实施例形成封装结构方法的中间阶段的剖面图。请参照图5，提供一载板510，其中载板510可以是印刷电路板、晶片或晶粒。载板510具有多个垫512位于其上。后续，将图4B的封装结构400经由凸块520大体上与载板510垂直整合。第一电子元114a和第二电子元件114b均经由内连线结构410电性连接载板510的垫512。
图6显示本发明一实施例封装结构的剖面图。请参照图6，本实施例的封装结构600类似于图4B的封装结构400，除了封装结构600的第二半导体基底102b是晶片。特别是，第一半导体基底102a和第二半导体基底102b均是晶片。
图7A-7B显示本发明一实施例形成封装结构方法的中间阶段的剖面图。
值得注意的是，图7A-7B的方法类似于图4A-4B的方法，除了图7A-7B第二半导体元件K2(或第二半导体基底102b)相较于图4A-4B第二半导体元件K2(或第二半导体基底102b)是倒置。特别是，第二半导体元件K2的第三侧S3(其上形成有第二电子元件114b)远离第一电子元件K1，且第二半导体元件K2的第四侧S4面对第一半导体元件K1。
请参照图7A，提供一第一半导体元件K1和一第二半导体元件K2，其中第一半导体元件K1具有第一半导体基底102a，第二半导体元件K2具有第二半导体基底102b。在本实施例中，第一半导体基底102a可以是晶粒或晶片。内连线结构710设置于第二半导体元件K2中，其中各内连线结构710包括导孔结构132b和第一金属垫130b。
特别是，导孔结构132b设置于通孔126b中，而不超出第一开口111b，且第一金属垫130b设置于第二半导体基底102b的第三侧S3上且覆盖通孔126b，其中第一金属垫130b邻接导孔结构132b，且经由重分配层420b电性连接第二电子元件114b。在一实施例中，部分的第一金属垫130b延伸至通孔126b。内连线结构710可还包括一第二金属垫134b，覆盖第二开口113b，且接合导孔结构132b。凸块430b系设置于第二金属垫134b上，且电性连接第二金属垫134b。
后续，请参照图7B，通过将凸块430b与凸块430a连接，将第一半导体元件K1大体上与第二半导体元件K2整合，以构成封装结构700。凸块430b与凸块430a连接以形成凸块430。
第一电子元件114a经由重分配层420a、凸块430、内连线结构710和重分配层420b电性连接第二电子元件114b。第一电子元件114a和第二电子元件114b均电性连接内连线结构410、710。
在本实施例中，第一半导体元件K1的第一侧106和第二半导体元件K2的第四侧S4彼此面对。换句话说，第一半导体元件K1的第一侧106邻近第二半导体元件K2的第四侧S4。
图8显示本发明一实施例封装结构的剖面图。请参照图8，本实施例的封装结构800类似于图7B的封装结构700，除了封装结构700的第二半导体基底102b是晶片。特别是，封装结构800的第一半导体基底102a和第二半导体基底102b均是晶片。更甚者，内连线结构410和710可彼此对准，且凸块430可夹设于内连线结构410和710间，且连接至两者。
图9A-9B显示本发明一实施例形成封装结构方法的中间阶段的剖面图。
值得注意的是，与图9A-9B单元相似或相同的图1A-8的单元具有类似的材料、结构及/或制作方法。因此，上述单元的细节在此不重复描述。
值得注意的是，图9A-9B的方法类似于图7A-7B的封装结构，除了图9A-9B的第二半导体元件K2包括一源极电极层S、一漏极电极层D和一夹设于两者间的主动层A。此外，第二半导体元件K2邻近第三侧S3的第二电子元件114b是栅电极。
特别是，第二电子元件114b(亦即栅电极)穿过源电极层S，其中一绝缘层(未绘示)设置于第二电子元件114b和源电极层S间，且设置于第二电子元件114b和主动层A间，以使第二电子元件114b与源电极层S和主动层A电性隔离。
请参照图9A，提供第一半导体元件K1和第二半导体元件K2，其中第一半导体元件K1具有第一半导体基底102a，第二半导体元件K2具有第二半导体基底102b。在本实施例中，第一半导体基底102a可以是晶粒或晶片，且第二半导体基底102b可以是晶粒。将凸块430b设置于第二半导体元件K2的第四侧S4，且电性连接至漏极电极层D。
后续，请参照图9B，通过连接凸块430b和凸块430a将第一半导体元件K1大体上与第二半导体元件K2垂直整合，以构成封装结构900。凸块430b和凸块430a连接以形成凸块430。
第一电子元件114a经由重分配层420a和凸块430电性连接第二半导体元件K2。第一电子元件114a和第二半导体元件K2均电性连接内连线结构410。
在本实施例中，第一半导体元件K1的第一侧106和第二半导体元件K2的第四侧S4彼此面对。换句话说，第一半导体元件K1的第一侧106邻近第二半导体元件K2的第四侧S4。
图10A-10B显示本发明一实施例形成封装结构方法的中间阶段的剖面图。
值得注意的是，与图10A-10B单元相似或相同的图1A-9B的单元具有类似的材料、结构及/或制作方法。因此，上述单元的细节在此不重复描述。
值得注意的是，图10A-10B的方法类似于图9A-9B的方法，除了图10A-10B的第一半导体元件K1相较于图9A-9B的第一半导体元件K1是倒置。特别是，第一半导体元件K1的第一侧106(该侧设置有第一电子元件114a)远离第二半导体元件K2，且第一半导体元件K1的第二侧108面向第二半导体元件K2。
请参照图10A，提供一第一半导体元件K1和一第二半导体元件K2，其中第一半导体元件K1具有第一半导体基底102a，第二半导体元件K2具有第二半导体基底102b。在本实施例中，第一半导体基底102a可以是晶粒或晶片，且第二半导体基底102b可以是晶粒。将凸块430a设置于第二金属垫134a上，且电性连接至第二金属垫134a。
后续，请参照图10B，通过连接凸块430b和凸块430a将第一半导体元件K1大体上与第二半导体元件K2垂直整合，以构成封装结构1000。凸块430b和凸块430a连接以形成凸块430。
第一电子元件114a经由重分配层420a、内连线结构410和凸块430电性连接第二半导体元件K2。第一电子元件114a和第二半导体元K2均电性连接内连线结构410。
在本实施例中，第一半导体元件K1的第二侧108和第二半导体元件K2的第四侧S4彼此面对。换句话说，第一半导体元件K1的第二侧108邻近第二半导体元件K2的第四侧S4。
值得注意的是，在上述实施例中，为示范性的说明，第一电子元件114a和第一金属垫130a形成在相同侧(亦即第一侧)，但其不用来限制本发明。在其他的实施例中(例如图3F的实施例)，第一电子元件314和第一金属垫330形成在不同侧。例如，第一电子元件314和第一金属垫330可分别形成在侧306和侧308。此外，钝化层322可形成在侧306上，以保护其下的第一电子元件314。
图11A显示本发明一实施例封装结构的立体图。图11B为图11A封装结构的等效电路图。
值得注意的是，图11A的封装结构1100类似于图10B的封装结构1000，除了图11A的封装结构1100还包括导线架1110。
特别是，如图11A和图11B所示，第一半导体元件K1包括具有氮化物半导体材料的HEMT元件，第二半导体元件K2包括具有氮化物半导体材料的垂直晶体管。第一和第二半导体元件K1、K2堆叠于导线架1110上。
导线架1110具有许多彼此分隔的部分1112、1114、1116、1118和1119。第一半导体元件K1设置于第一电子元件114a上。在此实施例中，第一电子元件114a是HEMT元件，设置于第一半导体元件K1的主动区上。第一半导体元件K1还包括一钝化层，覆盖部分的主动区、栅电极116a、源极电极118a和漏极电极120a。漏极电极120a设至于部分1112上，且电性连接部分1112。栅电极116a设至于部分1114上，且电性连接部分1114。源极电极118a设至于部分1116上，且电性连接部分1116。部分1112或部分1114可选择性的覆盖部分钝化层，以依产品设计的需要增加场板效应(field plate effect)。
内连线结构410设置于第一半导体基底102a中。第二半导体元件K2设置于第一半导体元件K1上。第二半导体元件K2包括第二电子元件114b。在此实施例中，第二电子元件114b是一垂直晶体管，包括源极电极S、栅电极G和漏极电极D，其中第二电子元件114b的漏极电极D经由内连线结构410电性连接第一电子元件114a的源极电极S。源极电极S经由夹钳结构1120(例如金属片)电性连接部分1118。特别是，第二电子元件114b的源极电极S经由夹钳结构1120和导线架1110中的导电路径(未绘示)电性连接第一电子元件114a的栅电极116a。栅电极116a经由两者间的接合引线1130电性连接部分1119。
根据上述，本发明使用内连线结构取代传统的引线，内连线结构相较于传统的引线具有较佳的电效能，使得封装结构有较好的表现。此外，本发明形成内连线结构的方法再电镀时使用第一金属垫作为晶种层，而不需要使用真空设备。因此，本发明的方法可以较低的成本制作半导体元件。
虽然本发明的较佳实施例说明如上，然其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当视所附的申请专利权利要求范围所界定者为准。

Claims (20)

1.一种封装结构，包括：
一第一半导体元件，包括一第一半导体基底和一第一电子元件，该第一半导体元件具有一第一侧和相对该第一侧的第二侧，其中至少部分该第一电子元件邻近该第一侧，且其中该第一半导体元件具有一通孔，穿过该第一半导体元件，其中该通孔具有一第一开口，邻近该第一侧；
一内连线结构，设置于该第一半导体元件中，其中该内连线结构包括：
一导孔结构，设置于该通孔中，且该导孔结构不超过该第一开口；
一第一金属垫，设置于该第一半导体元件的该第一侧上，且覆盖该通孔，其中该第一金属垫邻接该导孔结构，且电性连接该第一电子元件；及
一第二半导体元件，与该第一半导体元件垂直整合，其中该第二半导体元件包括一第二电子元件，电性连接该第一电子元件。
2.如权利要求1所述的封装结构，其中该第一半导体基底包括一晶粒或一晶片，且该第二半导体元件包括一第二半导体基底，其中该第二半导体基底包括一晶粒或一晶片。
3.如权利要求1所述的封装结构，其中该第二半导体元件具有一第三侧和与该第三侧相对的第四侧，且其中该第二半导体元件包括第二半导体基底，邻近该第四侧，且至少部分该第二电子元件邻近该第三侧。
4.如权利要求3所述的封装结构，其中该第一半导体元件的第一侧和该第二半导体元件的第三侧彼此面对。
5.如权利要求3项所述的封装结构，其中该第一半导体元件的第二侧和该第二半导体元件的第三侧彼此面对。
6.如权利要求3所述的封装结构，其中该第一半导体元件的第一侧和该第二半导体元件的第四侧彼此面对。
7.如权利要求3所述的封装结构，其中该第一半导体元件的第二侧和该第二半导体元件的第四侧彼此面对。
8.如权利要求1项所述的封装结构，其中该第一电子元件和该第二电子元件的至少一者是晶体管。
9.如权利要求1所述的封装结构，还包括：
一载板，其中该第一半导体元件和该第二半导体元件系堆叠于该载板上；且该第一电子元件和该第二电子元件经由该内连线结构电性连接该载板。
10.如权利要求1所述的封装结构，其中该第一金属垫的一部分延深入该通孔中。
11.一种封装结构的制作方法，包括：
提供一第一半导体元件，具有一第一侧和相对于该第一侧的第二侧；
形成一通孔，穿过该第一半导体元件，其中该通孔具有一第一开口和一第二开口，该第一开口邻近该第一侧，该第二开口邻近该第二侧；
形成一第一金属垫，覆盖该第一开口；
在形成该第一金属垫之后，形成一导孔结构于该通孔中，其中该导孔结构包括导电材料且邻接该第一金属垫；及
将该第一半导体元件大体上与该第二半导体元件垂直整合。
12.如权利要求11所述的封装结构的制作方法，还包括：
形成一第二金属垫，覆盖该第二开口，且邻接该导孔结构。
13.如权利要求11所述的封装结构的制作方法，其中该第一半导体元件包括：
一第一半导体基底；
一第一电子元件，设置于该第一半导体基底上，至少部分该第一电子元件邻近该第一半导体元件的该第一侧；及
一钝化层，设置于该第一半导体基底和该第一电子元件上。
14.如权利要求13所述的封装结构的制作方法，其中该第二半导体元件具有一第三侧和相对该第三侧的第四侧，且该第二半导体元件包括一第二半导体基底和一二电子元件，设置于该第二半导体基底上，至少部分该第二电子元件邻近该第三侧。
15.如权利要求14所述的封装结构的制作方法，其中该第一半导体元件垂直整合该第二半导体元件，且该第一半导体元件的第一侧与该第二半导体元件的第三侧彼此面对。
16.如权利要求14所述的封装结构的制作方法，其中该第一半导体元件垂直整合该第二半导体元件，且该第一半导体元件的第二侧与该第二半导体元件的第三侧彼此面对。
17.如权利要求14所述的封装结构的制作方法，其中该第一半导体元件垂直整合该第二半导体元件，且该第一半导体元件的第二侧与该第二半导体元件的第四侧彼此面对。
18.如权利要求14所述的封装结构的制作方法，其中该第一半导体元件垂直整合该第二半导体元件，而该第一半导体元件的第一侧与该第二半导体元件的第四侧彼此面对。
19.如权利要求11所述的封装结构的制作方法，其中形成该第一金属垫的步骤包括进行一网印工艺，形成该第一金属垫，覆盖该第一开口。
20.如权利要求11所述的封装结构的制作方法，其中该第一半导体元件包括：
一第一半导体基底；
一第一电子元件，设置于该第一半导体基底上，且至少部分该第一电子元件邻近该第一半导体元件的该第二侧；及
一钝化层，设置于该第一半导体基底和该第一电子元件上。
CN201310552017.3A 2012-11-13 2013-11-08 封装结构和其制作方法 Active CN103811465B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/675,297 US9159699B2 (en) 2012-11-13 2012-11-13 Interconnection structure having a via structure
US13/675,297 2012-11-13

Publications (2)

Publication Number Publication Date
CN103811465A true CN103811465A (zh) 2014-05-21
CN103811465B CN103811465B (zh) 2019-07-16

Family

ID=49510038

Family Applications (3)

Application Number Title Priority Date Filing Date
CN201310557121.1A Pending CN103811461A (zh) 2012-11-13 2013-11-08 内连线结构和其制作方法
CN201310552017.3A Active CN103811465B (zh) 2012-11-13 2013-11-08 封装结构和其制作方法
CN201910107660.2A Pending CN110085563A (zh) 2012-11-13 2013-11-08 内连线结构和其制作方法

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201310557121.1A Pending CN103811461A (zh) 2012-11-13 2013-11-08 内连线结构和其制作方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201910107660.2A Pending CN110085563A (zh) 2012-11-13 2013-11-08 内连线结构和其制作方法

Country Status (4)

Country Link
US (2) US9159699B2 (zh)
EP (2) EP2731133A3 (zh)
CN (3) CN103811461A (zh)
TW (2) TWI515859B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022236712A1 (en) * 2021-05-11 2022-11-17 Innoscience (suzhou) Semiconductor Co., Ltd. Integrated semiconductor device and method for manufacturing the same

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140073163A (ko) * 2012-12-06 2014-06-16 삼성전자주식회사 반도체 장치 및 그의 형성방법
US9659851B2 (en) * 2014-02-07 2017-05-23 Marvell World Trade Ltd. Method and apparatus for improving the reliability of a connection to a via in a substrate
FR3028095B1 (fr) 2014-11-04 2018-01-26 Commissariat A L'energie Atomique Et Aux Energies Alternatives Dispositif electronique de puissance a cellule de commutation 3d verticale
KR20170011366A (ko) * 2015-07-22 2017-02-02 삼성전자주식회사 반도체 칩 및 이를 가지는 반도체 패키지
CN109671773B (zh) * 2017-10-16 2020-05-05 苏州能讯高能半导体有限公司 半导体器件及其制造方法
US10366982B2 (en) 2017-11-30 2019-07-30 Taiwan Semiconductor Manufacturing Co., Ltd. Structure with embedded memory device and contact isolation scheme
KR102327745B1 (ko) * 2018-02-01 2021-11-17 미쓰비시덴키 가부시키가이샤 반도체 장치 및 그의 제조 방법
US11004794B2 (en) 2018-06-27 2021-05-11 Taiwan Semiconductor Manufacturing Co., Ltd. Partial barrier free vias for cobalt-based interconnects and methods of fabrication thereof
CN109300947B (zh) * 2018-09-28 2021-09-07 京东方科技集团股份有限公司 柔性显示基板及其制造方法、显示装置
EP3783663A1 (en) 2019-08-21 2021-02-24 Infineon Technologies AG Semiconductor device and method
FR3122036A1 (fr) * 2021-04-14 2022-10-21 Exagan Dispositif bidirectionnel pourvu d’un empilement de deux transistors a haute mobilite electronique connectes tete-beche
TWI813100B (zh) * 2021-12-17 2023-08-21 世界先進積體電路股份有限公司 半導體結構與其製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090093117A1 (en) * 2007-10-09 2009-04-09 Shinko Electric Industries Co., Ltd. Method of manufacturing substrate
US20090236731A1 (en) * 2008-03-19 2009-09-24 Seong Bo Shim Stackable integrated circuit package system
US20120056312A1 (en) * 2010-09-02 2012-03-08 Stats Chippac, Ltd. Semiconductor Device and Method of Forming TSV Semiconductor Wafer with Embedded Semiconductor Die
US20120228780A1 (en) * 2011-03-08 2012-09-13 Ji Hwang Kim Semiconductor device and method of manufacturing the same

Family Cites Families (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5447871A (en) * 1993-03-05 1995-09-05 Goldstein; Edward F. Electrically conductive interconnection through a body of semiconductor material
US6620731B1 (en) 1997-12-18 2003-09-16 Micron Technology, Inc. Method for fabricating semiconductor components and interconnects with contacts on opposing sides
TWI244571B (en) * 2002-01-30 2005-12-01 Sanyo Electric Co Semiconductor display device
US7312400B2 (en) * 2002-02-22 2007-12-25 Fujikura Ltd. Multilayer wiring board, base for multilayer wiring board, printed wiring board and its manufacturing method
US7045861B2 (en) * 2002-03-26 2006-05-16 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device, liquid-crystal display device and method for manufacturing same
JP2004095849A (ja) * 2002-08-30 2004-03-25 Fujikura Ltd 貫通電極付き半導体基板の製造方法、貫通電極付き半導体デバイスの製造方法
JP3937993B2 (ja) * 2002-10-02 2007-06-27 日立電線株式会社 配線板の製造方法
US6828512B2 (en) * 2002-10-08 2004-12-07 Intel Corporation Apparatus and methods for interconnecting components to via-in-pad interconnects
JP2004146748A (ja) * 2002-10-28 2004-05-20 Alps Electric Co Ltd 薄膜キャパシタ素子
EP2596948B1 (en) * 2003-03-10 2020-02-26 Toyoda Gosei Co., Ltd. Method of making a semiconductor device
US6897148B2 (en) * 2003-04-09 2005-05-24 Tru-Si Technologies, Inc. Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby
JP3891299B2 (ja) * 2003-05-06 2007-03-14 セイコーエプソン株式会社 半導体装置の製造方法、半導体装置、半導体デバイス、電子機器
GB0311251D0 (en) * 2003-05-16 2003-06-18 Koninkl Philips Electronics Nv Method of manufacture recyclable electronic products and electronic products obtained by the method
US7919787B2 (en) * 2003-06-27 2011-04-05 Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. Semiconductor device with a light emitting semiconductor die
KR100493063B1 (ko) * 2003-07-18 2005-06-02 삼성전자주식회사 스택 반도체 칩 비지에이 패키지 및 그 제조방법
US8084866B2 (en) * 2003-12-10 2011-12-27 Micron Technology, Inc. Microelectronic devices and methods for filling vias in microelectronic devices
JP2005303258A (ja) * 2004-03-16 2005-10-27 Fujikura Ltd デバイス及びその製造方法
JP4327644B2 (ja) * 2004-03-31 2009-09-09 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
US7498647B2 (en) * 2004-06-10 2009-03-03 Micron Technology, Inc. Packaged microelectronic imagers and methods of packaging microelectronic imagers
KR100594716B1 (ko) * 2004-07-27 2006-06-30 삼성전자주식회사 공동부를 구비한 캡 웨이퍼, 이를 이용한 반도체 칩, 및그 제조방법
JP4803993B2 (ja) * 2004-11-09 2011-10-26 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US7476918B2 (en) * 2004-11-22 2009-01-13 Panasonic Corporation Semiconductor integrated circuit device and vehicle-mounted radar system using the same
EP1920459A4 (en) * 2005-08-12 2012-07-25 Semiconductor Energy Lab PROCESS FOR PRODUCING A SEMICONDUCTOR COMPONENT
JP4758712B2 (ja) * 2005-08-29 2011-08-31 新光電気工業株式会社 半導体装置の製造方法
US7772116B2 (en) * 2005-09-01 2010-08-10 Micron Technology, Inc. Methods of forming blind wafer interconnects
KR100704915B1 (ko) * 2005-09-15 2007-04-09 삼성전기주식회사 미세 패턴을 가지는 인쇄회로기판 및 그 제조방법
US7633167B2 (en) * 2005-09-29 2009-12-15 Nec Electronics Corporation Semiconductor device and method for manufacturing same
TW200733336A (en) * 2006-02-17 2007-09-01 Advanced Semiconductor Eng Ball grid array package structure with identification marks and substrate thereof
US7741218B2 (en) * 2007-02-27 2010-06-22 Freescale Semiconductor, Inc. Conductive via formation utilizing electroplating
JP2008305938A (ja) * 2007-06-07 2008-12-18 Toshiba Corp 半導体装置および半導体装置の製造方法
JP2009070966A (ja) * 2007-09-12 2009-04-02 Toshiba Corp 半導体装置とその製造方法
US20120126419A1 (en) * 2008-07-24 2012-05-24 Vaidyanathan Kripesh Substrate Arrangement and a Method of Manufacturing a Substrate Arrangement
US7843072B1 (en) 2008-08-12 2010-11-30 Amkor Technology, Inc. Semiconductor package having through holes
KR101002680B1 (ko) * 2008-10-21 2010-12-21 삼성전기주식회사 반도체 패키지 및 그 제조 방법
JP2010103236A (ja) * 2008-10-22 2010-05-06 Panasonic Corp 窒化物半導体装置
JP5268618B2 (ja) * 2008-12-18 2013-08-21 株式会社東芝 半導体装置
JP5308145B2 (ja) * 2008-12-19 2013-10-09 ルネサスエレクトロニクス株式会社 半導体装置
JP5471268B2 (ja) * 2008-12-26 2014-04-16 大日本印刷株式会社 貫通電極基板及びその製造方法
US7932608B2 (en) * 2009-02-24 2011-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via formed with a post passivation interconnect structure
KR101573934B1 (ko) * 2009-03-02 2015-12-11 엘지전자 주식회사 태양 전지 및 그 제조 방법
US8329578B2 (en) * 2009-03-27 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Via structure and via etching process of forming the same
CN101847597B (zh) * 2009-03-27 2013-12-04 台湾积体电路制造股份有限公司 集成电路结构
CN102185580A (zh) * 2010-01-18 2011-09-14 精工爱普生株式会社 电子装置、基板的制造方法以及电子装置的制造方法
KR101688006B1 (ko) * 2010-11-26 2016-12-20 삼성전자주식회사 반도체 장치
US20120146111A1 (en) * 2010-12-14 2012-06-14 Shu-Ming Chang Chip package and manufacturing method thereof
CN102569144B (zh) * 2010-12-22 2015-05-13 中芯国际集成电路制造(上海)有限公司 一种通孔刻蚀方法
KR20120071921A (ko) * 2010-12-23 2012-07-03 한국전자통신연구원 실리콘 관통 홀(ｔｓｖ) 충진용 조성물, ｔｓｖ 충진방법 및 상기 조성물을 이용하여 형성된 ｔｓｖ 충진물을 포함하는 기판
WO2012090901A1 (ja) * 2010-12-28 2012-07-05 京セラ株式会社 光モジュールおよび光配線基板
KR101801137B1 (ko) * 2011-02-21 2017-11-24 삼성전자주식회사 반도체 장치 및 그 제조 방법
US8546900B2 (en) * 2011-06-09 2013-10-01 Optiz, Inc. 3D integration microelectronic assembly for integrated circuit devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090093117A1 (en) * 2007-10-09 2009-04-09 Shinko Electric Industries Co., Ltd. Method of manufacturing substrate
US20090236731A1 (en) * 2008-03-19 2009-09-24 Seong Bo Shim Stackable integrated circuit package system
US20120056312A1 (en) * 2010-09-02 2012-03-08 Stats Chippac, Ltd. Semiconductor Device and Method of Forming TSV Semiconductor Wafer with Embedded Semiconductor Die
US20120228780A1 (en) * 2011-03-08 2012-09-13 Ji Hwang Kim Semiconductor device and method of manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022236712A1 (en) * 2021-05-11 2022-11-17 Innoscience (suzhou) Semiconductor Co., Ltd. Integrated semiconductor device and method for manufacturing the same
US11967519B2 (en) 2021-05-11 2024-04-23 Innoscience (suzhou) Semiconductor Co., Ltd. Integrated semiconductor device and method for manufacturing the same
US11967521B2 (en) 2021-05-11 2024-04-23 Innoscience (suzhou) Semiconductor Co., Ltd. Integrated semiconductor device and method for manufacturing the same

Also Published As

Publication number Publication date
EP2731132A2 (en) 2014-05-14
US9159699B2 (en) 2015-10-13
EP2731132A3 (en) 2017-05-17
TWI532130B (zh) 2016-05-01
TWI515859B (zh) 2016-01-01
EP2731133A2 (en) 2014-05-14
CN103811465B (zh) 2019-07-16
US10424508B2 (en) 2019-09-24
EP2731133A3 (en) 2017-11-01
TW201419470A (zh) 2014-05-16
TW201419487A (zh) 2014-05-16
US20140131871A1 (en) 2014-05-15
CN103811461A (zh) 2014-05-21
US20150294910A1 (en) 2015-10-15
CN110085563A (zh) 2019-08-02

Similar Documents

Publication Publication Date Title
CN103811465A (zh) 封装结构和其制作方法
KR101920715B1 (ko) 고 전자 이동도 트랜지스터 및 그 제조방법
TW200929408A (en) Wafer level chip scale packaging
TW202211380A (zh) 用於在裸晶之前側上之柱連接及在裸晶之後側上之被動裝置整合之方法
US20120211884A1 (en) Wafer chip scale package connection scheme
KR20230061545A (ko) Rf 트랜지스터 증폭기 패키지
CN108493162A (zh) 用于晶圆级封装的密封环
US9275982B2 (en) Method of forming interconnection structure of package structure
US10796954B2 (en) Semiconductor structure and method for forming the same
US20210265241A1 (en) Front-end-of-line (feol) through semiconductor-on-substrate via (tsv)
US11075148B2 (en) Stacked transistor assembly with dual middle mounting clips
US20230343693A1 (en) Wafer-on-wafer Cascode HEMT Device
US11967521B2 (en) Integrated semiconductor device and method for manufacturing the same
US8853859B2 (en) Passivation for wafer level—chip-scale package devices
CN109473420B (zh) 耐电弧的开裂阻止
CN110660778B (zh) 半导体结构及其形成方法
US20240105692A1 (en) Packaged flip chip radio frequency transistor amplifier circuits
CN107980171B (zh) 半导体芯片、半导体晶圆及半导体晶圆的制造方法
CN115565952A (zh) 芯片封装结构及其制造方法
CN115881541A (zh) 半导体装置的制作方法
TW202314856A (zh) 半導體裝置的製作方法
JP2022121116A (ja) 半導体素子、当該半導体素子を備えた半導体装置、および、半導体素子の製造方法
CN116978899A (zh) 半导体结构及其形成方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20221109

Address after: No. 252, Shanying Road, Guishan District, Taoyuan City, Taiwan, China, China (6/F)

Patentee after: Anchorage Semiconductor Co.,Ltd.

Address before: Taoyuan County, Taiwan, China

Patentee before: DELTA ELECTRONICS, Inc.