CN103811461A - 内连线结构和其制作方法 - Google Patents

内连线结构和其制作方法 Download PDF

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Publication number
CN103811461A
CN103811461A CN201310557121.1A CN201310557121A CN103811461A CN 103811461 A CN103811461 A CN 103811461A CN 201310557121 A CN201310557121 A CN 201310557121A CN 103811461 A CN103811461 A CN 103811461A
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CN
China
Prior art keywords
substrate
pad
internal connection
hole
guide hole
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Pending
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CN201310557121.1A
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English (en)
Inventor
蔡欣昌
李嘉炎
李芃昕
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Delta Electronics Inc
Delta Optoelectronics Inc
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Delta Optoelectronics Inc
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Priority to CN201910107660.2A priority Critical patent/CN110085563A/zh
Publication of CN103811461A publication Critical patent/CN103811461A/zh
Pending legal-status Critical Current

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Abstract

本发明公开了一种内连线结构和其的制作方法，该方法包括：提供一基底，具有一第一侧和一相对于第一侧的一第二侧；形成一通孔，穿过基底，其中通孔具有一第一开口和一第二开口，第一开口邻近基底的第一侧，第二开口邻近基底的第二侧；形成一第一垫，覆盖第一开口；在形成第一垫之后，形成一导孔结构于通孔中，其中导孔结构包括导电材料，且邻接第一垫。

Description

内连线结构和其制作方法
技术领域
本发明有关于一种集成电路装置及其制作方法，特别是有关于一种内连线结构和其制作方法。
背景技术
半导体构件包括外部连接，使得电连接可从外部连接至半导体构件中的集成电路。例如，一半导体晶粒包括形成在晶粒表面的接合垫图案，而芯片尺寸封装(chip scale package)的半导体封装体亦包括外部连接。一般来说，构件在其表面侧(电路侧)或背面侧包括外部连接，且构件有时于表面侧和背面侧均需有外部连接。
在半导体技术中，穿基底导孔(through substrate via)是形成在半导体基底(晶片或晶粒)中的导电图样，以电性连接基底两侧的外部连接。TSV垂直穿过半导体基底，提供堆叠的晶片/晶粒的封装方法，使得分隔晶片或晶粒的电路间可形成电性连接。形成TSV的方法包括许多种，一般来说，其包括对半导体基底进行蚀刻，形成孔洞，且孔洞有时可穿过内连线结构。孔洞中可包括绝缘层及/或金属层。孔洞后续填入一般为铜的导电材料，形成TSV的主要部分。
传统的技术使用电镀法形成填入TSV孔洞中的导电填充材料，而电镀技术的晶种层(seeding layer)使用如物理气相沉积的真空技术在填入导电填充材料之前形成。然而，真空技术为高价的设备，因此增加元件的成本。
发明内容
本发明的目的在于提供一种内连线结构及其制作方法，用以解决上述的问题或其他问题。
根据上述，本发明于一实施例提供一种内连线结构，包括：一基底，具有至少一电子元件和一穿过基底的通孔，其中至少一电子元件邻近基底的第一侧，通孔具有一第一开口，邻近基底的第一侧；一导孔结构，位于通孔中，其中导孔结构不超过第一开口；一第一垫，位于基底的第一侧且覆盖通孔，其中第一垫邻接导孔结构且电性连接至少一电子元件。
本发明于一实施例提供一种内连线结构的制作方法，包括：提供一基底，具有一第一侧和一相对于第一侧的一第二侧；形成一通孔，穿过基底，其中通孔具有一第一开口和一第二开口，第一开口邻近基底的第一侧，第二开口邻近基底的第二侧；形成一第一垫，覆盖第一开口；在形成第一垫之后，形成一导孔结构于通孔中，其中导孔结构包括导电材料，且邻接第一垫。
本发明于一实施例提供一种内连线结构的制作方法，包括：提供一基底；形成一通孔，穿过基底；及于基底的一第一侧进行一网印工艺，填入一导电材料于通孔中，以于通孔中形成一导孔结构和位于基底的一第一侧的第一垫，其中第一垫邻接导孔结构。
附图说明
图1A～图1F显示本发明一实施例形成内连线结构的方法中间阶段的剖面图。
图2显示本发明另一实施例形成内连线结构的方法中间阶段的剖面图。
图3A～图3F显示本发明另一实施例形成内连线结构的方法中间阶段的剖面图。
其中，附图标记说明如下：
102～基底；  104～缓冲层；
106～第一侧；  108～第二侧；
110～通道层；  111～第一开口；
112～阻障层；  113～第二开口；
114～电子元件；  116～栅电极；
118～源极电极；  120～漏极电极；
122～钝化层；  124～感光层；
126～通孔；  128～绝缘层；
130～第一垫；  132～导孔结构；
134～第二垫；  202～第一垫；
302～基底；  304～缓冲层；
306～第一侧；  308～第二侧；
310～通道层；  311～第二开口；
312～阻障层；  314～电子元件；
316～栅电极；  318～源极电极；
320～漏极电极；  324～感光层；
326～通孔；  328～绝缘层；
330～第一垫；  332～导孔结构；
334～第二垫。
具体实施方式
以下详细讨论实施本发明的实施例。可以理解的是，实施例提供许多可应用的发明概念，其可以较广的变化实施。所讨论的特定实施例仅用来发明使用实施例的特定方法，而不用来限定发明的范畴。为让本发明的特征能更明显易懂，下文特举实施例，并配合所附图式，作详细说明如下：
以下配合图1A～图1F描述本发明一实施例形成内连线结构的方法。首先，请参照图1A，提供一基底102，包括第一侧106和相对于第一侧106的第二侧108。基底102可包括任何适合的半导体材料。例如基底102可包括Si、SiC、Ge、SiGe、GaAs、InAs、InP或GaN。后续，形成一缓冲层104于基底102上。在本发明一实施例中，缓冲层104是氮化物材料，以提供后续形成于其上层良好的粘着性，且亦可解决晶格不协调的问题。然而，本发明不限定于上述材料，缓冲层104可以任何适合的材料形成。在本发明一实施例中，缓冲层104可以是氮化铝。
后续，形成一通道层110和一阻障层112于缓冲层104上。在一实施例中，通道层110可以是GaN，阻障层112可以是AlGaN。接着，形成一第一金属层(未绘示)于通道层110上，并对第一金属层进行微影和蚀刻的图案化步骤，形成一源极电极118和一漏极电极120。在本发明一实施例中，第一金属层是Ti、Al、Ni及/或Au的堆叠层。在形成第一金属层之后，可对其进行快速热退火的步骤。接着，沉积一第二金属层(未绘示)于通道层110上，对第二金属层进行微影和蚀刻的图案化步骤，以形成栅电极116。后续，形成例如氮化硅或氧化硅的钝化层122(passivation layer)，以保护其下的元件。
通道层110、阻障层112、栅电极116、源极电极118和漏极电极120构成邻近基底102第一侧106的电子元件114。本发明在一实施例中将电子元件114设置为邻近基底102的第一侧106，但本发明不限于此，电子元件114可设置于基底102的第二侧108。在一实施例中，电子元件114为氮化物半导体元件，然而，本发明不限定电子元件为氮化物半导体元件，电子元件可以为任何适合的半导体元件，例如硅基元件、III-V族元件及/或绝缘层上有硅(SOI)元件。
接着，请参照图1B，形成一感光层124于基底102上方。后续，请参照图1C，进行一微影工艺，图案化感光层124，且使用图案化的感光层124作为蚀刻罩幕，蚀刻基底102，形成穿过基底102的通孔126(via)。在一实施例中，可使用雷射光束形成通孔126。
请参照图1D，形成一绝缘层128于通孔126的侧壁上，以作为保护和隔离的用途。在一实施例中，绝缘层128可以是氧化硅，其可以热氧化法或液相沈积法(Liquid phase deposition，简称LPD)形成。请参照图1E，形成第一垫130于基底102的第一侧106上，且覆盖通孔126的第一开口111。第一垫130可电性连接电子元件114和后续步骤形成的第二垫134，且包括一凸出部分，延伸至通孔126中。在一实施例中，第一垫130可包括银胶，且可使用网印法形成。请参照图1F，以第一垫130作为晶种层，进行一电镀工艺，成长一导电材料以填入通孔126中，而形成一导孔结构132。在一实施例中，导孔结构132和第一垫130包括相同的材料。在另一实施例中，导孔结构132和第一垫130包括不同的材料。例如，第一垫130和导孔结构132皆可包括铜或银。
如图1F所示，由于导孔结构132在形成第一垫130之后形成，导孔结构130不延伸超过通孔126的邻近基底102的第一侧106的第一开口111，但可延伸超过通孔126的邻近基底102的第二侧108的第二开口113。后续，形成第二垫134于基底102的第二侧108上。在一实施例中，第二垫134可包括银胶，且可使用网印法形成。虽然图式中未绘示，本发明可包括另一半导体基底，其具有另一电子元件，且该另一电子元件电性连接第二垫。
在本发明的一实施例中，电子元件114是高电子迁移率晶体管(highelectron mobility transistor，简称HEMT)，且基底102包括半导体基底。电子元件114可经由导孔结构132电性连接至半导体基底另一侧其他电子元件(未绘示)。
以下以图2描述本发明另一实施例形成内连线结构的方法。图2的内连线结构的形成方法类似图1E～图1F的内连线结构的形成方法，为简洁，相同的部分在此不重复描述。图2的内连线结构的形成方法与图1E～图1F的内连线结构的形成方法不同处在于第一垫202和导孔结构204以单一步骤形成。在一实施例中，通孔126的深度不深(例如20μm～50μm)，如图2所示，形成第一垫202的网印法亦可填满通孔126，所以可以单一网印步骤形成第一垫202和导孔结构204。
以下配合图3A～图3F描述本发明另一实施例形成内连线结构的方法。图3A～图3F与图1A～图1F实施例不同处为在形成导孔结构前，形成垫于基底与第一侧(邻近电子元件)相对的第二侧。首先，请参照图3A，提供一基底302，包括第一侧306和一第二侧308。基底302可包括任何适合的半导体材料。例如基底302可包括Si、SiC、Ge、SiGe、GaAs、InAs、InP或GaN。后续，形成一缓冲层304于基底302上。在本发明一实施例中，缓冲层304可以是氮化铝。后续，形成一通道层310和一阻障层312于缓冲层304上。在一实施例中，通道层310可以是GaN，阻障层312可以是AlGaN。接着，形成一第一金属层(未绘示)于通道层310上，且对第一金属层进行微影和蚀刻的图案化步骤，形成一源极电极318和一漏极电极320。在本发明一实施例中，第一金属层是Ti、Al、Ni及/或Au的堆叠层。在形成第一金属层之后，可对其进行快速热退火的步骤。接着，沉积一第二金属层(未绘示)于通道层310上，对第二金属层进行微影和蚀刻的图案化步骤，以形成栅电极316。后续，形成例如氮化硅或氧化硅的钝化层322(passivation layer)，以保护其下的元件。
通道层310、阻障层312、栅电极316、源极电极318和漏极电极320构成邻近基底302第一侧306的电子元件314。在一实施例中，电子元件314为氮化物半导体元件，然而，本发明不限定电子元件为氮化物半导体元件，电子元件可为任何适合的半导体元件，例如硅基元件、III-V族元件及/或绝缘层上有硅(SOI)元件。
接着，请参照图3B，形成一感光层324于基底302上方，以保护电子元件314。后续，请参照图3C，进行一微影工艺，图案化感光层324，且使用图案化的感光层324作为蚀刻罩幕，蚀刻基底302，形成穿过基底302之通孔326(via)。在一实施例中，可使用雷射光束形成通孔326。
请参照图3D，形成一绝缘层328于通孔326的侧壁上，以作为保护和隔离的用途。在一实施例中，绝缘层328可以是氧化硅，其可以热氧化法或液相沈积法(LPD)形成。请参照图3E，形成第一垫330于基底302的第二侧308上，且覆盖通326的第二开口311。在一实施例中，第一垫330可包括银胶，且可使用网印法形成。请参照图3F，以第一垫330作为晶种层，进行一电镀工艺，形成填入通孔326中的导孔结构332。在一实施例中，导孔结构332和第一垫330包括相同的材料。在另一实施例中，导孔结构332和第一垫330包括不同的材料。例如，第一垫330和导孔结构332皆可包括铜或银。如图3F所示，由于导孔结构332在形成第一垫330之后形成，导孔结构332不延伸超过通孔326的邻近基底302的第二侧308的第二开口311，但可延伸超过通孔326的邻近基底302的第一侧306的第一开口313。后续，形成例如银胶的第二垫334于基底302的第一侧306上。
本发明实施例形成内连线结构的方法具有以下优点：由于本发明形成内连线结构的方法在使用导孔结构的电镀工艺中使用第一垫作为晶种层，在形成内连线的过程中不需使用真空工艺，因此可以较低的成本制作半导体元件。
虽然本发明的较佳实施例说明如上，然其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当视所附的申请专利权利要求范围所界定者为准。

Claims (20)

1.一种内连线结构，包括：
一基底，具有至少一电子元件和一穿过该基底的通孔，其中该至少一电子元件邻近该基底的第一侧，该通孔具有一第一开口，邻近该基底的该第一侧；
一导孔结构，位于该通孔中，其中该导孔结构不超过该第一开口；及
一第一垫，位于该基底的第一侧且覆盖该通孔，其中该第一垫邻接该导孔结构且电性连接该至少一电子元件。
2.如权利要求1所述的内连线结构，其中该第一垫包括一凸出部分，延深至该通孔。
3.如权利要求1所述的内连线结构，还包括一第二垫，位于该基底的第二侧，且邻接该导孔结构。
4.如权利要求1所述的内连线结构，还包括一绝缘层，位于该通孔的侧壁上，且围绕该导孔结构。
5.如权利要求1所述的内连线结构，其中该第一垫和该导孔结构包括不同的材料。
6.如权利要求1所述的内连线结构，其中该第一垫和该导孔结构包括相同的材料。
7.如权利要求1所述的内连线结构，其中该导孔结构包括铜。
8.如权利要求1所述的内连线结构，其中该第一垫包括银胶。
9.一种内连线结构的制作方法，包括：
提供一基底，具有一第一侧和一相对于该第一侧的一第二侧；
形成一通孔，穿过该基底，其中该通孔具有一第一开口和一第二开口，该第一开口邻近该基底的该第一侧，该第二开口邻近该基底的该第二侧；
形成一第一垫，覆盖该第一开口；及
在形成该第一垫之后，形成一导孔结构于该通孔中，其中该导孔结构包括导电材料，且邻接该第一垫。
10.如权利要求9所述的内连线结构的制作方法，还包括：
形成至少一电子元件于该基底上；及
在形成该通孔前，形成一感光层于该基底上，覆盖该至少一电子元件。
11.如权利要求9所述的内连线结构的制作方法，其中在形成该导孔结构前，还包括形成一绝缘层于该通孔的侧壁上。
12.如权利要求9所述的内连线结构的制作方法，其中形成该第一垫的步骤包括进行一第一金属网印工艺，形成该第一垫，覆盖该第一开口。
13.如权利要求9所述的内连线结构的制作方法，其中在形成该导孔结构后，还包括形成一第二垫，覆盖该导孔结构。
14.如权利要求9所述的内连线结构的制作方法，其中形成该通孔穿过该基底的步骤包括使用雷射光束对该基底进行钻孔。
15.如权利要求9所述的内连线结构的制作方法，其中形成该导孔结构为使用以该第一垫作为晶种层的电镀工艺。
16.一种内连线结构的制作方法，包括：
提供一基底；
形成一通孔，穿过该基底；及
于该基底的一第一侧进行一网印工艺，填入一导电材料于该通孔中，以于该通孔中形成一导孔结构和位于该基底的一第一侧的第一垫，其中该第一垫邻接该导孔结构。
17.如权利要求16所述的内连线结构的制作方法，还包括：
形成至少一电子元件于该基底上；及
在形成该通孔前，形成一感光层于该基底上，覆盖该至少一电子元件。
18.如权利要求17所述的内连线结构的制作方法，其中该电子元件位于该基底的第一侧。
19.如权利要求17所述的内连线结构的制作方法，其中该电子元件位于该基底之第二侧，该第二侧相对于该第一侧。
20.如权利要求16所述的内连线结构的制作方法，其中在形成该导孔结构前，还包括形成一绝缘层于该通孔的侧壁上。
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