CN108493162A - 用于晶圆级封装的密封环 - Google Patents

用于晶圆级封装的密封环 Download PDF

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CN108493162A
CN108493162A CN201810150694.5A CN201810150694A CN108493162A CN 108493162 A CN108493162 A CN 108493162A CN 201810150694 A CN201810150694 A CN 201810150694A CN 108493162 A CN108493162 A CN 108493162A
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seal ring
crystal grain
redistribution layer
semiconductor device
sealing ring
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龚顺强
陈元文
高山
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GlobalFoundries Singapore Pte Ltd
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Abstract

本发明涉及用于晶圆级封装的密封环，揭示装置及用于形成装置的方法。提供至少一晶粒。具有扇出区域的重分布层从该至少一晶粒的外周缘同心地向外延伸。密封环设置在该重分布层的该扇出区域中。

Description

用于晶圆级封装的密封环
技术领域
本发明涉及晶圆级封装的技术。
背景技术
晶圆级封装(WLP)为在晶圆级集成电路(IC)的封装技术，这产生实质具有晶粒(die)尺寸的装置。传统WLP技术包括扇入WLP(Fan-In WLP；FIWLP)技术，其在芯片边缘形成接触垫的密集周边数组且添加重分布层(redistribution layer；RDL)以路由连接/电路迹线至较不密集的面积数组(area array)。不过，由于输入/输出(I/O)的组态受限于晶粒表面，FIWLP封装受限于低端半导体装置，例如，需要少于300个I/O的装置。
扇出WLP(Fan-Out WLP；FOWLP)技术，例如嵌入式晶圆级球栅数组(eWLB)为一种增强版FIWLP技术，其提供需要更多I/O个数及更高整合程度之半导体装置的解决方案。例如，FOWLP技术选择预切的已知良品晶粒(KGD)，使用环氧树脂模塑化合物(EMC)重组该等KGD于晶圆或面板中用以提供额外空间供互连用且增加具有一介电层及数个铜互连的扇出重分布层(RDL)。可在封装上实现有任意距离的任意多个附加互连(亦即，扇出设计)，而不是FIWLP，在此芯片面积会不足以适当的距离安置所需个数的互连。
为了满足半导体装置的电气效能要求，使用低k或超低k介电材料和铜互连来构造RDL。不过，此一材料选择免不了使封装的机械强度劣化，而产生芯片封装互动(CPI)可靠性问题。CPI可靠性问题的例子包括起于晶粒角落的剥离与起于切割工具把晶圆切成主动芯片区之区域的裂纹扩展。
因此，最好提供简化且有成本效益的技术用以减轻CPI可靠性问题。
发明内容
数个具体实施例大体系涉及半导体装置与形成半导体装置的方法。在一具体实施例中，提出一种半导体装置。该半导体装置包括至少一晶粒。具有扇出区域的重分布层从该至少一晶粒的外周缘同心地向外延伸。密封环设置在该重分布层的扇出区域中。
在一具体实施例中，揭示一种装置。该装置包括具有一第一面及相对之一第二面的一模塑化合物。至少一晶粒嵌入在该模塑化合物中。该晶粒的一主动面在该模塑化合物之该第二面上暴露。重分布层(RDL)设置在该模塑化合物的第二面上。该RDL具有从该至少一晶粒之数个外缘同心地向外延伸的一扇出区域。密封环设置在该RDL的扇出区域中。
在另一具体实施例中，揭示一种形成装置之方法。该方法包括形成嵌入至少一晶粒的一模塑化合物。该模塑化合物包括第一表面及相对之第二表面。在该模塑化合物的第二表面上面形成具有主要区域及扇出区域的重分布层(RDL)。该扇出区域从该至少一晶粒的数个外缘同心地向外延伸且包围该主要区域。形成该RDL包括同时形成在该主要区域的数个RDL互连及在该扇出区域中的一密封环。
通过参考以下说明及图式可明白揭示于本文之具体实施例的以上及其他优点及特征。此外，应了解，描述于本文之各种具体实施例的特征彼此不互斥而且可存在于各种组合及排列中。
附图说明
图式中，类似的组件大体用相同的组件符号表示于各处不同视图。再者，图式不一定按比例绘制，反而在图解说明本揭示内容之原理时大体加以强调。下文在描述本揭示内容的各种具体实施例时会参考以下图式，其中：
图1显示具有密封环的嵌入式晶圆级球栅数组(eWLB)封装的示范平面图；
图2显示eWLB封装的示范横截面图；
图3显示半导体装置的另一示范平面图；以及
图4显示密封环的示范横截面图。
主要组件符号说明
100 简化上视图、半导体装置、装置
101 半导体装置、装置
110 主要装置区
120 周缘区域、周缘区
150 密封环
150a 第一密封环、内密封环
150b 第二密封环、外密封环
200 简化横截面图
202 晶粒
204 模塑化合物
220 重分布层、RDL、RDL层
220a 扇出区域
221a 最上面RDL层级
221b 最下面RDL层级
222 RDL介电层
224 RDL通孔层级
225 RDL线路层级
230 接触
300 具体实施例
350a 内密封环
350b 外密封环
400 示范横截面图
418a、418c 沟槽
419a、419c 通孔
450 垫层
453a 连续金属结构、最外面金属结构
453b 连续金属结构
453c 连续金属结构、最里面金属结构
460 钝化层。
具体实施方式
数个具体实施例大体系涉及数种半导体封装。更特别的是，数个具体实施例系涉及形成环绕扇出WLP(FOWLP)(例如，嵌入式晶圆级球栅数组(eWLB)封装)之半导体晶粒之周边的密封环。该等半导体封装可并入，例如，消费者电子产品，例如计算机、手机及个人数字助理(PDA)。其他应用并入该等半导体封装也可能很有用。
图1为半导体装置101的简化上视图100。该上视图省略用以嵌入晶粒的模塑化合物。在一具体实施例中，该装置为晶圆级封装(WLP)。例如，该WLP为扇出WLP(FOWLP)，例如eWLB。半导体装置100包括主要装置区110(亦即，在点状方形内)与外框或周缘区域120(亦即，在点状方形与外周缘之间)。该主要装置区包括一或更多晶粒、特征及晶粒的互连。至于该周缘区域，其系包围该主要装置区。例如，该周缘区域在晶圆上用作分离相邻装置的切割道(dicing channel)。该等装置的切单系藉由沿着切割道切割晶圆。
图2为半导体装置101的对应简化横截面图200。如图标，该主要装置区包括嵌入在模塑化合物204中的晶粒(或芯片)202。该晶粒可为射频(RF)集成电路(IC)，内存IC或其他类型的IC。尽管只图示一个晶粒，然而该封装可包括并排安置或垂直堆栈而形成高密度FOWLP(HD-FOWLP)的多个晶粒/芯片。
装置101包括垫层(未图示)。该垫层可包括面向晶粒主动面的第一表面与面向重分布层(RDL)220的第二表面。该垫层可为介电层且包括多个传导柱。每个传导柱可耦合至设置在晶粒的主动面上的接触垫。例如，该传导柱可为铝或铜。在一具体实施例中，在晶粒的主动面与上接触层的第一部份之间可提供传导阻障层(未图示)，例如钽层。例如TaN、Ti或TiN层的其他传导阻障层也可能很有用。
RDL 220包括多个RDL层级。RDL层级的数量可取决于，例如，设计要求。例如，RDL层级包括具有RDL通孔层级(RDL via level)224及RDL线路层级(RDL line level)225的RDL介电层222。RDL介电层222可包括氧化硅或氮化硅。其他合适类型的介电材料也可能很有用。RDL层级的线路层级可称为Mi，在此i为1至x且为x个RDL层级中的第i个RDL层级。RDL层级的通孔层级称为Vi-1，在此i为x个RDL层级中的第i个RDL层级且CA常被表示为第一通孔层级。提供例如接触的互连用于RDL通孔层级224且提供导线用于RDL线路层级225。该等接触及导线例如为用镶嵌或双镶嵌技术形成的铜接触及导线。用于形成例如铜接触及导线之互连或RDL层级之组态的其他合适技术也可能很有用。最上面RDL层级221a的互连都连接至传导柱(柱体)，同时最下面RDL层级221b的互连都经由铝垫连接至接触230，例如焊料凸块。可在该RDL与接触之间提供钝化层(未图示)。
在一具体实施例中，RDL层220经组配成可延伸到晶粒202的外缘之外。例如，RDL层220包括从晶粒202之外周缘同心地向外延伸的扇出区域220a。对于有一个以上并排排列之晶粒的高密度扇出(HD-FO)装置，该扇出区域从最外面晶粒之外缘同心地向外延伸。如图2所示，扇出区域220a提供允许在晶粒周缘外重新路由铜互连及焊球的额外重新路由区(re-routing area)。
在装置100的周缘区120中设置密封环150。在一具体实施例中，密封环150设置在晶粒边缘与锯缝(saw kerf)之间的RDL 220的扇出区域220a中。如图1所示，密封环150包围主要装置区110且与晶粒的外周缘平行。在一具体实施例中，该密封环包括一对密封环，亦即，第一密封环150a与第二密封环150b。例如，平行地配置这一对密封环。第一密封环150a为内密封环而第二密封环150b为外密封环。内密封环150a设置在晶粒220及外密封环150b之间。在一具体实施例中，内密封环150a为与晶粒周缘平行的直线，除了转角区以外。外密封环150b贴近锯缝。外密封环与锯缝的距离约为1微米。如图1所示，内密封环150a经组配成有斜角或倒角(chamfered corner)而不是有尖角的晶粒，例如，90度转角。外密封环150b为与包括尖角之晶粒周缘平行的直线。在如图3所示的另一具体实施例300中，外密封环350b的组配方式与内密封环350a相同。例如，提供用于外密封环350b的斜角或倒角，致使外密封环350b为与内密封环350a平行的直线。提供具有其他组态的密封环可能也很有用。在一具体实施例中，该密封环(亦即，内密封环)与晶粒边缘的距离取决于制程公差(processtolerance)，亦即，组件隔离(assembly isolation)。该组件隔离确保密封环不干涉晶粒边缘。例如，该距离约为1至2微米。
例如，该密封环包括用通孔连接而形成连续金属结构的数个沟槽。在一具体实施例中，该密封环可包括平行设置的多个连续金属结构。图4显示设置在垫层450与钝化层460之间的密封环150之内密封环150a的示范横截面图400。如图示，内密封环150a包括平行设置的3个连续金属结构(453a-c)。最里面金属结构453c贴近晶粒边缘，而最外面金属结构453a贴近外密封环。在一具体实施例中，最外面金属结构453a的相邻沟槽418a用通孔419a连接，而最里面金属结构453c的相邻沟槽418c用多个通孔419c连接。设置在最外面及最里面金属结构之间的金属结构可具有最外面或者是最里面金属结构的组态。在一具体实施例中，密封环150的外密封环可具有与图4之内密封环相同的组态。替换地，外密封环可具有与内密封环不同的组态，例如有3个以下或以上的金属结构。
在一具体实施例中，该等金属结构有相同数量的金属层级。该等金属结构的金属层级的数量对应至RDL层级的数量。例如，该等金属结构的通孔设置在RDL通孔层级中且该等金属结构的沟槽设置在RDL线路层级中。该等金属结构由设置在RDL中之互连的导电材料形成。例如，在同一个RDL层级中的金属结构及互连在使用镶嵌或双镶嵌技术的同一个制程中同时形成。镶嵌技术包括在RDL介电层中形成填满导电材料的开口。用例如研磨法移除多余的导电材料。这在通孔或线路层级中形成通孔或沟槽。双镶嵌技术包括在RDL介电层中形成对应至通孔开口的开口与对应至沟槽的开口，这些开口都填满导电材料。用例如研磨法移除多余的导电材料。这是在单一制程中形成通孔及沟槽。
在一具体实施例中，图2的密封环150与晶粒202耦合至相同的接地。例如，内密封环、外密封环及晶粒耦合至相同的接地。如果半导体装置101有一个以上的晶粒，则所有晶粒耦合至与密封环相同的接地。在一具体实施例中，提供用于晶粒202的晶粒密封件(未图示)。例如，该晶粒密封件设置在包围晶粒之功能区的晶粒周边区。该等晶粒密封件为保护结构，其系保护在晶粒内的内部电路以免晶粒在从晶圆切出或锯出时受损。该晶粒密封件通常由金属线路及连接用传导通孔形成。在一具体实施例中，晶粒密封件、密封环及晶粒耦合至相同的接地。密封环与晶粒如此接地对于排尽在连结各种部件(例如，黏合晶粒)期间所发生的离子污染是重要的，从而防止射频干涉。
可使用本技艺习知的RDL先制方法(RDL-first method)或者是芯片先制方法(chip-first method)制成如图2所示的半导体装置101。RDL先制方法通常以施涂脱模层(release layer)于载具上开始，形成包括密封环的RDL层于脱模层上面，组装数个晶粒(或芯片)于RDL层的第一面上，用环氧树脂模塑化合物重组该等晶粒以形成一晶圆，使载具从晶圆脱模，在RDL层的第二面上形成焊料凸块，以及最后切单晶圆以形成个别半导体封装(装置)。另一方面，芯片先制方法通常以施涂热脱模层(thermal release layer)于载具上开始，组装数个晶粒于载具上，用环氧树脂模塑化合物重组该等晶粒以形成一晶圆，使晶圆从载具脱模，形成有在晶粒主动面上面之第一面的RDL层，该RDL层包括密封环，形成焊料凸块于RDL层的第二面上，以及最后切单晶圆以形成个别半导体封装(装置)。
不论制造方法为何，如在说明图1至图4时所述的密封环可与RDL互连在形成RDL层期间同时形成而不需任何额外制程步骤或微影掩模层。因此，所述的装置不招致额外制程步骤，此制造方法高度兼容且可与现有制程整合。此外，不需要提供用于收纳密封环的额外空间，因为密封环设置在装置的扇出区域中。存在包封晶粒区的密封环防止在切单制程期间裂纹扩展及边缘层离，从而消除芯片封装互动(CPI)可靠性问题。
具体实施例可用其他特定形式体现而不脱离彼等的精神或本质特性。因此，前述具体实施例在各方面都应被视为仅供图解说明而不是限定描述于本文的本发明。因此，本发明的范畴是用随附权利要求书陈明，而不是以上的描述，且旨在涵盖落在权利要求书之意义及等效范围内的所有改变。

Claims (20)

1.一种半导体装置，包含：
至少一晶粒；
一重分布层(RDL)，包含从该至少一晶粒的一外周缘同心地向外延伸的一扇出区域；以及
一密封环，设置在该重分布层的该扇出区域中。
2.如权利要求1所述的半导体装置，其特征在于，该至少一晶粒嵌入于一模塑化合物中。
3.如权利要求1所述的半导体装置，其特征在于，该重分布层包含多个重分布层层级，且其中，一重分布层层级包含具有一重分布层通孔层级及一重分布层线路层级的一重分布层介电层。
4.如权利要求1所述的半导体装置，其特征在于，该密封环包含平行配置的一内密封环与一外密封环。
5.如权利要求4所述的半导体装置，其特征在于，该内密封环设置在该晶粒与该外密封环之间。
6.如权利要求4所述的半导体装置，其特征在于：
该内密封环包含倒角；以及
该外密封环包含尖角。
7.如权利要求4所述的半导体装置，其特征在于，该内密封环及该外密封环包含倒角。
8.如权利要求4所述的半导体装置，其特征在于，该内密封环包含平行配置的多个连续金属结构。
9.如权利要求8所述的半导体装置，其特征在于，该内密封环包含平行配置的3个连续金属结构，且其中，该金属结构中的每一者包含由交替排列的沟槽及通孔组成的一堆栈。
10.如权利要求9所述的半导体装置，其特征在于：
一最外面金属结构的相邻沟槽用一通孔连接；以及
一最里面金属结构的相邻沟槽用多个通孔连接。
11.如权利要求1所述的半导体装置，其特征在于：
该密封环包含具有多个金属层级的一金属结构；
该重分布层包含多个重分布层层级；以及
该多个金属层级对应至该多个重分布层层级。
12.如权利要求1所述的半导体装置，其特征在于，该密封环与该晶粒的该外周缘平行。
13.如权利要求1所述的半导体装置，其特征在于，该至少一晶粒与该密封环耦合至相同的接地。
14.一种装置，包含：
一模塑化合物，具有一第一面及相对的一第二面；
至少一晶粒，嵌入在该模塑化合物中，其中，该晶粒的一主动面在该模塑化合物的该第二面上暴露；
一重分布层(RDL)，设置在该模塑化合物的该第二面上，其中，该重分布层包含从该至少一晶粒的外缘同心地向外延伸的一扇出区域；以及
一密封环，设置在该重分布层的该扇出区域中。
15.如权利要求13所述的装置，其特征在于，该密封环包含平行配置的一内密封环与一外密封环。
16.如权利要求15所述的装置，其特征在于，该内密封环设置在该晶粒与该外密封环之间。
17.如权利要求16所述的装置，其特征在于：
该内密封环包含倒角；以及
该外密封环包含尖角。
18.如权利要求16所述的装置，其特征在于，该内密封环及该外密封环包含倒角。
19.如权利要求15所述的装置，其特征在于，该内密封环包含平行配置的多个连续金属结构。
20.一种形成装置的方法，包含：
形成嵌入至少一晶粒的一模塑化合物，该模塑化合物包含一第一表面及相对的一第二表面；以及
在该模塑化合物的该第二表面上面形成具有一主要区域及一扇出区域的一重分布层(RDL)，该扇出区域从该至少一晶粒的外缘同心地向外延伸且包围该主要区域，其中，形成该重分布层包含同时形成在该主要区域中的重分布层互连及在该扇出区域中的一密封环。
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Cited By (2)

* Cited by examiner, † Cited by third party
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CN109712963A (zh) * 2018-12-29 2019-05-03 上海华力集成电路制造有限公司 Cpi测试结构及基于该结构的失效分析方法
WO2022088745A1 (zh) * 2020-10-28 2022-05-05 长鑫存储技术有限公司 半导体装置及其制作方法

Families Citing this family (4)

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Publication number Priority date Publication date Assignee Title
US10510691B2 (en) * 2017-08-14 2019-12-17 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US11309285B2 (en) * 2019-06-13 2022-04-19 Micron Technology, Inc. Three-dimensional stacking semiconductor assemblies and methods of manufacturing the same
US11456247B2 (en) 2019-06-13 2022-09-27 Nanya Technology Corporation Semiconductor device and fabrication method for the same
US20230307341A1 (en) * 2022-01-25 2023-09-28 Intel Corporation Packaging architecture with edge ring anchoring

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101290912A (zh) * 2007-04-19 2008-10-22 松下电器产业株式会社 半导体装置及其制造方法
CN105261609A (zh) * 2014-07-08 2016-01-20 台湾积体电路制造股份有限公司 半导体器件封装件、封装方法和封装的半导体器件
US20160020181A1 (en) * 2014-07-17 2016-01-21 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4502173B2 (ja) 2003-02-03 2010-07-14 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US8125054B2 (en) 2008-09-23 2012-02-28 Texas Instruments Incorporated Semiconductor device having enhanced scribe and method for fabrication
US20120286397A1 (en) * 2011-05-13 2012-11-15 Globalfoundries Inc. Die Seal for Integrated Circuit Device
US10453785B2 (en) 2014-08-07 2019-10-22 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming double-sided fan-out wafer level package
US10566289B2 (en) * 2015-10-13 2020-02-18 Samsung Electronics Co., Ltd. Fan-out semiconductor package and manufacturing method thereof
US9904776B2 (en) * 2016-02-10 2018-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor pixel array and methods of forming same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101290912A (zh) * 2007-04-19 2008-10-22 松下电器产业株式会社 半导体装置及其制造方法
CN105261609A (zh) * 2014-07-08 2016-01-20 台湾积体电路制造股份有限公司 半导体器件封装件、封装方法和封装的半导体器件
US20160020181A1 (en) * 2014-07-17 2016-01-21 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109712963A (zh) * 2018-12-29 2019-05-03 上海华力集成电路制造有限公司 Cpi测试结构及基于该结构的失效分析方法
WO2022088745A1 (zh) * 2020-10-28 2022-05-05 长鑫存储技术有限公司 半导体装置及其制作方法

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