KR101515275B1 - ３ｄｉｃ 적층 디바이스 및 제조 방법 - Google Patents

３ｄｉｃ 적층 디바이스 및 제조 방법 Download PDF

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KR101515275B1
KR101515275B1 KR1020130003844A KR20130003844A KR101515275B1 KR 101515275 B1 KR101515275 B1 KR 101515275B1 KR 1020130003844 A KR1020130003844 A KR 1020130003844A KR 20130003844 A KR20130003844 A KR 20130003844A KR 101515275 B1 KR101515275 B1 KR 101515275B1
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semiconductor die
die
semiconductor
encapsulant
external connectors
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KR1020130003844A
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English (en)
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KR20140001085A (ko
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징쳉 린
첸화 여
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타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드
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Abstract

반도체 디바이스들을 삼차원으로 적층하기 위한 방법 및 시스템이 제공된다. 실시예에서 두 개 이상의 반도체 다이들은 캐리어에 부착되고 캡슐화된다. 두 개 이상의 반도체 다이들의 연결부들은 노출되고, 두 개 이상의 반도체 다이들은 시닝되어 반대측면상에서 연결부들을 형성할 수 있다. 그 후 추가적인 반도체 다이들은 오프셋 또는 오버행 위치로 배치될 수 있다.

Description

３ＤＩＣ 적층 디바이스 및 제조 방법{3DIC STACKING DEVICE AND METHOD OF MANUFACTURE}
본 출원은 "3DIC Stacking Device and Method of Manufacture"이라는 명칭으로 2012년 6월 27일에 출원된 미국 가특허 출원 제61/665,123호의 우선권을 청구하며, 이 가특허 출원은 참조로서 본 명세서 내에 병합된다.
집적 회로(IC)의 발명때문에, 반도체 산업은 다양한 전자 컴포넌트들(즉, 트랜지스터, 다이오드, 저항기, 캐패시터 등)의 집적 밀도에서의 끊임없는 향상으로 인해 급격한 성장을 경험해 왔다. 대부분, 이러한 집적 밀도에서의 향상은 최소 피처 크기의 반복된 감축으로부터 유발되었으며, 이것은 주어진 면적내로 보다 많은 컴포넌트들이 집적되도록 해준다.
집적된 컴포넌트들에 의해 점유된 용적은 본질적으로 반도체 웨이퍼의 표면상에 대한 것이라는 점에서 이러한 집적도 향상은 본질적으로 성질상 이차원(2D)적인 것이다. 비록 리소그래피에서의 극적인 향상은 2D IC 형성에서의 상당한 향상을 불러일으켰지만, 이차원에서 달성될 수 있는 밀도에 대해서는 물리적 한계들이 존재한다. 이러한 한계들 중 하나는 이러한 컴포넌트들을 제조하는데 필요한 최소 크기이다. 또한, 하나의 칩내에 보다 많은 디바이스들이 투입될 때에는, 보다 복잡한 설계들이 요구된다.
회로 밀도를 한층 더 증가시키려는 시도로, 삼차원(3D) IC가 연구되어 왔다. 3D IC의 일반적인 형성 공정에서는, 두 개의 다이들이 함께 접합되고 전기적 연결부들이 기판상의 접촉 패드들과 각각의 다이 사이에서 형성된다. 예를 들어, 한가지 시도는 두 개의 다이들을 서로 위아래로 접합시키는 것을 포함한다. 그런 후 적층된 다이들은 캐리어 기판에 접합되고 배선 접합은 각각의 다이상의 접촉 패드들을 캐리어 기판상의 접촉 패드들에 전기적으로 결합시킨다.
이하에서는 본 발명개시의 실시예들의 실시 및 이용을 자세하게 설명한다. 그러나, 본 실시예들은 폭넓게 다양한 특정 환경들에서 구체화될 수 있는 많은 적용가능한 발명적 개념들을 제공한다는 것을 알아야 한다. 설명하는 특정한 실시예들은 본 실시예들을 실시하고 이용하는 특정한 방법들에 대한 단순한 예시에 불과하며, 본 발명개시의 범위를 한정시키려는 것은 아니다.
예시적인 실시예들을 상세하게 다루기 전에, 실시예들의 양태들 및 그 유리한 특징들을 개괄적으로 다룰 것이다. 아래에서 설명될 바와 같이, 여기서 개시된 실시예들은 최상단 다이 오버행(overhang) 문제와 관련된 문제들을 개선시키는 방법 및 구조물을 제공한다. 예를 들어, Co(CoS)(chip on (chip on substrate))는 낮은 수율과 비교적 높은 비용을 경험할 수 있다. (CoW)oS((Chip on wafer) on substrate) 기술들은 오버행하는 최상단 다이에 대해서는 실용적이지 않다. (CoC)oS((chip on chip) on substrate)는 Co(CoS)보다 높은 비용을 경험하고 (CoW)oS보다 낮은 수율을 경험한다.
실시예에 따르면, 제1 캐리어 웨이퍼 상에 하나 이상의 바닥부 다이들을 배치시키는 단계 및 하나 이상의 바닥부 다이들상의 전기적 접촉부들이 노출되도록 하면서 하나 이상의 바닥부 다이들 사이에 제1 몰딩 화합물을 형성하는 단계를 포함한 디바이스를 형성하기 위한 방법이 제공된다. 하나 이상의 바닥부 다이들과 제1 몰딩 화합물은 제2 캐리어 웨이퍼에 부착되고, 하나 이상의 바닥부 다이들을 관통하여 형성된 쓰루 비아를 노출시키도록 하나 이상의 바닥부 다이들은 시닝된다. 쓰루 비아들에 대한 전기적 접촉부들이 하나 이상의 바닥부 다이들의 후면을 따라 형성되며, 하나 이상의 최상단 다이들은 하나 이상의 바닥부 다이들에 부착된다.
또 다른 실시예에 따르면, 제1 외부 접촉부들을 포함한 제1 반도체 다이를 캐리어에 부착하는 단계, 및 제2 외부 접촉부들을 포함한 제2 반도체 다이를 캐리어에 부착하는 단계를 포함한 반도체 디바이스를 제조하는 방법이 제공된다. 제1 반도체 다이와 제2 반도체 다이는 봉지재로 캡슐화되고, 봉지재의 일부분은 제거되어 제1 외부 접촉부들과 제2 외부 접촉부들을 노출시킨다. 제1 반도체 다이 내의 제1 쓰루 기판 비아들 및 제2 반도체 다이 내의 제2 쓰루 기판 비아들을 형성하기 위해 제1 반도체 다이와 제2 반도체 다이는 시닝된다. 제3 반도체 다이가 제1 쓰루 기판 비아들에 전기적으로 연결되고 제4 반도체 다이가 제2 쓰루 기판 비아들에 전기적으로 연결된다.
또다른 실시예에 따르면, 제1 봉지재에 의해 캡슐화된 제1 반도체 다이를 포함한 반도체 디바이스가 제공된다. 적어도 하나의 쓰루 기판 비아는 제1 반도체 다이의 적어도 일부분을 관통하여 연장하고 제1 반도체 다이의 제1 측면상에서 노출되며, 제1 외부 커넥터들은 제1 반도체 다이의 제2 측면상에 위치한다. 제3 반도체 다이는 적어도 하나의 쓰루 기판 비아와 전기적으로 연결되어 있고, 제3 반도체 다이는 봉지재 위에서 연장한다.
일반적인 관점에서, 도시된 실시예들은 최상단 다이 오버행 또는 바닥부 다이(w/TV 다이)보다 큰 최상단 다이를 허용하는 CoW 공정을 제공한다. 실시예들은 또한 CoWoS 공정에 대한 솔루션을 제공할 수 있고 보다 낮은 조립 비용을 얻기 위해 잠재적으로 기판을 스킵할 수 있다. 실시예들은 또한 BGA 기술들을 활용함으로써 보다 낮은 폼 팩터를 나타낼 수 있다.
본 발명과, 본 발명의 장점들의 보다 완벽한 이해를 위해, 이제부터 첨부 도면들을 참조하면서 이하의 상세한 설명에 대해 설명을 한다.
도 1 내지 도 10d는 실시예에 따른 반도체 디바이스들을 연결시키기 위한 제조 공정을 나타낸다.
도 11 내지 도 13d는 실시예에 따른 반도체 디바이스들을 연결시키기 위한 제조 공정의 대안적인 실시예를 나타낸다.
여러 도면들에서의 대응하는 번호들 및 심볼들은 이와 다르게 언급되지 않는 한 일반적으로 대응하는 부분들을 가리킨다. 실시예들의 관련된 양태들을 명확하게 설명하기 위해 도면들이 작도되어 있으며, 도면들은 반드시 실척도로 도시되어 있지는 않다.
이제 도 1 내지 도 10b를 참조하면, 제1 실시예가 제공된다. 도 1은 제1 접착제(103)가 도포되어 있는 제1 캐리어 웨이퍼(101)를 나타낸다. 제1 캐리어 웨이퍼(101)는, 예컨대, 유리, 실리콘 산화물, 알루미늄 산화물 등을 포함할 수 있고, 약 12밀(mil)보다 큰 두께를 가질 수 있다. 대안적으로, 제1 캐리어 웨이퍼(101)는 적절한 캐리어 테이프를 포함할 수 있다. 캐리어 테이프가 활용되는 경우, 캐리어 테이프는 통상적으로 알려진 블루 테이프일 수 있다.
제1 접착제(103)는 제1 캐리어 웨이퍼(101)를 제1 반도체 다이(201) 및 제2 반도체 다이(203)(이것들은 도 1에서는 도시되어 있지 않지만 도 2와 관련하여 아래에서 설명되고 도시된다)와 같은 다른 디바이스들에 접합시키기 위해 이용될 수 있다. 실시예에서, 접착제는 열적 릴리즈 막(thermal release film)일 수 있다. 대안적으로, 제1 접착제(103)는 UV 광에 노출될 때 자신의 접착 특성을 손실하는 자외선(UV) 아교일 수 있다. 임의의 적절한 접착제가 활용될 수 있으며, 이러한 접착제들 모두는 본 실시예들의 범위내에 완전히 포함되는 것으로 한다.
도 2는 제1 접착제로 제1 캐리어 웨이퍼(101)에 부착된 제1 반도체 다이(201)(또는 제1 바닥부 다이)와 제2 반도체 다이(203)(또는 제2 바닥부 다이)를 나타낸다. 제1 반도체 다이(201)와 제2 반도체 다이(203) 모두는 기판(205), 쓰루 기판 비아(through substrate via; TSV) 개구들(207), 능동 디바이스들(209), 금속층들(211), 접촉 패드들(213), 제1 패시베이션층들(215), 및 제1 외부 커넥터들(217)을 포함할 수 있다. 하지만, 제1 반도체 다이(201)와 제2 반도체 다이(203)가 유사한 피처들을 갖는 것으로서 도시되어 있지만, 이것은 예시에 불과하며 본 실시예들을 한정시키려는 의도가 있는 것은 아니며, 따라서 제1 반도체 다이(201)와 제2 반도체 다이(203)에 대해 의도된 희망하는 기능적 능력들을 충족시키기 위해 제1 반도체 다이(201)와 제2 반도체 다이(203)는 유사한 구조들을 갖거나 또는 상이한 구조들을 가질 수 있다.
추가적으로, 도 2에서는 단일의 제1 반도체 다이(201)와 단일의 제2 반도체 다이(203)가 도시되고 있지만, 이것은 예시에 불과할 뿐이며, 본 실시예들을 한정시키려는 의도가 있는 것은 아니다. 이보다는, 단일의 제1 반도체 다이(201)는 최종적으로 내부에서 형성되어 함께 적층된 쓰루 기판 비아(TSV; 도 7과 관련하여 아래에서 자세하게 논의됨)들을 가질 하나 이상의 제1 반도체 다이들(201)을 나타낼 수 있다. 마찬가지로, 단일의 제2 반도체 다이(203)는 최종적으로 내부에서 형성되어 함께 적층된 TSV들을 가질 하나 이상의 제2 반도체 다이들(203)을 나타낼 수 있다. 임의의 적절한 갯수의 제1 반도체 다이들(201)과 제2 반도체 다이들(203)이 대안적으로 활용될 수 있으며, 이러한 모든 조합들은 본 실시예들의 범위내에 완전히 포함되는 것으로 한다.
기판들(205)은 도핑 또는 비도핑된 벌크 실리콘, 또는 SOI(silicon-on-insulator) 기판의 활성층을 포함할 수 있고 제1 측면(202)과 제2 측면(204)을 가질 수 있다. 일반적으로, SOI 기판은 실리콘, 게르마늄, 실리콘 게르마늄, SOI, SGOI(silicon germanium on insulator), 또는 이들의 조합과 같은 반도체 물질층을 포함한다. 이용될 수 있는 다른 기판들은 다층화된 기판들, 구배 기판들, 또는 하이브리드 배향 기판들을 포함한다.
쓰루 기판 비아(TSV) 개구들(207)이 기판들(205)의 제1 측면(202) 내에 형성될 수 있다. TSV 개구들(207)은 적절한 포토레지스트(미도시됨)를 도포하여 현상하고, 노출된 기판(205)을 희망하는 깊이까지 제거함으로써 형성될 수 있다. TSV 개구들(207)은 적어도 기판들(205) 내에 및/또는 그 위에 형성된 능동 디바이스들(209)보다 더 멀리 기판들(205) 내로 확장하도록 형성될 수 있고, 기판들(205)의 최종적인 희망하는 높이보다 큰 깊이까지 확장할 수 있다. 따라서, 이러한 깊이는 제1 반도체 다이(201)와 제2 반도체 다이(203)의 총체적인 설계들에 의존적이지만, 이 깊이는, 기판들(205)상의 능동 디바이스들(209)로부터 약 100㎛의 깊이와 같이, 기판들(205)상의 능동 디바이스들(209)로부터 약 20㎛와 약 200㎛ 사이에 있을 수 있다.
TSV 개구들(207)이 기판들(205) 내에서 형성되면, TSV 개구들(207)은 라이너(도 2에서는 독자적으로 도시되어 있지 않음)에 대해 라이닝(line)될 수 있다. 라이너는, 예컨대 TEOS(tetraethylorthosilicate) 또는 실리콘 질화물로부터 형성된 산화물일 수 있지만, 임의의 적절한 유전체 물질이 대안적으로 이용될 수 있다. 라이너는 플라즈마 강화된 화학적 기상 증착(plasma enhanced chemical vapor deposition; PECVD) 공정을 이용하여 형성될 수 있지만, 물리적 기상 증착 또는 열 공정과 같은 다른 적절한 공정들이 대안적으로 이용될 수 있다. 추가적으로, 라이너는 약 1㎛와 같이, 약 0.1㎛와 약 5㎛ 사이의 두께로 형성될 수 있다.
라이너가 TSV 개구들(207)의 측벽들과 바닥부를 따라 형성되면, 배리어층(독자적으로 도시되어 있지 않음)이 형성될 수 있고 TSV 개구들(207)의 나머지는 제1 도전성 물질(219)로 충전될 수 있다. 제1 도전성 물질(219)은 구리를 포함할 수 있지만, 알루미늄, 합금들, 도핑된 폴리실리콘, 이들의 조합 등과 같은 다른 적절한 물질들이 대안적으로 활용될 수 있다. 제1 도전성 물질(219)은 구리를 시드층(미도시됨)상에서 전기도금하고, TSV 개구들(207)을 충전 및 과충전시킴으로써 형성될 수 있다. TSV 개구들(207)이 충전되면, TSV 개구들(207)의 외부에 있는 과잉 라이너, 배리어층, 시드층, 및 제1 도전성 물질(219)은 화학적 기계적 폴리싱(chemical mechanical polishing; CMP)과 같은 평탄화 공정을 통해 제거될 수 있으나, 임의의 적절한 제거 공정이 이용될 수 있다.
도 2에서 능동 디바이스들(209)은 각각의 기판들(205)상에서 단일의 트랜지스터로서 나타난다. 하지만, 본 발명분야의 당업자는 제1 반도체 다이(201)와 제2 반도체 다이(203)에 대한 설계의 희망하는 구조적 및 기능적 요건들을 생성하기 위해 캐패시터, 저항기, 인덕터 등과 같은 다양한 폭의 수동 디바이스들 및 능동 디바이스들이 이용될 수 있다는 것을 알 것이다. 능동 디바이스들(209)은 임의의 적절한 방법들을 이용하여 기판들(205)의 제1 측면(202) 내에서 또는 이와 달리 제1 측면(202)상에서 형성될 수 있다.
금속층들(211)은 기판들(205)의 제1 측면(202) 및 능동 디바이스들(209) 위에서 형성되며, 다양한 능동 디바이스들(209)을 연결시켜서 기능적 회로를 형성하도록 설계된다. 도 2에서 금속층들(211)은 단일층의 유전체 및 상호연결부들로서 도시되지만, 금속층들(211)은 교호하는 유전체 및 도전성 물질층들로 형성되고, 이것은 (증착, 다마신, 듀얼 다마신 등과 같은) 임의의 적절한 공정을 통해 형성될 수 있다. 실시예에서는 적어도 하나의 층간 유전체층(interlayer dielectric layer; ILD)에 의해 기판들(205)로부터 분리된 네 개의 금속층들이 존재할 수 있지만, 금속층들(211)의 정확한 갯수는 제1 반도체 다이(201) 및 제2 반도체 다이(203)의 설계에 따라 좌우된다.
접촉 패드들(213)이 금속층들(211)과 전기적 접촉을 이루면서 금속층들(211) 위에서 형성될 수 있다. 접촉 패드들(213)은 알루미늄을 포함할 수 있지만, 구리와 같은 다른 물질들이 대안적으로 이용될 수 있다. 접촉 패드들(213)은 스퍼터링과 같은 증착 공정을 이용하여 물질층(미도시됨)을 형성함으로써 형성될 수 있고, 그런 후 이 물질층의 일부분들은 (포토리소그래피 마스킹 및 에칭과 같은) 적절한 공정을 통해 제거되어 접촉 패드들(213)을 형성할 수 있다. 하지만, 접촉 패드들(213)을 형성하기 위해 임의의 다른 적절한 공정이 활용될 수 있다. 접촉 패드들(213)은 약 1.45㎛와 같이, 약 0.5㎛과 약 4㎛ 사이의 두께를 갖도록 형성될 수 있다.
제1 패시베이션층들(215)은 기판들(205)상의 금속층들(211)과 접촉 패드들(213) 위에서 형성될 수 있다. 제1 패시베이션층들(215)은 실리콘 산화물, 실리콘 질화물, 탄소도핑된 산화물과 같은 저 k(low-k) 유전체, 탄소도핑된 다공성 실리콘 이산화물과 같은 극저 k(extremely low k) 유전체, 이들의 조합 등과 같은 하나 이상의 적절한 유전체 물질들로 이루어질 수 있다. 제1 패시베이션층들(215)은 화학적 기상 증착(CVD)과 같은 공정을 통해 형성될 수 있지만, 임의의 적절한 공정이 활용될 수 있으며, 약 9.25KÅ와 같이, 약 0.5㎛와 약 5㎛ 사이의 두께를 가질 수 있다.
추가적인 보호를 제공하기 위해 제2 패시베이션층들(1002)(명료성을 위해 도 2에서는 독자적으로 도시되어 있지 않지만, 아래의 도 10b와 관련한 확대도에서는 도시됨)이 제1 패시베이션층들(215) 위에 형성될 수 있다. 실시예에서, 제2 패시베이션층들(1002)은 폴리이미드와 같은 폴리머로부터 형성될 수 있거나, 또는 대안적으로 제1 패시베이션층들(215)과 유사한 물질(예컨대, 실리콘 산화물, 실리콘 질화물, 저 k 유전체, 극저 k 유전체, 이들의 조합 등)로 형성될 수 있다. 제2 패시베이션층들(1002)은 약 5㎛와 같이, 약 2㎛와 약 15㎛ 사이의 두께를 갖도록 형성될 수 있다.
인쇄 회로 보드 또는 예컨대 플립칩 배열의 다른 반도체 다이들과 같은 외부 디바이스들(도 2에서는 미도시됨)과 접촉 패드들(213) 사이에 접촉용 도전성 영역들을 제공하기 위해 제1 외부 커넥터들(217)이 형성될 수 있다. 제1 외부 커넥터들(217)은 또한 화학적 기계적 폴리싱(CMP)과 같은 평탄화 공정에서의 버퍼로서 활용될 수 있다. 실시예에서, 제1 외부 커넥터들(217)은 도전성 기둥들일 수 있고, 초기에 제1 패시베이션층들(215) 및 제2 패시베이션층들(1002) 위에서 약 10㎛와 같이, 약 5㎛와 약 20㎛ 사이의 두께까지 포토레지스트(미도시됨)를 형성함으로써 형성될 수 있다. 포토레지스트는 제2 패시베이션 층들(1002)과 제1 패시베이션 층들(215)의 일부분들(이 노출된 부분들을 통해 도전성 기둥들은 연장할 것이다)을 노출시키도록 패턴화된다. 포토레지스트가 패턴화되면, 그 후 포토레지스트는 제2 패시베이션 층들(1002)과 제1 패시베이션 층들(215)의 희망하는 부분들을 제거하기 위한 마스크로서 이용될 수 있고, 이로써 도전성 기둥들이 접촉할 아래의 접촉 패드들(213)의 부분들을 노출시킨다.
접촉 패드들(213)이 노출되면, 제1 UBM 층들(1003)(도 2에서는 독자적으로 도시되어 있지 않지만, 아래의 도 10b와 관련한 확대도에서는 도시됨)이 접촉 패드(105)와 전기적 접촉을 이루면서 형성될 수 있다. 제1 UBM 층들(1003)은 티타늄층, 또는 니켈층과 같은, 도전성 물질층을 포함할 수 있다. 제1 UBM 층들(1003)은 다중 서브층들(미도시됨)을 포함할 수 있다. 본 발명분야의 당업자는, 크롬/크롬 구리 합금/구리/금의 배열, 티타늄/티타늄 텅스텐/구리의 배열, 또는 구리/니켈/금의 배열과 같은, 제1 UBM 층들(1003)의 형성에 적절한 수 많은 적절한 물질 및 층 배열이 존재한다는 것을 알 것이다. 제1 UBM 층들(1003)을 위해 이용될 수 있는 임의의 적절한 물질들 또는 층들은 본 실시예들의 범위 내에 완전히 포함되는 것으로 한다. 제1 UBM 층들(1003)은 희망하는 물질들에 따라, 스퍼터링, 증착, 또는 PECVD 공정들과 같은 공정들을 이용하여 생성될 수 있다. 제1 UBM 층들(1003)은 약 5㎛와 같이, 약 0.7㎛와 약 10㎛ 사이의 두께를 갖도록 형성될 수 있다.
제1 UBM 층들(1003)이 형성된 후, 도전성 기둥들은 제1 패시베이션층들(215), 제2 패시베이션층들(1002), 및 포토레지스트 모두의 개구들 내에서 형성될 수 있다. 도전성 기둥들은 구리와 같은 도전성 물질로부터 형성될 수 있지만, 니켈, 금, 또는 금속 합금, 이들의 조합 등과 같은 다른 도전성 물질들이 또한 이용될 수 있다. 추가적으로, 도전성 기둥들은 전기도금과 같은 공정을 이용하여 형성될 수 있는데, 이 때 전류는 도전성 기둥들이 형성되기를 희망하는 접촉 패드들(213)의 도전부분들에 흐르고, 접촉 패드들(213)은 용액에 침지된다. 용액과 전류는 개구들 내에서 예컨대 구리를 침전시켜서 포토레지스트, 제1 패시베이션층들(215), 및 제2 패시베이션층들(1002)의 개구들을 충전 및/또는 과충전시키고, 이로써 도전성 기둥들을 형성한다. 그런 후 개구들 외부에 있는 과잉 도전성 물질은 예컨대 화학적 기계적 폴리싱(CMP)을 이용하여 제거될 수 있다.
도전성 기둥들이 형성된 후, 포토레지스트는 애싱(ashing)과 같은 공정을 통해 제거될 수 있고, 이로써 포토레지스트의 온도는 포토레지스트가 분해되고 제거될 수 있을 때 까지 증가한다. 포토레지스트의 제거 후, 도전성 기둥들은 제1 패시베이션층들(215) 및 제2 패시베이션층들(1002)로부터 약 40㎛와 같이, 약 5㎛와 약 50㎛ 사이의 제1 거리만큼 멀리 연장한다. 택일적 사항으로서, 배리어층(미도시됨)이 예컨대 무전해 도금에 의해 도전성 기둥들 위에서 형성될 수 있고, 배리어층은 니켈, 바나듐(V), 크롬(Cr), 및 이들의 조합으로 형성될 수 있다.
하지만, 본 발명분야의 당업자라면, 도전성 기둥들을 형성하기 위한 상술한 공정은 단순히 하나의 설명예에 불과하며, 실시예들을 바로 그 공정으로 제한시키는 것을 의미하지 않는다는 것을 알 것이다. 이보다는, 설명한 공정은 단지 예시적인 것으로서 의도된 것이며, 제1 외부 커넥터들(217)을 형성하기 위한 임의의 적절한 공정이 대안적으로 활용될 수 있다. 예를 들어, 제1 패시베이션층들(215)과 제2 패시베이션층들(1002)을 최종적인 두께보다 큰 두께로 형성하는 것, 제1 패시베이션층들(215)과 제2 패시베이션층들(1002)의 개구 내에 도전성 기둥들을 형성하는 것, 및 그 후 도전성 기둥들이 제1 패시베이션층들(215)과 제2 패시베이션층들(1002)로부터 멀리 연장하도록 제1 패시베이션층들(215)과 제2 패시베이션층들(1002)의 상단부를 제거하는 것이 또한 활용될 수 있다. 적절한 모든 공정들이 본 실시예들의 범위 내에 완전히 포함되는 것으로 한다.
택일적 사항으로서, 제1 외부 커넥터들(217)을 보호하기 위해 보호층(221)이 제1 외부 커넥터들(217) 위에서 형성될 수 있다. 실시예에서 보호층(221)은 폴리머층과 같은 보호층일 수 있지만, 임의의 적절한 물질이 대안적으로 활용될 수 있다. 보호층(221)은 약 8㎛와 같이, 약 5㎛과 약 15㎛ 사이의 두께를 갖도록 형성될 수 있다.
도 3은 제1 반도체 다이(201)와 제2 반도체 다이(203)가 제1 캐리어 웨이퍼(101)에 부착된 상태로 남아있도록 하면서 제1 반도체 다이(201)와 제2 반도체 다이(203)를 캡슐화하기 위한 제1 몰딩 공정을 나타낸다. 실시예에서, 제1 반도체 다이(201)와 제2 반도체 다이(203)는 예컨대 몰딩 디바이스(미도시됨)를 이용하여 캡슐화될 수 있다. 예를 들어, 제1 반도체 다이(201), 제2 반도체 다이(203), 및 제1 캐리어 웨이퍼(101)는 몰딩 디바이스의 공동(cavity) 내에 배치될 수 있고, 이러한 공동은 밀봉될 수 있다. 봉지재(encapsulant)(301)는 공동이 밀봉되기 전에 공동 내에 위치할 수 있거나 또는 이와 달리 주입 포트를 통해 공동 내로 주입될 수 있다. 실시예에서, 봉지재(301)는 폴리이미드, PPS, PEEK, PES, 내열성 수정 수지, 이들의 조합 등과 같은 몰딩 화합물 수지일 수 있다.
봉지재(301)가 제1 반도체 다이(201)와 제2 반도체 다이(203)를 캡슐화하도록 봉지재(301)가 공동 내로 배치되면, 봉지재(301)를 최적의 보호를 위해 굳게하도록 봉지재(301)는 경화될 수 있다. 정확한 경화 공정은 봉지재(301)용으로 선택된 특정 물질에 적어도 부분적으로 의존하지만, 몰딩 화합물이 봉지재(301)로서 선택된 실시예에서, 경화는 봉지재(301)를 약 600초와 같이, 약 60초 내지 약 3000초 동안에, 약 125℃와 같이, 약 100℃와 약 130℃ 사이까지 가열시키는 것과 같은 공정을 통해 일어날 수 있다. 추가적으로, 경화 공정을 보다 잘 제어하기 위해 개시자들 및/또는 촉매들이 봉지재(301) 내에 포함될 수 있다.
하지만, 본 발명분야의 당업자라면, 상술한 경화 공정은 단순히 예시적인 공정에 불과하며, 이것은 본 실시예들을 제한시키려는 의미는 아니라는 것임을 알 것이다. 대안적으로 봉지재(301)를 상온에서도 경화시킬 수 있도록 해주는 방사선조사와 같은 다른 경화 공정들이 이용될 수 있다. 임의의 적절한 경화 공정이 이용될 수 있으며, 이러한 공정들 모두는 여기서 논의된 실시예들의 범위 내에 완전히 포함되는 것으로 한다.
도 4는 제1 외부 커넥터들(217)을 노출시키기 위한 봉지재(301)의 제거를 나타낸다. 실시예에서 봉지재(301)의 제거는 예컨대 화학적 기계적 폴리싱(CMP) 공정을 이용하여 수행될 수 있고, 여기서는 봉지재(301)와 상호작용을 해서 제1 외부 커넥터들(217)이 노출될 때 까지 봉지재(301)를 그라인딩하여 제거하도록 하기 위해 연마재와 에천트가 봉지재(301)에 도포되고 폴리싱된다. 대안적으로, 봉지재(301)를 제거하고 봉지재(301)를 제1 외부 커넥터들(217)과 함께 평탄화하기 위해 하나 이상의 에칭 공정들이 활용될 수 있다.
도 5는 제1 반도체 다이(201)와 제2 반도체 다이(203)로부터의 제1 캐리어 웨이퍼(101)의 제거를 나타낸다. 제1 캐리어 웨이퍼(101)의 제거는 활용되는 제1 접착제(103)의 유형에 적어도 부분적으로 좌우되지만, 제1 접착제(103)가 열적 릴리즈 막인 실시예에서, 제1 접착제(103)는 제1 반도체 다이(201)와 제2 반도체 다이(203)로부터 제1 캐리어 웨이퍼(101)를 떼어내기 위해 약 200℃보다 큰 온도까지 가열될 수 있다. 제1 접착제(103)가 UV 아교인 경우 제1 접착제(103)를 UV 광으로 조사시키는 것과 같은, 제1 캐리어 웨이퍼(101)를 제거하기 위한 임의의 다른 적절한 방법이 대안적으로 활용될 수 있다.
도 6은 제2 접착제(603)를 활용하여 봉지재(301)와 제1 외부 커넥터들(217)을 제2 캐리어 웨이퍼(601)에 부착시키는 것을 나타낸다. 실시예에서 제2 캐리어 웨이퍼(601)와 제2 접착제(603)는 각각 유리 캐리어 웨이퍼와 열적 릴리즈 막과 같은 것인, 제1 캐리어 웨이퍼(101)와 제1 접착제(103)와 유사할 수 있다. 하지만, 이와 달리 제2 캐리어 웨이퍼(601)와 제2 접착제(603)는 제1 캐리어 웨이퍼(101)와 제1 접착제(103)와 상이할 수 있다.
도 7은 TSV 개구들(207)을 노출시키고 TSV들(701)을 형성하기 위한 기판들(205)의 제2 측면(204)의 일부분 및 봉지재(301)의 제거를 나타낸다. 실시예에서, 기판들(205)의 제2 측면(204)의 일부분 및 봉지재(301) 모두를 제거하고 또한 기판들(205)의 제2 측면(204) 및 봉지재(301)를 평탄화하기 위해 기판들(205)의 제2 측면(204) 및 봉지재(301)는 예컨대 CMP 및 그라인딩 공정들을 이용하여 제거될 수 있다. 대안적으로, 봉지재(301)를 제거하고 TSV 개구들(207)을 노출시켜서 TSV(701)를 형성하기 위해 하나 이상의 에칭 공정들 또는 다른 제거 공정들이 이용될 수 있다.
도 8은 기판(205)의 제2 측면(204)상에서의 제1 재분배층(RDL)(801) 및 제2 외부 커넥터들(803)의 형성을 나타낸다. 제1 RDL(801)은 알루미늄, 구리, 텅스텐, 티타늄, 및 이들의 조합과 같은 금속들로 형성된 두 개의 도전층들을 포함할 수 있다. 제1 RDL(801)은 화학적 기상 증착을 통해 금속층들을 증착하고 그런 후 희망하지 않는 부분들을 에칭하여 제1 RDL(801)을 남겨둠으로써 형성될 수 있다. 제1 RDL(801)은 약 5㎛와 같이, 약 2㎛와 약 30㎛ 사이의 두께를 가질 수 있다. 하지만, 잘 알려진 다마신 공정과 같은, 다른 공정 및 물질들이 제1 RDL(801)을 형성하기 위해 대안적으로 이용될 수 있다.
택일적으로서, 실시예에서, 제1 RDL(801)은 제1 반도체 다이(201) 및 제2 반도체 다이(203) 위 뿐만이 아니라, 봉지재(301) 위에서 형성될 수 있다. 제1 RDL(801)을 봉지재(301) 위에 형성함으로써, 제1 반도체 다이(201) 및 제2 반도체 다이(203)를 위한 팬 아웃(fan-out) 영역은 제1 반도체 다이(201) 및 제2 반도체 다이(203)의 경계들을 넘어 연장할 수 있는데, 이것은 또한 입력/출력(I/O) 카운트들에서의 증가를 가능하게 해준다.
제2 외부 커넥터들(803)은 마이크로범프들 또는 제어된 붕괴형 칩 연결부(C4) 범프들과 같은 접촉 범프들일 수 있고, 주석과 같은 물질, 또는 은 또는 구리와 같은 다른 적절한 물질들을 포함할 수 있다. 제2 외부 커넥터들(803)이 주석 솔더 범프들인 실시예에서, 제2 외부 커넥터들(803)은 전기도금, 증착, 프린팅, 솔더 전사, 볼 배치 등과 같은 임의의 적절한 방법을 통해 약 100㎛의 바람직한 두께로 주석층을 초기에 형성함으로써 형성될 수 있다. 주석층이 구조물상에서 형성되면, 물질을 원하는 범프 형상으로 쉐이핑하기 위해 리플로우가 수행된다.
도 9a는 제3 반도체 다이(901)(또는 제3 최상단 다이)와 제4 반도체 다이(903)(또는 제4 최상단 다이)가 제2 반도체 다이(203)와 제1 반도체 다이(201)에 각각 부착된 것을 나타낸다. 실시예에서, 제3 반도체 다이(901) 및 제4 반도체 다이(903)는 제1 반도체 다이(201) 및 제2 반도체 다이(203)와 유사한 능동 디바이스들, 금속층들, 및 접촉 패드들(이것들 모두는 명확성을 위해 도시되지는 않는다)을 포함할 수 있지만, 이것들은 이와 다른 구조물들을 또한 포함할 수 있고 자신들이 부착되어 있는 반도체 다이들과 상이하거나 또는 상보적인 기능들을 수행할 수 있다.
실시예에서, 제3 반도체 다이(901)는 아래에 있는 제2 반도체 다이(203)보다 클 수 있다. 예를 들어, 제2 반도체 다이(203)가 약 8㎜와 같은, 약 3㎜와 약 14㎜ 사이의 제1 길이(l1)를 가질 수 있는 실시예에서, 제3 반도체 다이(901)는 약 10㎜와 같은, 약 1㎜와 약 20㎜ 사이의 제2 길이(l2)를 가질 수 있다. 제3 반도체 다이(901)는, 제2 반도체 다이(203)보다 큰 치수들을 가짐으로써 제2 반도체 다이(203)를 오버행(overhang)할 수 있다. 하지만, 제2 반도체 다이(203) 및 제3 반도체 다이(901)에 대한 지지 및 연결성을 제공하기 위해 봉지재(301)와 RDL(801)이 활용될 수 있다.
하지만, 도 9a에서 도시된 바와 같이 제2 길이(l2)가 제1 길이(l1)보다 큰 것이 하나의 실시예인데, 본 발명분야의 당업자라면 이러한 설명은 단지 예시에 불과하며 본 실시예를 한정하려는 의도는 없다는 것을 알 것이다. 다른 실시예들에서, 제2 길이(l2)는 제1 길이보다 크거나, 이보다 작거나, 또는 제1 길이(l1)와 동등할 수 있다. 제1 길이(l1)와 제2 길이(l2)의 모든 크기들 및 치수들은 본 실시예들의 범위 내에 완전히 포함되는 것으로 한다.
실시예에서, 제일먼저 제3 반도체 다이(901)를 제2 반도체 다이(203)에 정렬시키고 제4 반도체 다이(903)를 제1 반도체 다이(201)에 정렬시킴으로써 제3 반도체 다이(901) 및 제4 반도체 다이(903)는 제2 반도체 다이(203) 및 제1 반도체 다이(201)에 접합될 수 있다. 다이들이 정렬되면, 리플로우가 수행되어 제2 외부 커넥터들(803)의 물질은 리플로우되고 다이들은 함께 접합될 수 있다. 하지만, 제1 반도체 다이(201), 제2 반도체 다이(203), 제3 반도체 다이(901) 및 제4 반도체 다이(903)를 접합시키기 위해, 구리-구리 접합과 같은, 임의의 적절한 접합 방법이 대안적으로 활용될 수 있다.
택일적으로, 도 9a는 또한 제3 반도체 다이(901)와 제4 반도체 다이(903)의 캡슐화를 나타낸다. 실시예에서, 제3 반도체 다이(901)와 제4 반도체 다이(903)를 캡슐화하기 위해 제2 몰딩 공정이 이용될 수 있으며, 제2 몰딩 공정은 제1 반도체 다이(201)와 제2 반도체 다이(203)를 캡슐화하기 위한 제1 몰딩 공정과 유사할 수 있다. 예를 들어, 봉지재(301)는 도 3과 관련하여 위에서 설명한 바와 같이, 제1 반도체 다이(201), 제2 반도체 다이(203), 제3 반도체 다이(901), 및 제4 반도체 다이(903)와 함께 몰딩 챔버내에 배치될 수 있다. 하지만, 제2 몰딩 공정은 제1 몰딩 공정과 유사할 수 있지만, 대안적으로 제2 몰딩 공정은 본 실시예들의 범위 내에 남아있으면서 상이한 물질들 및 상이한 공정들을 이용할 수 있다.
제3 반도체 다이(901)와 제4 반도체 다이(903)를 캡슐화함으로써, 제1 RDL(801)은 두 개의 봉지재(301) 세트들 사이에 위치할 수 있다. 이러한 위치는, 제1 반도체 다이(201), 제2 반도체 다이(203), 제3 반도체 다이(901) 및 제4 반도체 다이(903) 사이에 직접 위치하지 않은 제1 RDL(801)의 일부분들에 대한 지지를 제공하는 것을 도와준다. 보다 나은 보호를 제공함으로써, 장래의 제1 RDL(801)의 악화는 감소될 수 있거나 또는 제거될 수 있다.
또한 택일적으로, 제3 반도체 다이(901)와 제4 반도체 다이(903)를 캡슐화하기 위해 활용된 봉지재(301)는 제3 반도체 다이(901) 및 제4 반도체 다이(903)를 노출시키도록 제3 반도체 다이(901) 및 제4 반도체 다이(903)와 함께 평탄화될 수 있다. 실시예에서 제3 반도체 다이(901)와 제4 반도체 다이(903)가 노출될 때 까지, 봉지재(301)는, 예컨대 봉지재(301)와 반응해서 봉지재(301)를 그라인딩하여 제거하기 위한 CMP 공정을 이용하여 평탄화되고 제거될 수 있다.
추가적으로, 도 9a에서는 단일의 제3 반도체 다이(901)와 단일의 제4 반도체 다이(903)가 도시되고 있지만, 이것은 예시예 불과할 뿐이며, 본 실시예들을 한정시키려는 의도가 있는 것은 아니다. 대안적인 실시예들에서 도 9a에서 도시된 단일의 제3 반도체 다이(901)는 제2 반도체 다이(203)에 전기적으로 연결될 것이 요망되는 다수의 반도체 다이들을 나타낼 수 있다. 마찬가지로, 9a에서 도시된 단일의 제4 반도체 다이(903)는 제1 반도체 다이(201)에 전기적으로 연결될 것이 요망되는 다수의 반도체 다이들을 나타낼 수 있다. 제3 반도체 다이(901)와 제4 반도체 다이(903)의 임의의 갯수 조합이 대안적으로 활용될 수 있으며, 이러한 모든 조합들은 본 실시예들의 범위내에 완전히 포함되는 것으로 한다.
도 9b는 제3 반도체 다이(901)와 제4 반도체 다이(903)의 대안적인 배치를 나타낸다. 이 실시예에서, 제3 반도체 다이(901)와 제4 반도체 다이(903)는, 제1 반도체 다이(201)와 제2 반도체 다이(203)를 단순히 오버행하는 것 대신에, 이들이 각자의 다이들로부터 오프셋되도록 배치된다. 실시예에서, 제3 반도체 다이(901)와 제4 반도체 다이(903)는 약 1.5㎜와 같은, 약 100㎛와 약 3㎜ 사이의 제1 거리(l1) 만큼 오프셋될 수 있다.
택일적으로, 언더필 물질(905)이 제1 반도체 다이(201), 제2 반도체 다이(203), 제3 반도체 다이(901) 및 제4 반도체 다이(903) 사이의 공간에 주입되거나 또는 이와 다른 방법으로 이 공간에서 형성될 수 있다. 언더필 물질(905)은, 예컨대, 제1 반도체 다이(201), 제2 반도체 다이(203), 제3 반도체 다이(901) 및 제4 반도체 다이(903) 사이에 분배되고 그 후 경화되어 굳게되는 액체 에폭시를 포함할 수 있다. 이 언더필 물질(905)은 제3 외부 커넥터들(805)에서 크랙들이 형성되는 것을 방지하기 위해 이용될 수 있으며, 이러한 크랙들은 일반적으로 열 응력에 의해 유발된다.
대안적으로, 제2 외부 커넥터들(803) 내에서 크랙들이 발생하는 것을 방지하는 것을 도와주기 위해 제1 반도체 다이(201), 제2 반도체 다이(203), 제3 반도체 다이(901) 및 제4 반도체 다이(903) 사이에 변형가능한 겔이나 또는 실리콘 고무가 형성될 수 있다. 이러한 겔이나 또는 실리콘 고무는, 제1 반도체 다이(201), 제2 반도체 다이(203), 제3 반도체 다이(901) 및 제4 반도체 다이(903) 사이에 변형가능한 겔이나 또는 고무를 주입하거나 또는 이와 다른 방법으로 이 사이에 배치시킴으로써 형성될 수 있다. 변형가능한 겔이나 또는 실리콘 고무는 또한 후속 공정 동안에 응력 제거를 제공할 수 있다.
도 10a는 제2 캐리어 웨이퍼(601)와 제2 접착제(603)의 제거, 및 제3 외부 커넥터들(1001)과 제1 외부 커넥터들(217)의 형성을 나타낸다. 제2 접착제(603)가 열적 릴리즈 막인 실시예에서, 제2 접착제(603)와 제2 캐리어 웨이퍼(601)는 제2 캐리어 웨이퍼(601)가 손쉽게 제거가능하도록 제2 접착제(603)의 온도를 약 200℃보다 높게까지 증가시킴으로써 제거될 수 있다. 대안적으로, 제2 접착제(603)가 UV 아교인 실시예에서, 제2 캐리어 웨이퍼(601)와 제2 접착제(603)를 제거하기 위해 제2 접착제(603)는 UV 광으로 조사될 수 있다.
제2 캐리어 웨이퍼(601)와 제2 접착제(603)가 제거되면, 제3 외부 커넥터들(1001)이 제1 외부 커넥터들(217)과 접촉하면서 형성될 수있다. 실시예에서, 제3 외부 커넥터들(1001)은 마이크로범프들 또는 제어된 붕괴형 칩 연결부(C4) 범프들과 같은 접촉 범프들일 수 있고, 주석과 같은 물질, 또는 은 또는 구리와 같은 다른 적절한 물질들을 포함할 수 있다. 제3 외부 커넥터들(1001)이 주석 솔더 범프들인 실시예에서, 제3 외부 커넥터들(1001)은 전기도금, 증착, 프린팅, 솔더 전사, 볼 배치 등과 같은 임의의 적절한 방법을 통해 약 100㎛의 바람직한 두께로 주석층을 초기에 형성함으로써 형성될 수 있다. 주석층이 구조물상에서 형성되면, 물질을 원하는 범프 형상으로 쉐이핑하기 위해 리플로우가 수행되는 것이 바람직하다.
도 10a는 또한 제2 기판(1022)으로의 제1 반도체 다이(201)와 제2 반도체 다이(203)의 연결을 나타낸다. 제2 기판(1022)은, 제1 반도체 다이(201)와 제2 반도체 다이(203)를 지지하고 보호하기 위해 활용될 수 있는 동시에 또한 외부 디바이스들(미도시됨)로의 제1 반도체 다이(201)와 제2 반도체 다이(203)상의 제3 외부 커넥터들(1001)간의 연결을 제공하기 위해 이용될 수 있다. 실시예에서, 제2 기판(1022)은 인쇄 회로 보드일 수 있고, BT(bismaleimide triazine), FR-4 등과 같은 폴리머 물질의 다중 주석층들(또는 라미네이트들)의 스택으로서 형성된 적층 기판일 수 있다. 하지만, 유기 기판, 세라믹 기판 등과 같은 임의의 다른 적절한 기판이 대안적으로 활용될 수 있고, 제1 반도체 다이(201)와 제2 반도체 다이(203)에 대한 지지 및 연결성을 제공하는 이러한 모든 기판들은 본 실시예들의 범위 내에 완전히 포함되는 것으로 한다.
도 10b는 점선(1020)에 의해 에워싸여진 도 10a의 일부분의 보다 상세한 확대된 모습을 나타낸다. 살펴볼 수 있는 바와 같이, 제1 외부 커넥터들(217)은 봉지재(301)를 거쳐서 제1 UBM 층들(1003)로부터 멀리 연장한다. 따라서, 봉지재(301)는 제1 외부 커넥터들(217)에 대한 추가적인 지지 및 보호를 제공하는 동시에 또한 제1 반도체 다이(201)의 나머지에 대한 지지 및 보호를 제공한다.
도 10c와 도 10d는 제1 외부 커넥터들(217)을 보호하기 위해 택일적인 보호층(221)이 이용될 수 있는 실시예들을 나타낸다. 도 10c는 예컨대 CMP 공정과 같은 평탄화 공정을 이용하여, 보호층(221)이 제1 외부 커넥터들(217)의 윗면과 평면을 이루도록 형성될 수 있는 하나의 실시예를 나타낸다. 도 10d는 보호층(221)이 제1 외부 커넥터들(217)의 일부분을 보호하지만 제1 외부 커넥터들(217)의 윗면까지 완전히 연장하지 않는 대안적인 실시예를 나타낸다.
여기서 설명한 실시예를 활용함으로써, 칩 온 웨이퍼 공정 또는 칩 온 웨이퍼 온 기판 공정은 최상단 다이(예컨대, 제3 반도체 다이(901) 또는 제4 반도체 다이(903))가 바닥부 다이(예컨대, 제1 반도체 다이(201) 또는 제2 반도체 다이(203))를 오버행하거나 또는 이것보다 큰 치수를 갖도록 해준다. 이 실시예들은 또한 제1 반도체 다이(201), 제2 반도체 다이(203), 제3 반도체 다이(901) 및 제4 반도체 다이(903)를 연결시키기 위해 볼 그리드 어레이들을 이용함으로써 폼 팩터 감소를 가능하게 해주며, 제1 반도체 다이(201)와 제2 반도체 다이(203)가 (인쇄 회로 보드와 같은) 또다른 기판에 부착되기 전에 제3 반도체 다이(901)와 제4 반도체 다이(903)에 연결될 수 있기 때문에, 보다 큰 처리 유연성을 가능하게 해준다. 이러한 유연성은 인쇄 회로 보드로의 부착이 제거되거나 또는 재배열됨으로써 잠재적으로 어셈블리 비용을 낮출 수 있다는 것을 의미한다.
도 11은 제2 RDL(1101)이 제1 반도체 다이(201)와 제2 반도체 다이(203)의 제1 측면(202) 위에서 형성되는 또다른 실시예를 나타낸다. 실시예에서, 제2 RDL(1101)은 봉지재(301)가 제거되어 제1 외부 커넥터들(217)을 노출시킨 후 제1 캐리어(101)가 제거되기 전에 형성될 수 있다. 제2 RDL(1101)은 도 8과 관련하여 상술한 제1 RDL(801)과 유사한 물질들을 이용하여 이와 유사한 형식으로 형성될 수 있다. 예를 들어, 제2 RDL(1101)은 알루미늄, 구리, 텅스텐, 티타늄, 및 이들의 조합과 같은 금속들로 형성된 두 개의 도전층들을 포함할 수 있고, 화학적 기상 증착 및 패턴화 공정을 이용하여 형성될 수 있다. 하지만, 이와 달리 제2 RDL(1101)은 제1 RDL(801)과는 상이한 물질들과 이와 상이한 공정들을 이용하여 형성될 수 있다.
도 12는 제1 캐리어(101)가 제거되고, 제2 캐리어 웨이퍼(601)가 예컨대 제2 접착제(603)를 이용하여 제2 RDL(110)에 부착되고, 제1 반도체 다이(201)와 제2 반도체 다이(203)가 시닝되어 TSV들(701)을 형성하고, 제1 RDL(801)과 제2 외부 커넥터들(803)이 제1 반도체 다이(201)와 제2 반도체 다이(203)의 제2 측면(204) 위에서 형성되며, 제3 반도체 다이(901)와 제4 반도체 다이(903)가 제2 반도체 다이(203)와 제1 반도체 다이(201)에 접합된 후의 결과적인 구조물을 나타낸다.
도 13a와 도 13b는 제2 RDL(1101)로부터의 제2 캐리어 웨이퍼(601)와 제2 접착제(603)의 제거, 및 제2 RDL(1101)과 연결된 제5 외부 커넥터들(1307)의 형성을 나타내며, 도 13b는 점선 박스(1320)에 의해 경계가 표시된 도 13a의 영역의 보다 상세한 확대된 모습을 나타낸다. 제2 접착제(603)가 열적 릴리즈 막인 실시예에서, 제2 캐리어 웨이퍼(601)는, 제2 캐리어 웨이퍼(601)가 제거될 수 있을 때 까지 제2 접착제(603)의 온도를 증가시킴으로써 제거될 수 있다.
제2 캐리어 웨이퍼(601)가 제거되면, 제2 RDL(1101)에 대한 보호를 제공하기 위해 제3 패시베이션층(1301)이 제2 RDL(1101) 위에서 형성될 수 있다. 제3 패시베이션층(1301)은 실리콘 산화물, 실리콘 질화물, 탄소도핑된 산화물과 같은 저 k(low-k) 유전체, 탄소도핑된 다공성 실리콘 이산화물과 같은 극저 k(extremely low k) 유전체, 이들의 조합 등과 같은 하나 이상의 적절한 유전체 물질들로 이루어질 수 있다. 제3 패시베이션층(1301)은 화학적 기상 증착(CVD)과 같은 공정을 통해 형성될 수 있지만, 임의의 적절한 공정이 활용될 수 있으며, 약 9.25KÅ와 같이, 약 0.5㎛와 약 5㎛ 사이의 두께를 가질 수 있다.
추가적인 보호를 제공하기 위해 제4 패시베이션층(1303)이 제3 패시베이션층(1301) 위에서 형성될 수 있다. 실시예에서, 제4 패시베이션층(1303)은 폴리이미드와 같은 폴리머로부터 형성될 수 있거나, 또는 대안적으로 제3 패시베이션층(1301)과 유사한 물질(예컨대, 실리콘 산화물, 실리콘 질화물, 저 k 유전체, 극저 k 유전체, 이들의 조합 등)로 형성될 수 있다. 제4 패시베이션층(1303)은 약 5㎛와 같이, 약 2㎛와 약 15㎛ 사이의 두께를 갖도록 형성될 수 있다.
제4 패시베이션층(1303)이 형성된 후, 제2 RDL(1101)의 일부분들을 노출시키기 위해 제3 패시베이션층(1301)과 제4 패시베이션층(1303)이 예컨대 포토리소그래피 마스킹 및 에칭 공정을 이용하여 패턴화될 수 있다. 제2 RDL(1101)이 노출되면, 제2 UBM 층들(1305)이 제2 RDL(1101)과 전기적 접촉을 이루면서 형성될 수 있다. 제2 UBM 층들(1305)은 티타늄층, 또는 니켈층과 같은, 도전성 물질층을 포함할 수 있다. 제2 UBM 층들(1305)은 다중 서브층들(미도시됨)을 포함할 수 있다. 본 발명분야의 당업자는, 크롬/크롬 구리 합금/구리/금의 배열, 티타늄/티타늄 텅스텐/구리의 배열, 또는 구리/니켈/금의 배열과 같은, 제2 UBM 층들(1305)의 형성에 적절한 수 많은 적절한 물질 및 층들의 배열들이 존재한다는 것을 알 것이다. 제2 UBM 층들(1305)을 위해 이용될 수 있는 임의의 적절한 물질들 또는 물질층들은 본 실시예들의 범위 내에 완전히 포함되는 것으로 한다. 제2 UBM 층들(1305)은 희망하는 물질들에 따라, 스퍼터링, 증착, 또는 PECVD 공정들과 같은 공정들을 이용하여 생성될 수 있다. 제2 UBM 층들(1305)은 약 5㎛와 같이, 약 0.7㎛와 약 10㎛ 사이의 두께를 갖도록 형성될 수 있다.
제2 UBM 층들(1305)이 형성되면, 제5 외부 커넥터들(1307)이 제2 RDL(1101)과 전기적 연결을 이루면서 형성될 수 있다. 제5 외부 커넥터들(1307)은 마이크로범프들 또는 제어된 붕괴형 칩 연결부(C4) 범프들과 같은 접촉 범프들일 수 있고, 주석과 같은 물질, 또는 은 또는 구리와 같은 다른 적절한 물질들을 포함할 수 있다. 제5 외부 커넥터들(1307)이 주석 솔더 범프들인 실시예에서, 제5 외부 커넥터들(1307)은 전기도금, 증착, 프린팅, 솔더 전사, 볼 배치 등과 같은 임의의 적절한 방법을 통해 약 100㎛의 바람직한 두께로 주석층을 초기에 형성함으로써 형성될 수 있다. 주석층이 구조물상에서 형성되면, 원하는 범프 형상으로 물질을 쉐이핑하기 위해 리플로우가 수행되는 것이 바람직하다.
도 13c와 도 13d는 제1 외부 커넥터들(217)을 보호하기 위해 택일적인 보호층(221)이 이용될 수 있는 실시예들을 나타낸다. 도 13c는 예컨대 CMP 공정과 같은 평탄화 공정을 이용하여, 보호층(221)이 제1 외부 커넥터들(217)의 윗면과 평면을 이루도록 형성될 수 있는 하나의 실시예를 나타낸다. 도 13d는 보호층(221)이 제1 외부 커넥터들(217)의 일부분을 보호하지만 제1 외부 커넥터들(217)의 윗면까지 완전히 연장하지 않는 대안적인 실시예를 나타낸다.
택일적으로, 도 13a와 도 13b에서는 도시되어 있지 않지만, 본 실시예에서는 제3 반도체 다이(901)와 제4 반도체 다이(903)도 캡슐화될 수 있다. 실시예에서, 제3 반도체 다이(901)와 제4 반도체 다이(903)는 (도 3과 관련하여 상술한 바와 같이) 제1 반도체 다이(201)와 제2 반도체 다이(203)가 캡슐화된 것과 유사한 방식으로 캡슐화될 수 있다. 하지만, 제3 반도체 다이(901)와 제4 반도체 다이(903)를 캡슐화하기 위해 대안적인 봉지재 또는 상이한 방법이 활용될 수 있다.
도 11 내지 도 13b와 관련하여 상술한 실시예들을 활용함으로써, 재분배층들(예컨대, 제1 RDL(801) 및 제2 RDL(1101))이 제1 반도체 다이(201)와 제2 반도체 다이(203)의 양측면들상에서 형성될 수 있다. 이것은 연결부들의 제어 및 배치에서의 희망하는 바에 따른 보다 큰 팬 아웃 및 보다 큰 유연성을 가능하게 해줌에 따라, 배치 및 공간에서 보다 큰 효율성을 가능하게 해준다.
택일적으로, 도 1 내지 도 13d와 관련하여 상술한 실시예들 각각 이후, 본 실시예들은, 예컨대 제1 반도체 다이(201)와 제4 반도체 다이(903)를 포함한 제1 패키지가 예컨대 제2 반도체 다이(203)와 제3 반도체 다이(901)를 포함한 제2 패키지로부터 분리될 수 있는 단품화 공정(개별적으로 도시되지는 않음)을 더 포함할 수 있다. 단품화 공정은 예컨대 다이아몬드 코팅된 소잉 블레이드(saw blade)로 제1 패키지와 제2 패키지 사이의 스크라이브 영역을 슬라이싱함으로써 수행될 수 있지만, 제2 패키지로부터 제1 패키지를 분리하기 위한 일련의 하나 이상의 에칭들과 같은, 임의의 적절한 대안적인 분리 방법이 대안적으로 활용될 수 있다.
본 발명개시 및 그 장점들을 자세하게 설명하였지만, 여기에 다양한 변경, 대체, 및 변동이 첨부된 청구범위들에 의해 정의된 본 실시예들의 범위 및 사상을 벗어나지 않고서 행해질 수 있다는 것을 이해해야 한다. 또한, 본 출원의 범위는 본 명세서에서 설명된 물질, 수단, 방법, 및 단계의 공정, 머신, 제조, 조성의 특정한 실시예들로 한정되는 것을 의도하지 않는다. 본 발명분야의 당업자라면 여기서 설명된 대응하는 실시예들과 실질적으로 동일한 기능을 수행하거나 또는 이와 실질적으로 동일한 결과를 달성하는, 현존하거나 후에 개발될 물질, 수단, 방법, 또는 단계의 공정, 머신, 제조, 조성이 본 발명개시에 따라 이용될 수 있다는 것을 본 발명개시로부터 손쉽게 알 것이다. 따라서, 첨부된 청구항들은 이와 같은 물질, 수단, 방법, 또는 단계의 공정, 머신, 제조, 조성을 청구항의 범위내에 포함하는 것으로 한다.

Claims (10)

  1. 디바이스를 형성하기 위한 방법에 있어서,
    제1 캐리어 웨이퍼 상에 하나 이상의 바닥부 다이를 배치하는 단계;
    상기 하나 이상의 바닥부 다이의 전면(frontside)상의 제1 전기적 접촉부들이 노출되도록, 상기 하나 이상의 바닥부 다이의 사이와, 상기 하나 이상의 바닥부 다이의 전면 위와, 상기 제1 전기적 접촉부들 사이에 제1 몰딩 화합물을 형성하는 단계;
    상기 하나 이상의 바닥부 다이와 상기 제1 몰딩 화합물을 제2 캐리어 웨이퍼에 부착하는 단계;
    상기 하나 이상의 바닥부 다이를 시닝(thinning)하여 상기 하나 이상의 바닥부 다이를 관통하여 형성된 쓰루 비아들을 노출시키는 단계;
    상기 쓰루 비아들에 대한 제2 전기적 접촉부들을 상기 하나 이상의 바닥부 다이의 후면(backside)을 따라 형성하는 단계; 및
    상기 하나 이상의 바닥부 다이에 하나 이상의 최상단 다이를 부착하는 단계
    를 포함하는, 디바이스 형성 방법.
  2. 제1항에 있어서, 상기 하나 이상의 바닥부 다이 위에 재분배층을 형성하는 단계를 더 포함하는, 디바이스 형성 방법.
  3. 제1항에 있어서, 상기 하나 이상의 최상단 다이 위에 제2 몰딩 화합물을 형성하는 단계를 더 포함하는, 디바이스 형성 방법.
  4. 반도체 디바이스를 제조하는 방법에 있어서,
    제1 외부 접촉부들을 포함한 제1 반도체 다이 - 상기 제1 외부 접촉부들은 상기 제1 반도체 다이의 전면상에 형성됨 - 를 캐리어에 부착하는 단계;
    제2 외부 접촉부들을 포함한 제2 반도체 다이 - 상기 제2 외부 접촉부들은 상기 제2 반도체 다이의 전면상에 형성됨 - 를 상기 캐리어에 부착하는 단계;
    상기 제1 반도체 다이와 상기 제2 반도체 다이를 봉지재(encapsulant)로 캡슐화(encapsulating)하는 단계;
    상기 봉지재의 일부분을 제거하여 상기 봉지재의 나머지 부분이 상기 제1 및 제2 반도체 다이의 사이와, 상기 제1 및 제2 반도체 다이의 전면 위와, 상기 제1 및 제2 외부 접촉부들 사이에 형성되도록 함으로써, 상기 제1 외부 접촉부들과 상기 제2 외부 접촉부들을 노출시키는 단계;
    상기 제1 반도체 다이 내의 제1 쓰루 기판 비아들 및 상기 제2 반도체 다이 내의 제2 쓰루 기판 비아들을 형성하기 위해 상기 제1 반도체 다이와 상기 제2 반도체 다이를 시닝하는 단계; 및
    상기 제1 쓰루 기판 비아들에 제3 반도체 다이를 전기적으로 연결하고 상기 제2 쓰루 기판 비아들에 제4 반도체 다이를 전기적으로 연결하는 단계
    를 포함하는, 반도체 디바이스 제조 방법.
  5. 제4항에 있어서, 상기 제3 반도체 다이와 상기 제4 반도체 다이를 캡슐화하는 단계를 더 포함하는, 반도체 디바이스 제조 방법.
  6. 제4항에 있어서, 상기 제1 반도체 다이와 상기 제2 반도체 다이를 캡슐화한 이후에 상기 제1 외부 접촉부들상에 제3 외부 접촉부를 형성하는 단계를 더 포함하는, 반도체 디바이스 제조 방법.
  7. 반도체 디바이스에 있어서,
    제1 봉지재에 의해 캡슐화된 제1 반도체 다이;
    상기 제1 반도체 다이의 적어도 일부분을 관통하여 연장하고 상기 제1 반도체 다이의 제1 측면상에서 노출된 적어도 하나의 쓰루 기판 비아;
    상기 제1 반도체 다이의 제2 측면상에 위치한 제1 외부 커넥터들 - 상기 제1 외부 커넥터들이 노출되도록 상기 제1 반도체 다이의 제2 측면 위와, 상기 제1 외부 커넥터들의 사이에 상기 제1 봉지재가 형성됨 - ; 및
    상기 적어도 하나의 쓰루 기판 비아와 전기적으로 연결된 제3 반도체 다이
    를 포함하며, 상기 제3 반도체 다이는 상기 제1 봉지재 위에서 연장하는 것인, 반도체 디바이스.
  8. 제7항에 있어서,
    상기 제1 봉지재에 의해 캡슐화된 제2 반도체 다이;
    상기 제2 반도체 다이와 전기적으로 연결된 제4 반도체 다이
    를 더 포함하며, 상기 제4 반도체 다이는 상기 제1 봉지재 위에서 연장하는 것인, 반도체 디바이스.
  9. 제7항에 있어서, 상기 제1 외부 커넥터들과 전기적으로 연결된 제1 재분배층을 더 포함하며, 상기 제1 재분배층은 상기 제1 봉지재 위에서 연장하는 것인, 반도체 디바이스.
  10. 제9항에 있어서, 상기 적어도 하나의 쓰루 기판 비아와 전기적으로 연결된 제2 재분배층을 더 포함하며, 상기 제2 재분배층은 상기 제1 봉지재 위에서 연장하는 것인, 반도체 디바이스.
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US20140001645A1 (en) 2014-01-02
TWI528471B (zh) 2016-04-01
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US20170005073A1 (en) 2017-01-05
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