TWI528471B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI528471B
TWI528471B TW102120259A TW102120259A TWI528471B TW I528471 B TWI528471 B TW I528471B TW 102120259 A TW102120259 A TW 102120259A TW 102120259 A TW102120259 A TW 102120259A TW I528471 B TWI528471 B TW I528471B
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Taiwan
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semiconductor die
semiconductor
layer
die
substrate via
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TW102120259A
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TW201401391A (zh
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林俊成
余振華
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台灣積體電路製造股份有限公司
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Description

半導體裝置及其製造方法
本發明係有關於一種半導體技術，特別為有關於一種三維半導體裝置及其製造方法。
自積體電路的發明創造以來，由於各個電子部件(即，電晶體、二極體、電阻、電容等等)的集積度(integration density)持續的改進，使半導體業持續不斷的快速成長發展。主要來說，集積度的改進來自於最小特徵尺寸(minimum feature size)不斷縮小而容許更多的部件整合至既有的晶片面積內。
這些集積度的改進實質上是朝二維(two-dimensional,2D)方面的，因為積體部件所佔的體積實際上位於半導體晶圓的表面。儘管微影(lithography)技術的精進為2D積體電路製作帶來相當大的助益，二維空間所能擁有的密度還是有其物理限制。這些限制之一在於製作這些部件所需的最小尺寸。再者，當更多的裝置放入一晶片中，需具有更複雜的電路設計。
為了進一步增加積體電路密度，已開始研究三維(3D)積體電路(three-dimensional integrated circuit,3DIC)。 在典型的3DIC製程中，二個晶粒彼此接合，且在每一晶粒與基底上的接觸墊之間形成電性連接。例如，在彼此上方接合二個晶粒。疊置的晶粒接著與一承載基底(carrier substrate)接合，而接線將每一晶粒上的接觸墊電性耦接至承載基底上的接觸墊。
本發明係提供一種半導體裝置的製造方法，包括在一第一承載晶圓上放置一或多個的底部晶粒。在一或多個的底部晶粒之間形成一第一模塑成型材料，而暴露出位於一或多個的底部晶粒上的複數電性接觸窗。將一或多個的底部晶粒及第一模塑成型材料貼附至一第二承載晶圓。將一或多個的底部晶粒薄化，以暴露出穿透一或多個的底部晶粒的複數通孔電極。沿著一或多個的底部晶粒的一背側，形成連接通孔電極的複數電性連接器。將一或多個的頂部晶粒貼附至一或多個的底部晶粒。
本發明係提供另一種半導體裝置的製造方法，包括將一第一半導體晶粒貼附至一載具，第一半導體晶粒包括複數第一外部接觸窗。將一第二半導體晶粒貼附至載具，第二半導體晶粒包括複數第二外部接觸窗。以一封膠封裝第一半導體晶粒及第二半導體晶粒。去除一部分的封膠，以暴露出第一外部接觸窗及第二外部接觸窗。將第一半導體晶粒及第二半導體晶粒薄化，以暴露出第一半導體晶粒內的複數第一基板通孔電極及第二半導體晶粒內的複數第二基板通孔電極。將一第三半導體晶粒電性連接至第一基板通孔電極，及將一第四半導體晶 粒電性連接至第二基板通孔電極。
本發明係提供一種半導體裝置，包括以一第一封膠封裝的一第一半導體晶粒。至少一個基板通孔電極延伸穿透至少一部分的第一半導體晶粒，且從第一半導體晶粒的一第一側上暴露出。複數第一外部連接器位於第一半導體晶粒的一第二側上。一第三半導體晶粒，與至少一個基板通孔電極電性連接，且延伸至第一封膠上方。
101‧‧‧第一承載晶圓
103‧‧‧第一黏著層
201‧‧‧第一半導體(或底部)晶粒
202‧‧‧第一側
203‧‧‧第二半導體(或底部)晶粒
204‧‧‧第二側
205‧‧‧第一基板
207‧‧‧基板通孔電極開口
209‧‧‧主動裝置
211‧‧‧金屬化層
213‧‧‧接觸墊
215‧‧‧第一鈍化護層
217‧‧‧第一外部連接器/導電柱
219‧‧‧第一導電材料
221‧‧‧保護層
301‧‧‧封膠
601‧‧‧第二承載晶圓
603‧‧‧第二黏著層
701‧‧‧基板通孔電極
801‧‧‧第一重佈線層
803‧‧‧第二外部連接器
901‧‧‧第三半導體(或頂部)晶粒
903‧‧‧第四半導體(或頂部)晶粒
905‧‧‧底膠材料
1001‧‧‧第三外部連接器
1002‧‧‧第二鈍化護層
1003‧‧‧第一凸塊下金屬層
1020、1320‧‧‧虛線
1022‧‧‧第二基板
1101‧‧‧第二重佈線層
1301‧‧‧第三鈍化護層
1303‧‧‧第四鈍化護層
1305‧‧‧第二凸塊下金屬層
1307‧‧‧第四外部連接器
d1‧‧‧距離
l1‧‧‧第一長度
l2‧‧‧第二長度
第1-8、9A-9B、10A-10D圖係繪示出本發明一實施例之連接半導體裝置的製造過程的剖面示意圖。
第11-12、13A-13D圖係繪示出本發明另一實施例之連接半導體裝置的製造過程的剖面示意圖。
以下說明本發明實施例之製作與使用。然而，可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。
在詳細說明實施例之前，將大致說明本發明實施例的概念及其優點與特徵。如以下說明，本發明揭露的實施例提供一種方法及結構，以改善頂部晶粒側向突出(overhang)的問題。舉例來說，一晶片-(晶片-基板)(chip on(chip on substrate)，Co(CoS))可能良率低且成本相對較高。一(晶片-晶圓)-基板((chip on wafer)on substrate，(CoW)oS)不會產生頂部 晶粒側向突出的問題。一(晶片-晶片)-基板((chip on chip)on substrate，(CoC)oS)比晶片-(晶片-基板)的成本高，而比(晶片-晶圓)-基板的良率低。
簡言之，本發明實施例提供一種晶片-晶圓的製造方法，以容許頂部晶粒側向突出或頂部晶粒大於底部晶粒(即，具有通孔電極的晶粒(with through via die，w/TV die))。本發明實施例也提供一種晶片-晶圓-基板的製程的改良方法，可避免增加基板下方的組裝成本。透過球柵陣列(ball grid array，BGA)技術，本發明實施例更揭示了一種低形狀因子(form factor)的結構。
請參照第1至10B圖，其提供第一實施例。第1圖係繪示出一第一承載晶圓101，具有塗佈於其上的一第一黏著層103。例如，第一承載晶圓101可包括玻璃、氧化矽、氧化鋁及類似的材料，且其厚度可大約大於12 mils。另外，第一承載晶圓101可包括適合的承載膠帶。承載膠帶可為習知的藍色膠帶。
第一黏著層103可用來黏著第一承載晶圓101與其他裝置(例如，一第一半導體晶粒201及一第二半導體晶粒203(繪示於第2圖，並於後續作說明))。在一實施例中，第一黏著層103可為一熱釋放層。另外，第一黏著層103可為一紫外光膠(ultraviolet glue)，其暴露於紫外光時會失去黏性。也可使用任何適合的黏著劑，且所有上述黏著劑皆涵蓋於本發明實施例的範圍內。
第2圖係繪示出透過第一黏著層103而貼附至第 一承載晶圓101的第一半導體(或底部)晶粒201及第二半導體(或底部)晶粒203。第一半導體晶粒201及第二半導體晶粒203皆可包括第一基板205、基板通孔電極(through substrate via，TSV)開口207、主動裝置209、金屬化層211、接觸墊213、第一鈍化護層215及第一外部連接器217。然而，第一半導體晶粒201及第二半導體晶粒203具有類似的特徵部件，其僅作為說明而並非用以侷限本發明實施例的範圍。第一半導體晶粒201及第二半導體晶粒203可具有類似或不同的結構，以符合其所需的功能。
此外，第2圖只繪示出一個第一半導體晶粒201及一個第二半導體晶粒203，其僅作為說明而並非用以侷限本發明實施例的範圍。更確切地說，一個第一半導體晶粒201可代表具有基板通孔電極(將於後續配合第7圖說明)的一個或一個以上的第一半導體晶粒201形成於其中且堆疊在一起。同樣地，一個第二半導體晶粒203可代表具有基板通孔電極的一個或一個以上的第二半導體晶粒203形成於其中且堆疊在一起。可使用任何適合的數量的第一半導體晶粒201及第二半導體晶粒203，且所有上述組合皆涵蓋於本發明實施例的範圍內。
第一基板205可包括塊狀矽、摻雜、未摻雜或絕緣層上覆矽(silicon-on insulator，SOI)基板的一主動層，且具有一第一側202及一第二側204。一般而言，絕緣層上覆矽基板包括一層半導體材料(例如，矽、鍺、矽鍺、絕緣層上覆矽、絕緣層上覆矽鍺(silicon germanium on insulator，SGOI)或其組合)。也可使用其他基板，包括多層結構的基板、漸變(gradient) 基板或混合方向基板。
可在第一基板205的第一側202內形成基板通孔電極開口207。可透過塗佈一適合的光阻(未繪示)並顯影，及去除暴露出的第一基板205至所需深度，形成基板通孔電極開口207。基板通孔電極開口207延伸至第一基板205內且至少超過形成於第一基板205內及/或第一基板205上的主動裝置209，其延伸的深度可大於第一基板205最後所需的高度。因此，延伸的深度取決於第一半導體晶粒201及第二半導體晶粒203的整體設計，從第一基板205上的主動裝置209算起的深度可大約為20微米至200微米的範圍(例如，從第一基板205上的主動裝置209算起的深度大約為100微米)。
當基板通孔電極開口207形成於第一基板205內，基板通孔電極開口207與一襯層(未繪示)對齊。例如，襯層可為由矽酸乙酯(tetraethylorthosilicate，TEOS)或氮化矽所形成的氧化物，然而，也可使用任何適合的介電材料。可透過一電漿增強化學氣相沉積(plasma enhanced chemical vapor deposition oxide，PECVD)製程形成襯層，然而，也可使用其他適合的製程(例如，物理氣相沉積製程或熱處理製程)。此外，襯層的厚度可大約為0.1微米至5微米的範圍(例如，大約為1微米)。
沿著基板通孔電極開口207的側壁及底部形成襯層後，可形成一阻隔層(未繪示)及將第一導電材料219填入剩餘的基板通孔電極開口207。第一導電材料219可包括銅，然而，也可使用其他適合的材料(例如，鋁、合金、摻雜多晶矽、 其組合或類似的材料)。可透過在一晶種(seed)層(未繪示)上電鍍銅，並填入及填滿基板通孔電極開口207，而形成第一導電材料219。當填滿基板通孔電極開口207後，可透過一平坦化製程(例如，化學機械研磨(chemical mechanical polishing，CMP)製程)，去除基板通孔電極開口207外多餘的襯層、阻隔層、晶種層及第一導電材料219，然而，也可使用任何適合的去除製程。
第2圖繪示出的主動裝置209為位於每一第一基板205上的單一電晶體。然而，本發明所屬技術領域中具有通常知識者可以理解的是，只要符合第一半導體晶粒201及第二半導體晶粒203的設計所需的結構及功能需求，可使用的主動裝置及被動裝置(例如，電容、電阻、電感及類似的元件)的類型很廣。可使用任何適合的方法，在第一基板205的第一側202內或上形成主動裝置209。
金屬化層211形成於第一基板205的第一側202及主動裝置209上，且連接各種主動裝置209，以形成功能電路系統。雖然第2圖繪示出一層介電層及內連線結構，金屬化層211可由另外的介電材料層及導電材料層所構成，且可透過任何適合的製程(例如，沉積製程、鑲嵌製程、雙鑲嵌製程等等)所形成。在一實施例中，透過至少一層的內層介電層(interlayer dielectric，ILD)，將四層金屬化層與第一基板205隔開。然而，金屬化層211的實際數量取決於第一半導體晶粒201及第二半導體晶粒203的設計。
接觸墊213形成於金屬化層211上，且與其電性 接觸。接觸墊213可包括鋁，但也可使用其他材料(例如，銅)。可透過一沉積製程(例如，濺鍍製程)形成一層材料層(未繪示)，接著可透過一適合的製程(例如，光微影罩幕製程及蝕刻製程)去除部分的材料層，以形成接觸墊213。然而，也可使用其他適合的製程來形成接觸墊213。接觸墊213的厚度可大約為0.5微米至4微米的範圍(例如，大約為1.45微米)。
第一鈍化護層215可形成於第一基板205上的金屬化層211及接觸墊213上。第一鈍化護層215可由一種或一種以上的適合的介電材料(例如，氧化矽、氮化矽、低介電常數(k)材料(例如，碳摻雜氧化物)、極低介電常數材料(例如，多孔碳摻雜二氧化矽)、其組合或類似的材料)所構成。可透過一製程(例如，化學氣相沉積製程)形成第一鈍化護層215，然而，也可使用任何適合的製程。第一鈍化護層215的厚度可大約為0.5微米至5微米的範圍(例如，0.925微米)。
第二鈍化護層1002(未繪示於第2圖，但繪示於第10B圖)可形成於第一鈍化護層215上，以提供更進一步的保護。在一實施例中，第二鈍化護層1002可由一高分子(例如，聚亞醯胺)所形成，或可由類似於第一鈍化護層215的材料(例如，氧化矽、氮化矽、低介電常數材料、極低介電常數材料、其組合或類似的材料)所形成。第二鈍化護層1002的厚度可大約為2微米至15微米的範圍(例如，大約為5微米)。
可形成第一外部連接器217，以提供連結接觸墊213及外部裝置(未繪示，例如，印刷電路板或其他覆晶式的半導體晶粒)的導電區域。在平坦化製程(例如，化學機械研磨製 程)中，第一外部連接器217也可作為緩衝物。在一實施例中，第一外部連接器217可為導電柱，且可透過以下步驟形成：在第一鈍化護層215及第二鈍化護層1002上先形成厚度大約為5微米至20微米的一光阻(未繪示)。將光阻圖案化，以在導電柱延伸處暴露出部分的第一鈍化護層215及第二鈍化護層1002。接著，在圖案化光阻後，將光阻作為罩幕層，去除部分的第一鈍化護層215及第二鈍化護層1002，進而暴露出下方的部分接觸墊213，以接觸後續形成的導電柱。
當暴露出接觸墊213後，可形成與接觸墊213電性接觸的第一凸塊下金屬(under bump metal，UBM)層1003(未繪示於第2圖，但繪示於第10B圖)。第一凸塊下金屬層1003可包括一層導電材料(例如，鈦層或鎳層)。第一凸塊下金屬層1003可包括多層子層(未繪示)。本發明所屬技術領域中具有通常知識者可以理解的是，許多適合的材料及材料層的配置(例如，鉻/鉻銅合金/銅/金的配置、鈦/鈦鎢/銅的配置或銅/鎳/金的配置)可適用於形成第一凸塊下金屬層1003。任何用於形成第一凸塊下金屬層1003的適合的材料或材料層皆可涵蓋於本發明實施例的範圍內。形成第一凸塊下金屬層1003的製程(例如，濺鍍製程、蒸鍍製程或電漿增強氣相沉積製程)，取決於所需的材料。第一凸塊下金屬層1003的厚度可大約為0.03微米至10微米的範圍(例如，大約為5微米)。
在形成第一凸塊下金屬層1003之後，導電柱217可形成於第一鈍化護層215、第二鈍化護層1002及光阻的開口內。導電柱217由一導電材料(例如，銅)所構成，然而，也可 使用其他導電材料(例如，鎳、金、金屬合金、其組合或類似的材料)。此外，可透過一製程(例如，電鍍製程)形成導電柱217，其使電流通過接觸墊213的導電部分至預計形成導電柱的位置，而接觸墊213浸於一溶液中。溶液及電流在開口內沉積(例如，銅)，以填入及/或填滿光阻、第一鈍化護層215及第二鈍化護層1002的開口，進而形成導電柱217。接著，去除開口外多餘的導電材料，例如，透過化學機械研磨製程。
在形成導電柱217之後，可透過一製程(例如，灰化製程)去除光阻，其增加光阻的溫度直到光阻分解且可被去除。在去除光阻之後，導電柱217從第一鈍化護層215及第二鈍化護層1002延伸出的距離大約為5微米至50微米的範圍(例如，40微米)。一阻隔層(未繪示)可選擇性地形成於導電柱217上(例如，透過無電鍍製程)，其中阻隔層可由鎳、釩、鉻及其組合所構成。
然而，本發明所屬技術領域中具有通常知識者可以理解的是，上述形成導電柱217的製程僅作為說明，而並非用以侷限本發明實施例的實際製程。更確切地說，上述製程僅為說明，可使用任何適合的製程來形成第一外部連接器217。舉例來說，先形成厚度大於其最後厚度的第一鈍化護層215及第二鈍化護層1002，在第一鈍化護層215及第二鈍化護層1002的開口內形成導電柱217，接著去除第一鈍化護層215及第二鈍化護層1002的上部，使得導電柱217從第一鈍化護層215及第二鈍化護層1002延伸而出。任何適合的製程皆涵蓋於本發明實施例的範圍內。
一保護層221可選擇性地形成於第一外部連接器217上，以保護第一外部連接器217。在一實施例中，保護層221可為高分子層，然而，也可使用任何適合的材料。保護層221的厚度可大約為5微米至15微米的範圍(例如，8微米)。
第3圖係繪示出一第一模塑成型(molding)製程，以封裝第一半導體晶粒201及第二半導體晶粒203，使第一半導體晶粒201及第二半導體晶粒203維持固定於第一承載晶圓101。在一實施例中，可使用一模塑成型裝置(未繪示)封裝第一半導體晶粒201及第二半導體晶粒203。舉例來說，可將第一半導體晶粒201、第二半導體晶粒203及第一承載晶圓101放置於模塑成型裝置的一腔室內，且腔室可密封而與外界隔絕。可在腔室密封之前將封膠301放置於腔室內，或可透過一注射口將封膠301注入腔室內。在一實施例中，封膠301可為一模塑成型樹脂材料(例如，高分子、聚苯硫醚(polyphenylene sulfide，PPS)、聚醚醚酮(polyether ether ketone，PEEK)、聚醚碸(polyether sulfone，PES)、其組合或類似的材料)。
當封膠301放置於腔室內後，封膠301封裝第一半導體晶粒201及第二半導體晶粒203，封膠301可固化，以加強封膠301的保護作用。實際的固化製程至少部分取決於作為封膠301的特定材料。在一實施例中，選用模塑成型材料作為封膠301，可透過一製程加以固化，例如，將封膠301加熱至大約100℃至230℃的範圍(例如，大約為150℃)，且持續大約60秒至3000秒的範圍(例如，600秒)。此外，封膠301內可包括引發劑(initiator)及/或催化劑(catalyst)，以利於控制固 化製程。
然而，本發明所屬技術領域中具有通常知識者可以理解的是，上述固化製程僅作為說明而並非用以侷限本發明實施例的範圍。也可使用其他固化製程，例如，透過輻射或甚至在室溫下將封膠301硬化。可使用任何適合的固化製程，且所有上述製程皆涵蓋於本發明實施例的範圍內。
第4圖係繪示出去除封膠301，以暴露出第一外部連接器217。在一實施例中，可透過化學機械研磨製程去除封膠301，其藉由在封膠301上施加研磨料(abrasive)及蝕刻劑並研磨，以與封膠301產生反應，且研磨封膠301直到暴露出第一外部連接器217。另外，可使用一個或一個以上的蝕刻製程，以去除封膠301，且平坦化封膠301與第一外部連接器217。
第5圖係繪示出從第一半導體晶粒201及第二半導體晶粒203去除第一承載晶圓101。第一承載晶圓101的去除方法至少部分取決於使用的第一黏著層103的類型。在一實施例中，第一黏著層103為一熱釋放層，可加熱第一黏著層103的溫度至大約大於200℃，以使第一承載晶圓101脫離第一半導體晶粒201及第二半導體晶粒203。可使用任何適合的方法去除第一承載晶圓101(例如，當第一黏著層103為紫外光膠時，以紫外光照射第一黏著層103)。
第6圖係繪示出使用一第二黏著層603，將一第二承載晶圓601貼附至封膠301及第一外部連接器217。在一實施例中，第二承載晶圓601及第二黏著層603可分別類似於第一承載晶圓101及第一黏著層103，例如，分別為一玻璃承載 晶圓及一熱釋放層。然而，第二承載晶圓601及第二黏著層603也可不同於第一承載晶圓101及第一黏著層103。
第7圖係繪示出去除封膠301及部分的第一基板205的第二側204，以暴露出基板通孔電極開口207及形成基板通孔電極701。在一實施例中，可透過化學機械研磨製程及研磨(grinding)製程，去除封膠301及部分的第一基板205的第二側204，且平坦化封膠301及第一基板205的第二側204。另外，也可使用一個或一個以上的蝕刻製程或其他去除製程，以去除封膠301及暴露出基板通孔電極開口207，進而形成基板通孔電極701。
第8圖係繪示出在第一基板205的第二側204上形成一第一重佈線層(redistribution layer，RDL)801及第二外部連接器803。第一重佈線層801可包括兩層由金屬(例如，鋁、銅、鎢、鈦及其組合)所構成的導電層，且可透過以下步驟形成：透過化學氣相沉積製程沉積金屬層，接著蝕刻不需要的部分，留下第一重佈線層801。第一重佈線層801的厚度可大約為2微米至30微米的範圍(例如，5微米)。然而，也可使用其他材料及製程(例如，習知的鑲嵌製程)來形成第一重佈線層801。
在一實施例中，第一重佈線層801可選擇性地同時形成於第一半導體晶粒201、第二半導體晶粒203及封膠301上。藉由在封膠301上形成第一重佈線層801，第一半導體晶粒201及第二半導體晶粒203的扇出(fan-out)區域可延伸至第一半導體晶粒201及第二半導體晶粒203的邊界之外，而容許 增加輸入/輸出(input/output，I/O)裝置的數量。
第二外部連接器803可為接觸凸塊(例如，微凸塊(micro bump)或控制塌陷高度晶片連接(controlled collapse chip connection，C4)結構)，且可包括一材料(例如，錫)或其他適合的材料(例如，銀或銅)。在一實施例中，第二外部連接器803為焊錫凸塊，且可透過以下步驟形成：先透過任何適合的方法(例如，蒸鍍製程、電鍍製程、印刷製程、焊料轉移(solder transfer)、植球(ball placement)等等)，形成較佳厚度大約為100微米的一層錫。當錫層形成於結構上後，進行一回流製程，以將材料塑形為所需的凸塊形狀。
第9A圖係繪示出將一第三半導體晶粒(或第三頂部晶粒)901及一第四半導體晶粒(或第四頂部晶粒)903分別貼附至第二半導體晶粒203及第一半導體晶粒201。在一實施例中，第三半導體晶粒901及第四半導體晶粒903可包括類似於第一半導體晶粒201及第二半導體晶粒203的主動區、金屬化層及接觸墊(為簡化圖式，以上元件皆未繪示)。然而，上述半導體晶粒與其貼附的半導體晶粒也可包括不同的結構，且可執行不同或互補的功能。
在一實施例中，第三半導體晶粒901可大於下方的第二半導體晶粒203。例如，在一實施例中，第二半導體晶粒203的一第一長度l1為大約3 mm至14 mm的範圍(例如，大約為8 mm)，第三半導體晶粒901的一第二長度l2為大約1 mm至20 mm的範圍(例如，大約為10 mm)。由於第三半導體晶粒901的尺寸大於第二半導體晶粒203，第三半導體晶粒901 可側向突出第二半導體晶粒203。然而，使用封膠301及第一重佈線層801，可提供第二半導體晶粒203及第三半導體晶粒901的支撐及連接。
然而，本發明所屬技術領域中具有通常知識者可以理解的是，如第9A圖所示，第二長度l2大於第一長度l1僅為一實施例，而並非用以侷限本發明實施例的範圍。在其他實施例中，第二長度l2可大於、小於或等於第一長度l1。所有第一長度l1及第二長度l2的尺寸皆涵蓋於本發明實施例的範圍內。
在一實施例中，可透過先將第三半導體晶粒901對準於第二半導體晶粒203，再將第四半導體晶粒903對準於第一半導體晶粒201，以將第三半導體晶粒901及第四半導體晶粒903分別接合至第二半導體晶粒203及第一半導體晶粒201。當對準後，可進行一回流製程，以回流第二外部連接器803的材料，並將上述半導體晶粒接合在一起。然而，也可使用任何適合的接合方法(例如，銅-銅接合)來接合第一半導體晶粒201、第二半導體晶粒203、第三半導體晶粒901及第四半導體晶粒903。
第9A圖也繪示出可選擇性形成的第三半導體晶粒901及第四半導體晶粒903的封膠301。在一實施例中，可使用一第二模塑成型製程，以封裝第三半導體晶粒901及第四半導體晶粒903，且第二模塑成型製程類似於用以封裝第一半導體晶粒201及第二半導體晶粒203的第一模塑成型製程。例如，如同配合第3圖所述，將封膠301與第一半導體晶粒201、 第二半導體晶粒203、第三半導體晶粒901及第四半導體晶粒903一起放置於模塑成型腔室內。然而，第二模塑成型製程可類似於第一模塑成型製程，也可使用不同的材料及製程，皆涵蓋於本發明實施例的範圍內。
藉由封裝第三半導體晶粒901及第四半導體晶粒903，第一重佈線層801可位於兩組封膠301之間，其有助於支撐未直接位於第一半導體晶粒201、第二半導體晶粒203、第三半導體晶粒901及第四半導體晶粒903之間的部分的第一重佈線層801。藉由提供更好的保護，可降低或消除第一重佈線層801未來的劣化。
同樣地，可選擇性地平坦化用以封裝第三半導體晶粒901及第四半導體晶粒903的封膠301與第三半導體晶粒901及第四半導體晶粒903，以暴露出第三半導體晶粒901及第四半導體晶粒903。在一實施例中，平坦化及去除封膠301的步驟可包括使用化學機械研磨製程，以使封膠301產生反應，且研磨封膠301直到暴露出第三半導體晶粒901及第四半導體晶粒903。
此外，第9A圖只繪示出一個第三半導體晶粒901及一個第四半導體晶粒903，其僅作為說明而並非用以侷限本發明實施例的範圍。在另一實施例中，第9A圖繪示的一個第三半導體晶粒901可代表電性連接於第二半導體晶粒203的多個第三半導體晶粒901。同樣地，第9A圖繪示的一個第四半導體晶粒903可代表電性連接於第一半導體晶粒201的多個第四半導體晶粒903。可使用任何第三半導體晶粒901及第四半 導體晶粒903的數量的組合，且所有上述組合皆涵蓋於本發明實施例的範圍內。
第9B圖係繪示出第三半導體晶粒901及第四半導體晶粒903的另一種配置。在此實施例中，第三半導體晶粒901及第四半導體晶粒903不只側向突出第一半導體晶粒201及第二半導體晶粒203，更分別偏移第一半導體晶粒201及第二半導體晶粒203。在一實施例中，第三半導體晶粒901及第四半導體晶粒903偏移的一距離d1大約為100微米至3毫米的範圍(例如，1.2毫米)。
一底膠材料905可選擇性地注射或形成於第一半導體晶粒201、第二半導體晶粒203、第三半導體晶粒901及第四半導體晶粒903之間。例如，底膠材料905可包括一液態環氧化物，其分布於第一半導體晶粒201、第二半導體晶粒203、第三半導體晶粒901及第四半導體晶粒903之間，並加以固化及硬化。使用底膠材料905，可避免第二外部連接器803內出現典型地由於熱應力所造成的破裂。
另外，變形凝膠或矽橡膠(未繪示)可形成於第一半導體晶粒201、第二半導體晶粒203、第三半導體晶粒901及第四半導體晶粒903之間，以有助於避免第二外部連接器803內發生破裂。可透過在第一半導體晶粒201、第二半導體晶粒203、第三半導體晶粒901及第四半導體晶粒903之間注射或放置凝膠或橡膠，形成變形凝膠或矽橡膠。變形凝膠或矽橡膠也在後續的製程期間提供應力的釋放。
第10A圖係繪示出去除第二承載晶圓601及第二 黏著層603，及形成連接至第一外部連接器217的第三外部連接器1001。在一實施例中，第二黏著層603為熱釋放層，可透過將第二黏著層603的溫度增加至大約大於200℃，使第二承載晶圓601容易去除，以去除第二承載晶圓601及第二黏著層603。另外，在一實施例中，第二黏著層603為紫外光膠，可透過紫外光照射第二黏著層603，以去除第二承載晶圓601及第二黏著層603。
當去除第二承載晶圓601及第二黏著層603後，可形成第三外部連接器1001，與第一外部連接器217接觸。在一實施例中，第三外部連接器1001可為接觸凸塊(例如，控制塌陷高度晶片連接器或微凸塊)，且可包括一材料(例如，錫)或其他適合的材料(例如，銀或銅)。在一實施例中，第三外部連接器1001為焊錫凸塊，且可透過以下步驟形成：先透過任何適合的方法(例如，蒸鍍製程、電鍍製程、印刷製程、焊料轉移、植球等等)，形成較佳厚度大約為100微米的一層錫。當錫層形成於結構上後，進行一回流製程，以將材料塑形為所需的凸塊形狀。
第10A圖也繪示出將第一半導體晶粒201及第二半導體晶粒203連接至一第二基板1022。使用第二基板1022，可支撐及保護第一半導體晶粒201及第二半導體晶粒203，也可用以提供位於第一半導體晶粒201及第二半導體晶粒203上的第三外部連接器1001與外部裝置(未繪示)的連接。在一實施例中，第二基板1022可為一印刷電路板，也可為堆疊多層的高分子材料(例如，雙馬來醯亞胺三氮雜苯(bismaleimide triazine，BT)樹脂、環氧樹脂玻璃纖維FR-4或類似的材料)薄層所形成的一多層基板。然而，也可使用任何其他適合的基板(例如，有機基板、陶瓷基板或類似的基板)，且可提供第一半導體晶粒201及第二半導體晶粒203的支撐及連接的所有上述基板皆涵蓋於本發明實施例的範圍內。
第10B圖係詳細繪示出第10A圖中虛線1020圍繞的部分。如圖所示，第一外部連接器217從第一凸塊下金屬層1003延伸穿過封膠301。因此，封膠301可提供第一外部連接器217額外的支撐及保護，同時也提供第一半導體晶粒201其餘部分的支撐及保護。
第10C及10D圖係繪示出可選擇性地形成保護層221，以保護第一外部連接器217的實施例。第10C圖係繪示出一實施例，可透過平坦化製程(例如，化學機械研磨製程)，形成與第一外部連接器217的一上表面共平面的保護層221。第10D圖係繪示出另一實施例，保護層221保護一部分的第一外部連接器217，但未延伸至第一外部連接器217的上表面。
藉由使用上述實施例，在晶片-晶圓製程或(晶片-晶圓)-基板製程中，一頂部晶粒(例如，第三半導體晶粒901或第四半導體晶粒903)可比一底部晶粒(例如，第一半導體晶粒201或第二半導體晶粒203)側向突出或具有較大的尺寸。透過使用球柵陣列結構連接第一半導體晶粒201、第二半導體晶粒203、第三半導體晶粒901及第四半導體晶粒903，上述實施例可容許尺寸的縮小，且也可增加製程的彈性，例如，可在貼附至另一基板(例如，印刷電路板)之前，將第一半導體晶粒201 及第二半導體晶粒203連接於第三半導體晶粒901及第四半導體晶粒903。上述製程彈性表示貼附至印刷電路板的步驟可省略或重新配置，進而可能降低組裝成本。
第11圖係繪示出又另一實施例，一第二重佈線層1101形成於第一半導體晶粒201及第二半導體晶粒203的第一側202上。在一實施例中，可在去除封膠301以暴露出第一外部連接器217之後及在去除第一承載晶圓101之前，形成第二重佈線層1101。可透過類似於配合第8圖所述的第一重佈線層801的形成方法及材料，形成第二重佈線層1101。舉例來說，第二重佈線層1101可包括兩層由金屬(例如，鋁、銅、鎢、鈦及其組合)所構成的導電層，且可透過化學氣相沉積製程及圖案化製程而形成。然而，也可使用不同於第一重佈線層801的材料及製程，形成第二重佈線層1101。
第12圖係繪示出經過以下步驟所得到的結構。在去除第一承載晶圓101之後，透過第二黏著層603，將第二承載晶圓601貼附於第二重佈線層1101。將第一半導體晶粒201及第二半導體晶粒203薄化，以形成基板通孔電極701。在第一半導體晶粒201及第二半導體晶粒203的第二側204上形成第一重佈線層801及第二外部連接器803。將第三半導體晶粒901及第四半導體晶粒903接合於第一半導體晶粒201及第二半導體晶粒203。
第13A至13B圖係繪示出從第二重佈線層1101去除第二承載晶圓601及第二黏著層603，及形成與第二重佈線層1101連接的第四外部連接器1307。第13B圖係詳細繪示出 第13A圖中虛線1320劃分的區域。在一實施例中，第二黏著層603為熱釋放層，可透過增加第二黏著層603的溫度直到可去除第二承載晶圓601，以去除第二承載晶圓601。
去除第二承載晶圓601後，一第三鈍化護層1301可形成於第二重佈線層1101上，以保護第二重佈線層1101。第三鈍化護層1301可由一種或一種以上的適合的介電材料(例如，氧化矽、氮化矽、低介電常數材料(例如，碳摻雜氧化物)、極低介電常數材料(例如，多孔碳摻雜二氧化矽)、其組合或類似的材料)所構成。可透過一製程(例如，化學氣相沉積製程)形成第三鈍化護層1301，然而，也可使用任何適合的製程。第三鈍化護層1301的厚度可大約為0.2微米至18微米的範圍(例如，0.925微米)。
一第四鈍化護層1303可形成於第三鈍化護層1301上，以提供更進一步的保護。在一實施例中，第四鈍化護層1303可由一高分子(例如，聚亞醯胺)所形成，或可由類似於第三鈍化護層1301的材料(例如，氧化矽、氮化矽、低介電常數材料、極低介電常數材料、其組合或類似的材料)所形成。第四鈍化護層1303的厚度可大約為0.2微米至15微米的範圍(例如，大約為5微米)。
在形成第四鈍化護層1303之後，可透過光微影罩幕製程及蝕刻製程，圖案化第三鈍化護層1301及第四鈍化護層1303，以暴露出部分的第二重佈線層1101。當暴露出第二重佈線層1101後，可形成與第二重佈線層1101電性接觸的第二凸塊下金屬層1305。第二凸塊下金屬層1305可包括一層導 電材料(例如，鈦層或鎳層)。第二凸塊下金屬層1305可包括多層子層(未繪示)。本發明所屬技術領域中具有通常知識者可以理解的是，許多適合的材料及材料層的配置(例如，鉻/鉻銅合金/銅/金的配置、鈦/鈦鎢/銅的配置或銅/鎳/金的配置)可適用於形成第二凸塊下金屬層1305。任何用於形成第二凸塊下金屬層1305的適合的材料或材料層皆可涵蓋於本發明實施例的範圍內。形成第二凸塊下金屬層1305的製程(例如，濺鍍製程、蒸鍍製程或電漿增強氣相沉積製程)，取決於所需的材料。第二凸塊下金屬層1305的厚度可大約為0.7微米至10微米的範圍(例如，大約為5微米)。
在形成第二凸塊下金屬層1305之後，可形成與第二重佈線層1101電性連接的第四外部連接器1307。第四外部連接器1307可為接觸凸塊(例如，微凸塊或控制塌陷高度晶片連接器)，且可包括一材料(例如，錫)或其他適合的材料(例如，銀或銅)。在一實施例中，第四外部連接器1307為焊錫凸塊，且可透過以下步驟形成：先透過任何適合的方法(例如，蒸鍍製程、電鍍製程、印刷製程、焊料轉移、植球等等)，形成較佳厚度大約為100微米的一層錫。當錫層形成於結構上後，進行一回流製程，以將材料塑形為所需的凸塊形狀。
第13C及13D圖係繪示出可選擇性地形成保護層221，以保護第一外部連接器217的實施例。第13C圖係繪示出一實施例，可透過平坦化製程(例如，化學機械研磨製程)，形成與第一外部連接器217的一上表面共平面的保護層221。第13D圖係繪示出另一實施例，保護層221保護一部分的第一 外部連接器217，但未延伸至第一外部連接器217的上表面。
雖然未繪示於第13A至13B圖，在本實施例中，也可選擇性地封裝第三半導體晶粒901及第四半導體晶粒903。在一實施例中，可透過類似於配合第3圖所述的封裝第一半導體晶粒201及第二半導體晶粒203的方法，封裝第三半導體晶粒901及第四半導體晶粒903。然而，也可使用另外的封膠或不同的方法，封裝第三半導體晶粒901及第四半導體晶粒903。
藉由使用第11至13B圖所述的實施例，在第一半導體晶粒201及第二半導體晶粒203兩側上皆形成重佈線層(例如，第一重佈線層801及第二重佈線層1101)，可增加扇出區域及所需的連接之控制及配置的彈性，進而增加配置及空間的效率。
在第1至13D圖所述的每一實施例之後，可更包括選擇性地進行一單體化(singlulation)製程(未繪示)，其可將一第一封裝結構(例如，包括第一半導體晶粒201及第四半導體晶粒903)與一第二封裝結構(例如，包括第二半導體晶粒203第三半導體晶粒901)分開。可透過一鑽石鋸刀(diamond coated saw blade)，切割第一封裝結構與第二封裝結構之間的一切割區，進行單體化製程，然而，也可使用任何適合的分離方法(例如，透過連續一次或一次以上的蝕刻，以分離第一封裝結構與第二封裝結構)。
配合本發明一實施例之一種半導體裝置的製造方法，包括在一第一承載晶圓上放置一或多個的底部晶粒。在一 或多個的底部晶粒之間形成一第一模塑成型材料，而暴露出位於一或多個的底部晶粒上的複數電性接觸窗。將一或多個的底部晶粒及第一模塑成型材料貼附至一第二承載晶圓。將一或多個的底部晶粒薄化，以暴露出穿透一或多個的底部晶粒的複數通孔電極。沿著一或多個的底部晶粒的一背側，形成連接通孔電極的複數電性連接器。將一或多個的頂部晶粒貼附至一或多個的底部晶粒。
配合本發明另一實施例之一種半導體裝置的製造方法，包括將一第一半導體晶粒貼附至一載具，第一半導體晶粒包括複數第一外部接觸窗。將一第二半導體晶粒貼附至載具，第二半導體晶粒包括複數第二外部接觸窗。以一封膠封裝第一半導體晶粒及第二半導體晶粒。去除一部分的封膠，以暴露出第一外部接觸窗及第二外部接觸窗。將第一半導體晶粒及第二半導體晶粒薄化，以暴露出第一半導體晶粒內的複數第一基板通孔電極及第二半導體晶粒內的複數第二基板通孔電極。將一第三半導體晶粒電性連接至第一基板通孔電極，及將一第四半導體晶粒電性連接至第二基板通孔電極。
配合本發明一實施例之一種半導體裝置，包括以一第一封膠封裝的一第一半導體晶粒。至少一個基板通孔電極延伸穿透至少一部分的第一半導體晶粒，且從第一半導體晶粒的一第一側上暴露出。複數第一外部連接器位於第一半導體晶粒的一第二側上。一第三半導體晶粒，與至少一個基板通孔電極電性連接，且延伸至第一封膠上方。
雖然本發明已以較佳實施例揭露如上，然其並非 用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。
201‧‧‧第一半導體(或底部)晶粒
202‧‧‧第一側
203‧‧‧第二半導體(或底部)晶粒
204‧‧‧第二側
217‧‧‧第一外部連接器
301‧‧‧封膠
701‧‧‧基板通孔電極
801‧‧‧第一重佈線層
803‧‧‧第二外部連接器
901‧‧‧第三半導體(或頂部)晶粒
903‧‧‧第四半導體(或頂部)晶粒
1001‧‧‧第三外部連接器
1020‧‧‧虛線
1022‧‧‧第二基板

Claims (12)

  1. 一種半導體裝置的製造方法，包括：在一第一承載晶圓上放置一或多個的底部晶粒；在該一或多個的底部晶粒之間形成一第一模塑成型材料，而暴露出該一或多個的底部晶粒上的複數電性接觸窗，其中暴露出的該等電性接觸窗位於該一或多個的底部晶粒背向該第一承載晶圓的一側；將該一或多個的底部晶粒及該第一模塑成型材料貼附至一第二承載晶圓；將該一或多個的底部晶粒薄化，以暴露出穿透該一或多個的底部晶粒的複數通孔電極；沿著該一或多個的底部晶粒的一背側，形成連接該等通孔電極的複數電性連接器；以及將一或多個的頂部晶粒貼附至該一或多個的底部晶粒。
  2. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該第一模塑成型材料覆蓋該一或多個的底部晶粒的一底側，且其中形成該第一模塑成型材料的步驟包括薄化該第一模塑成型材料，以暴露出位於該一或多個的底部晶粒上的該等電性接觸窗。
  3. 如申請專利範圍第1項所述之半導體裝置的製造方法，更包括在該一或多個的底部晶粒上形成一重佈線層，其中該重佈線層延伸至該第一模塑成型材料的上方，且更包括在該一或多個的頂部晶粒上形成一第二模塑成型材料。
  4. 一種半導體裝置的製造方法，包括： 將一第一半導體晶粒貼附至一載具，該第一半導體晶粒包括複數第一外部接觸窗；將一第二半導體晶粒貼附至該載具，該第二半導體晶粒包括複數第二外部接觸窗；以一封膠封裝該第一半導體晶粒及該第二半導體晶粒；去除一部分的該封膠，以暴露出該等第一外部接觸窗及該等第二外部接觸窗；將該第一半導體晶粒及該第二半導體晶粒薄化，以暴露出該第一半導體晶粒內的複數第一基板通孔電極及該第二半導體晶粒內的複數第二基板通孔電極；以及將一第三半導體晶粒電性連接至該等第一基板通孔電極，及將一第四半導體晶粒電性連接至該等第二基板通孔電極。
  5. 如申請專利範圍第4項所述之半導體裝置的製造方法，更包括封裝該第三半導體晶粒及該第四半導體晶粒及在封裝該第一半導體晶粒及該第二半導體晶粒後，在該等第一外部接觸窗上形成複數第三外部接觸窗。
  6. 如申請專利範圍第4項所述之半導體裝置的製造方法，更包括在將該第一半導體晶粒及該第二半導體晶粒薄化之前，形成與該等第一外部接觸窗電性連接的一重佈線層，且更包括在將該第三半導體晶粒電性連接至該等第一基板通孔電極之後，形成與該重佈線層電性連接的複數第三外部接觸窗。
  7. 如申請專利範圍第4項所述之半導體裝置的製造方法，其中 將該第三半導體晶粒電性連接至該等第一基板通孔電極的步驟更包括該第三半導體晶粒自該第一半導體晶粒偏移。
  8. 如申請專利範圍第4項所述之半導體裝置的製造方法，其中在將該第三半導體晶粒電性連接至該等第一基板通孔電極之後，該第三半導體晶粒自該第一半導體晶粒側向突出。
  9. 一種半導體裝置，包括：一第一半導體晶粒，以一第一封膠封裝；至少一個基板通孔電極，延伸穿透至少一部分的該第一半導體晶粒，且從該第一半導體晶粒的一第一側上暴露出；複數第一外部連接器，位於該第一半導體晶粒的一第二側上；一第一重佈線層，與該等第一外部連接器電性連接，且延伸至該第一封膠上方；以及一第三半導體晶粒，與該至少一個基板通孔電極電性連接，且延伸至該第一封膠上方。
  10. 如申請專利範圍第9項所述之半導體裝置，更包括：一第二半導體晶粒，以該第一封膠封裝；以及一第四半導體晶粒，與該第二半導體晶粒電性連接，且延伸至該第一封膠上方，其中透過一第二封膠，封裝該第三半導體晶粒及該第四半導體晶粒。
  11. 如申請專利範圍第10項所述之半導體裝置，更包括一第二重佈線層，與該至少一個基板通孔電極電性連接，且延伸至該第一封膠上方。
  12. 如申請專利範圍第9項所述之半導體裝置，其中該第三半導 體晶粒自該第一半導體晶粒偏移。
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US20140001645A1 (en) 2014-01-02
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US10109613B2 (en) 2018-10-23
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