US20110159639A1 - Method for Making a Stackable Package - Google Patents
Method for Making a Stackable Package Download PDFInfo
- Publication number
- US20110159639A1 US20110159639A1 US12/856,401 US85640110A US2011159639A1 US 20110159639 A1 US20110159639 A1 US 20110159639A1 US 85640110 A US85640110 A US 85640110A US 2011159639 A1 US2011159639 A1 US 2011159639A1
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- Prior art keywords
- chip
- carrier
- layer
- rdl
- redistribution layer
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- the present invention relates to a method for making a stackable package, and more particularly to a method for making a stackable package having a redistribution layer and a through via.
- FIG. 1 shows a cross-sectional view of a conventional stackable package.
- the conventional stackable package 1 comprises an interposer 10 and a chip 20 .
- the interposer 10 comprises a body 11 , a plurality of through vias 12 , a plurality of conductive traces 13 , a plurality of pads 14 and a plurality of solder balls 15 .
- the body 11 has a first surface 111 and a second surface 112 .
- the through vias 12 penetrate through the body 11 , and are exposed to the first surface 111 and the second surface 112 .
- the conductive traces 13 are disposed on the first surface 111 of the body 11 , and electrically connected to the through vias 12 .
- the pads 14 are disposed on the second surface 112 of the body 11 , and electrically connected to the through vias 12 .
- the solder balls 15 are disposed on the pads 14 .
- the chip 20 is disposed on the interposer 10 .
- the chip 20 comprises a plurality of chip pads 21 and a plurality of bumps 22 .
- the bumps 22 are disposed between the chip pads 21 and the conductive traces 13 , and the chip 20 is electrically connected to the interposer 10 by the bumps 22 .
- the conventional stacked package 1 has the following disadvantages.
- the chip 20 of the conventional stacked package 1 is electrically connected to exterior elements by the interposer 10 .
- the interposer 10 increases the thickness of the product, and the manufacturing processes of the interposer 10 is too complicated, so that the manufacturing cost is increased.
- the gap between the bumps 22 of the chip 20 is too small, so that an underfill (not shown) is difficult to be formed therein to encapsulate the bumps 22 .
- the present invention is directed to a method for making a stackable package.
- the method comprises the following steps: (a) providing a first carrier having a surface; (b) disposing at least one chip on a surface of the first carrier, wherein the chip comprises a first surface, a second surface, an active circuit layer and at least one conductive via, the active circuit layer is disposed in the chip and exposed to the second surface, the conductive via is disposed in the chip and connected to the active circuit layer; (c) forming a molding compound on the surface of the first carrier, so as to encapsulate the chip, wherein the molding compound comprises a surface attached to the surface of the first carrier; (d) removing the first carrier, so as to expose the second surface of the chip and the surface of the molding compound; (e) forming a first redistribution layer (RDL) and at least one first bump, wherein the first redistribution layer (RDL) is disposed on the second surface of the chip and the surface of the molding compound, and electrically connected to the conductive
- the present invention is further directed to a method for making a stackable package.
- the method comprises the following steps: (a) providing a first carrier having a surface; (b) disposing at least one chip on a surface of the first carrier, wherein the chip comprises a first surface, a second surface and an active circuit layer, the active circuit layer is disposed in the chip and exposed to the second surface; (c) forming a molding compound on the surface of the first carrier, so as to encapsulate the chip, wherein the molding compound comprises a surface attached to the surface of the first carrier; (d) removing the first carrier, so as to expose the second surface of the chip and the surface of the molding compound; (e) forming a first redistribution layer (RDL) and at least one first bump, wherein the first redistribution layer (RDL) is disposed on the second surface of the chip and the surface of the molding compound, and electrically connected to the active circuit layer, the first bump is disposed on the first redistribution layer (RDL), and electrically connected
- the second redistribution layer enables the stackable package to have more flexibility to be utilized. Moreover, the through via is formed in the chip, and electrically connected to the first redistribution layer (RDL), and an extra element is unnecessary. As a result, the manufacturing cost and the size of the product are reduced.
- RDL redistribution layer
- FIG. 1 is a cross-sectional view of a conventional stackable package
- FIG. 2 is a flow chart of a method for making a stackable package according to a first embodiment of the present invention
- FIGS. 3 to 9 are schematic views of the method for making a stackable package according to the first embodiment of the present invention.
- FIG. 10 is a flow chart of a method for making a stackable package according to a second embodiment of the present invention.
- FIGS. 11 to 18 are schematic views of the method for making a stackable package according to the second embodiment of the present invention.
- FIGS. 19 to 20 are schematic views showing the application of a stackable package according to the present invention.
- FIG. 2 shows a flow chart of a method for making a stackable package according to a first embodiment of the present invention.
- a first carrier 31 is provided.
- the first carrier 31 has a surface 311 .
- at least one chip 32 is disposed on the surface 311 of the first carrier 31 .
- the chip 32 comprises a first surface 321 , a second surface 322 , an active circuit layer 323 and at least one conductive via 326 .
- the active circuit layer 323 is disposed in the chip 32 , and exposed to the second surface 322 .
- the conductive via 326 is disposed in the chip 32 , and connected to the active circuit layer 323 .
- the chip 32 is a known-good die, and the second surface 322 of the chip 32 is adhered to the surface 311 of the first carrier 31 by an adhesive 33 .
- the chip 32 further comprises at least one hole 325 .
- the conductive via 326 comprises a first insulating layer (not shown) and a conductor (not shown).
- the first insulating layer is disposed on a side wall of the hole 325 , and defines a first groove (not shown).
- the conductor fills up the first groove.
- a second chip (not shown) can be disposed side by side with the chip 32 on the surface 311 of the first carrier 31 , and the second chip is also a known-good die.
- a molding compound 34 is formed on the surface 311 of the first carrier 31 , so as to encapsulate the chip 32 .
- the molding compound 34 comprises a second surface 342 attached to the surface 311 of the first carrier 31 .
- the second surface 342 of the molding compound 34 is level with the second surface 322 of the chip 32 .
- the molding compound 34 is used as a support of the chip 32 , so as to increase the thickness and the strength of the chip 32 . Therefore, a first surface 341 of the molding compound 34 is used as a supporting surface of the following manufacturing process, so as to facilitate processing the second surface 322 of the chip 32 .
- the first carrier 31 is removed, preferably, the adhesive 33 is removed at the same time, so as to expose the second surface 322 of the chip 32 and the second surface 342 of the molding compound 34 .
- the molding compound 34 is used as a support of the chip 32 , therefore a first redistribution layer (RDL) 35 and at least one first bump 36 are formed, and another carrier is not needed, as shown in step S 25 .
- the first redistribution layer (RDL) 35 is disposed on the second surface 322 of the chip 32 and the second surface 342 of the molding compound 34 , and electrically connected to the conductive via 326 by the active circuit layer 323 .
- the first bump 36 is disposed on the first redistribution layer (RDL) 35 , and electrically connected to the active circuit layer 323 and the conductive via 326 by the first redistribution layer (RDL) 35 .
- the first redistribution layer (RDL) 35 comprises to a protective layer 352 , a first circuit layer 353 and an under ball metal layer (UBM) 354 .
- the first circuit layer 353 is disposed in the protective layer 352 .
- the protective layer 352 has a first surface 355 and a second surface 356 .
- the second surface 356 has at least one second opening, so as to expose part of the first circuit layer 353 .
- the under ball metal layer (UBM) 354 is disposed in the second opening, and electrically connected to the first circuit layer 353 .
- the first bump 36 is disposed on the under ball metal layer (UBM) 354 .
- the first redistribution layer (RDL) 35 is used to re-distribute the position of the under ball metal layer (UBM) 354 and the first bump 36 , to match the position of electrical contact points of other package.
- the stackable package 2 ( FIG. 9 ) made by the method according to the present invention is more flexible in application.
- a second carrier 37 is provided.
- a surface 351 of the first redistribution layer (RDL) 35 is disposed on the second carrier 37 by a glue layer 38 , and the glue layer 38 encapsulates the first bump 36 .
- the glue layer 38 is a peelable glue layer, and formed by spin coating. Therefore, the glue layer 38 protects the first bump 36 , and the second carrier 37 is used as a support of the first redistribution layer (RDL) 35 . Therefore, a surface 371 of the second carrier 37 is used as a supporting surface of the following manufacturing process, so as to facilitate processing the first surface 341 of the molding compound 34 .
- step S 28 part of the chip 32 and part of the molding compound 34 are removed, so as to expose the conductive via 326 ( FIG. 6 ) to the first surface 321 of the chip 32 , and a through via 324 is formed. That is, the conductive via 326 is substantially the same as the through via 324 , and the difference between the conductive via 326 and the through via 324 is that the through via 324 is exposed to the first surface 321 of the chip 32 .
- the first surface 321 of the chip 32 and part of the first surface 341 of the molding compound 34 are ground first, and then trimmed by chemical-mechanical polishing (CMP).
- part of the chip 32 and part of the molding compound 34 can be removed only by chemical-mechanical polishing (CMP).
- CMP chemical-mechanical polishing
- part of the through via 324 is exposed to the first surface 321 of the chip 32 , and forms a contact point.
- a second redistribution layer (RDL) 39 is formed on the first surface 321 of the chip 32 .
- the second redistribution layer (RDL) 39 is electrically connected to the through via 324 .
- the second redistribution layer (RDL) 39 comprises a protective layer 391 , a second circuit layer 392 and an under ball metal layer (UBM) 393 .
- the second circuit layer 392 is disposed in the protective layer 391 .
- the protective layer 391 has a first surface 394 and a second surface 395 .
- the second surface 395 has at least one second opening, so as to expose part of the second circuit layer 392 .
- the under ball metal layer (UBM) 393 is disposed in the second opening, and electrically connected to the second circuit layer 392 . Therefore, the second redistribution layer (RDL) 39 is used to re-distribute the position of the contact point of the through via 324 , to match the position of electrical contact points of other package. As a result, the stackable package 2 ( FIG. 9 ) made by the method according to the present invention is more flexible in application.
- the glue layer 38 can choose to be softened by heated or under ultraviolet ray according to the characteristic of the material of the glue layer 38 , so as to remove the glue layer 38 .
- the glue layer 38 is a peelable material with better thermoplasticity, so that the glue layer 38 can be softened by heating, so as to remove the glue layer 38 .
- the glue layer 38 can be a material that can be softened under ultraviolet ray, so that the glue layer 38 can be softened by providing ultraviolet ray, so as to remove the glue layer 38 . Therefore, the glue layer 38 protects the first bump 36 during the manufacturing process.
- FIG. 10 shows a flow chart of a method for making a stackable package according to a second embodiment of the present invention.
- FIGS. 11 to 18 show schematic views of the method for making a stackable package according to the second embodiment of the present invention.
- the method for making a stackable package according to the second embodiment is substantially the same as the method for making a stackable package according to the first embodiment ( FIGS. 3 to 9 ), and the same elements are designated by the same reference numbers.
- step S 36 the second carrier 37 is provided (step S 36 ), and the surface 351 of the first redistribution layer (RDL) 35 is disposed on the second carrier 37 by the glue layer 38 (step S 37 ). Then, as shown in FIG. 15 , part of the chip 32 and part of the molding compound 34 (step S 38 ) are removed.
- RDL redistribution layer
- a through via 324 is formed in the chip 32 (step S 39 ).
- the through via 324 is connected to the active circuit layer 323 , and exposed to the first surface 321 of the chip 32 .
- the same processes as the method according to the first embodiment are conducted, that is, as shown in FIG. 17 , the second redistribution layer (RDL) 39 is formed (step S 40 ).
- the second carrier 37 and the glue layer 38 are removed (step S 41 ), so as to form the stackable package 2 according to the present invention.
- a second package 3 is further stacked on the stackable package 2 , so as to form a double-layered stacked package.
- at least one conductive element for example, a second bump 40
- RDL redistribution layer
- a third package 4 can be further stacked on the second package 3 , so as to form a third-layered stacked package.
- the stackable package 2 is a processor
- the second package 3 is a radio frequency (RF) device
- the third package 4 is a memory.
- the second redistribution layer (RDL) 39 is used to re-distribute the position of the contact point of the through via 324 , to match the position of electrical contact points of other package.
- the stackable package 2 ( FIG. 9 ) made by the method according to the present invention is more flexible in application, for example, the stackable package 2 according to the present invention can be applied to the three following situation.
- the molding compound 34 of the stackable package 2 encapsulates a plurality of chips 32 , and after another package having the same size of the stackable package 2 is stacked thereon, a singulation process is conducted.
- the molding compound 34 of the stackable package 2 encapsulates a plurality of chips 32 , and after a plurality of chips are stacked thereon, a singulation process is conducted.
- a singulation process is conducted to the stackable package 2 first, and then, another chip is stacked thereon.
- the through via 324 is formed in the chip 32 , and electrically connected to the first redistribution layer (RDL) 35 , and an extra element is unnecessary. As a result, the manufacturing cost and the size of the product are reduced.
- RDL redistribution layer
Abstract
The present invention relates to a method for making a stackable package. The method includes the following steps: (a) providing a first carrier; (b) disposing at least one chip on the first carrier; (c) forming a molding compound so as to encapsulate the chip; (d) removing the first carrier; (e) forming a first redistribution layer and at least one first bump; (f) providing a second carrier; (g) disposing on the second carrier; (h) removing part of the chip and part of the molding compound; (i) forming a second redistribution layer; and (j) removing the second carrier. Therefore, to the second redistribution layer enables the stackable package to have more flexibility to be utilized.
Description
- 1. Field of the Invention
- The present invention relates to a method for making a stackable package, and more particularly to a method for making a stackable package having a redistribution layer and a through via.
- 2. Description of the Related Art
-
FIG. 1 shows a cross-sectional view of a conventional stackable package. The conventional stackable package 1 comprises aninterposer 10 and achip 20. Theinterposer 10 comprises abody 11, a plurality of throughvias 12, a plurality ofconductive traces 13, a plurality ofpads 14 and a plurality ofsolder balls 15. Thebody 11 has afirst surface 111 and asecond surface 112. The throughvias 12 penetrate through thebody 11, and are exposed to thefirst surface 111 and thesecond surface 112. Theconductive traces 13 are disposed on thefirst surface 111 of thebody 11, and electrically connected to the throughvias 12. Thepads 14 are disposed on thesecond surface 112 of thebody 11, and electrically connected to the throughvias 12. Thesolder balls 15 are disposed on thepads 14. Thechip 20 is disposed on theinterposer 10. Thechip 20 comprises a plurality ofchip pads 21 and a plurality ofbumps 22. Thebumps 22 are disposed between thechip pads 21 and theconductive traces 13, and thechip 20 is electrically connected to theinterposer 10 by thebumps 22. - The conventional stacked package 1 has the following disadvantages. The
chip 20 of the conventional stacked package 1 is electrically connected to exterior elements by theinterposer 10. However, theinterposer 10 increases the thickness of the product, and the manufacturing processes of theinterposer 10 is too complicated, so that the manufacturing cost is increased. Moreover, the gap between thebumps 22 of thechip 20 is too small, so that an underfill (not shown) is difficult to be formed therein to encapsulate thebumps 22. - Therefore, it is necessary to provide a method for making a stackable package to solve the above problems.
- The present invention is directed to a method for making a stackable package. The method comprises the following steps: (a) providing a first carrier having a surface; (b) disposing at least one chip on a surface of the first carrier, wherein the chip comprises a first surface, a second surface, an active circuit layer and at least one conductive via, the active circuit layer is disposed in the chip and exposed to the second surface, the conductive via is disposed in the chip and connected to the active circuit layer; (c) forming a molding compound on the surface of the first carrier, so as to encapsulate the chip, wherein the molding compound comprises a surface attached to the surface of the first carrier; (d) removing the first carrier, so as to expose the second surface of the chip and the surface of the molding compound; (e) forming a first redistribution layer (RDL) and at least one first bump, wherein the first redistribution layer (RDL) is disposed on the second surface of the chip and the surface of the molding compound, and electrically connected to the conductive via by the active circuit layer, the first bump is disposed on the first redistribution layer (RDL), and electrically connected to the active circuit layer and the conductive via by the first redistribution layer (RDL); (f) providing a second carrier; (g) disposing a surface of the first redistribution layer (RDL) on the second carrier; (h) removing part of the chip and part of the molding compound, so as to expose the conductive via to the first surface of the chip, and form a through via; (i) forming a second redistribution layer (RDL) on the first surface of the chip, wherein the second redistribution layer (RDL) is electrically connected to the through via; and (j) removing the second carrier.
- The present invention is further directed to a method for making a stackable package. The method comprises the following steps: (a) providing a first carrier having a surface; (b) disposing at least one chip on a surface of the first carrier, wherein the chip comprises a first surface, a second surface and an active circuit layer, the active circuit layer is disposed in the chip and exposed to the second surface; (c) forming a molding compound on the surface of the first carrier, so as to encapsulate the chip, wherein the molding compound comprises a surface attached to the surface of the first carrier; (d) removing the first carrier, so as to expose the second surface of the chip and the surface of the molding compound; (e) forming a first redistribution layer (RDL) and at least one first bump, wherein the first redistribution layer (RDL) is disposed on the second surface of the chip and the surface of the molding compound, and electrically connected to the active circuit layer, the first bump is disposed on the first redistribution layer (RDL), and electrically connected to the active circuit layer by the first redistribution layer (RDL); (f) providing a second carrier; (g) disposing a surface of the first redistribution layer (RDL) on the second carrier; (h) removing part of the chip and part of the molding compound; (i) forming at least one through via in the chip, wherein the through via is connected to the active circuit layer and exposed to the first surface of the chip; (j) forming a second redistribution layer (RDL) on the first surface of the chip, wherein the second redistribution layer (RDL) is electrically connected to the through via; and (k) removing the second carrier.
- Therefore, the second redistribution layer enables the stackable package to have more flexibility to be utilized. Moreover, the through via is formed in the chip, and electrically connected to the first redistribution layer (RDL), and an extra element is unnecessary. As a result, the manufacturing cost and the size of the product are reduced.
-
FIG. 1 is a cross-sectional view of a conventional stackable package; -
FIG. 2 is a flow chart of a method for making a stackable package according to a first embodiment of the present invention; -
FIGS. 3 to 9 are schematic views of the method for making a stackable package according to the first embodiment of the present invention; -
FIG. 10 is a flow chart of a method for making a stackable package according to a second embodiment of the present invention; -
FIGS. 11 to 18 are schematic views of the method for making a stackable package according to the second embodiment of the present invention; and -
FIGS. 19 to 20 are schematic views showing the application of a stackable package according to the present invention. -
FIG. 2 shows a flow chart of a method for making a stackable package according to a first embodiment of the present invention. First, as shown inFIG. 3 and step S21, afirst carrier 31 is provided. Thefirst carrier 31 has asurface 311. As shown in step S22, at least onechip 32 is disposed on thesurface 311 of thefirst carrier 31. Thechip 32 comprises afirst surface 321, asecond surface 322, anactive circuit layer 323 and at least one conductive via 326. Theactive circuit layer 323 is disposed in thechip 32, and exposed to thesecond surface 322. The conductive via 326 is disposed in thechip 32, and connected to theactive circuit layer 323. - In this embodiment, the
chip 32 is a known-good die, and thesecond surface 322 of thechip 32 is adhered to thesurface 311 of thefirst carrier 31 by an adhesive 33. Moreover, thechip 32 further comprises at least onehole 325. The conductive via 326 comprises a first insulating layer (not shown) and a conductor (not shown). The first insulating layer is disposed on a side wall of thehole 325, and defines a first groove (not shown). The conductor fills up the first groove. However, in other embodiments, a second chip (not shown) can be disposed side by side with thechip 32 on thesurface 311 of thefirst carrier 31, and the second chip is also a known-good die. It is understood that, the form of the second chip has no limitation, and the second chip can comprise a conductive via or not. Moreover, the conductive via 326 can further comprise a second insulating layer (not shown). The conductor is only disposed on a side wall of the first groove, and defines a second groove (not shown), and the second insulating layer fills up the second groove. In the present invention, only when thechip 32 is a known-good die, thechip 32 can be disposed on thefirst carrier 31, therefore the yield rate is increased. - As shown in
FIG. 4 and step S23, amolding compound 34 is formed on thesurface 311 of thefirst carrier 31, so as to encapsulate thechip 32. Themolding compound 34 comprises asecond surface 342 attached to thesurface 311 of thefirst carrier 31. In this embodiment, thesecond surface 342 of themolding compound 34 is level with thesecond surface 322 of thechip 32. Themolding compound 34 is used as a support of thechip 32, so as to increase the thickness and the strength of thechip 32. Therefore, afirst surface 341 of themolding compound 34 is used as a supporting surface of the following manufacturing process, so as to facilitate processing thesecond surface 322 of thechip 32. - As shown in
FIG. 5 and step S24, thefirst carrier 31 is removed, preferably, theadhesive 33 is removed at the same time, so as to expose thesecond surface 322 of thechip 32 and thesecond surface 342 of themolding compound 34. Meanwhile, themolding compound 34 is used as a support of thechip 32, therefore a first redistribution layer (RDL) 35 and at least onefirst bump 36 are formed, and another carrier is not needed, as shown in step S25. The first redistribution layer (RDL) 35 is disposed on thesecond surface 322 of thechip 32 and thesecond surface 342 of themolding compound 34, and electrically connected to the conductive via 326 by theactive circuit layer 323. Thefirst bump 36 is disposed on the first redistribution layer (RDL) 35, and electrically connected to theactive circuit layer 323 and the conductive via 326 by the first redistribution layer (RDL) 35. - In this embodiment, the first redistribution layer (RDL) 35 comprises to a
protective layer 352, afirst circuit layer 353 and an under ball metal layer (UBM) 354. Thefirst circuit layer 353 is disposed in theprotective layer 352. Theprotective layer 352 has afirst surface 355 and asecond surface 356. Thesecond surface 356 has at least one second opening, so as to expose part of thefirst circuit layer 353. The under ball metal layer (UBM) 354 is disposed in the second opening, and electrically connected to thefirst circuit layer 353. Thefirst bump 36 is disposed on the under ball metal layer (UBM) 354. Therefore, the first redistribution layer (RDL) 35 is used to re-distribute the position of the under ball metal layer (UBM) 354 and thefirst bump 36, to match the position of electrical contact points of other package. As a result, the stackable package 2 (FIG. 9 ) made by the method according to the present invention is more flexible in application. - As shown in
FIG. 6 and step S26, asecond carrier 37 is provided. As shown in step S27, asurface 351 of the first redistribution layer (RDL) 35 is disposed on thesecond carrier 37 by aglue layer 38, and theglue layer 38 encapsulates thefirst bump 36. In this embodiment, theglue layer 38 is a peelable glue layer, and formed by spin coating. Therefore, theglue layer 38 protects thefirst bump 36, and thesecond carrier 37 is used as a support of the first redistribution layer (RDL) 35. Therefore, asurface 371 of thesecond carrier 37 is used as a supporting surface of the following manufacturing process, so as to facilitate processing thefirst surface 341 of themolding compound 34. - As shown in
FIG. 7 and step S28, part of thechip 32 and part of themolding compound 34 are removed, so as to expose the conductive via 326 (FIG. 6 ) to thefirst surface 321 of thechip 32, and a through via 324 is formed. That is, the conductive via 326 is substantially the same as the through via 324, and the difference between the conductive via 326 and the through via 324 is that the through via 324 is exposed to thefirst surface 321 of thechip 32. In this embodiment, thefirst surface 321 of thechip 32 and part of thefirst surface 341 of themolding compound 34 are ground first, and then trimmed by chemical-mechanical polishing (CMP). However, in other embodiments, part of thechip 32 and part of themolding compound 34 can be removed only by chemical-mechanical polishing (CMP). In this embodiment, part of the through via 324 is exposed to thefirst surface 321 of thechip 32, and forms a contact point. - As shown in
FIG. 8 and step S29, a second redistribution layer (RDL) 39 is formed on thefirst surface 321 of thechip 32. The second redistribution layer (RDL) 39 is electrically connected to the through via 324. In this embodiment, the second redistribution layer (RDL) 39 comprises aprotective layer 391, asecond circuit layer 392 and an under ball metal layer (UBM) 393. Thesecond circuit layer 392 is disposed in theprotective layer 391. Theprotective layer 391 has afirst surface 394 and asecond surface 395. Thesecond surface 395 has at least one second opening, so as to expose part of thesecond circuit layer 392. The under ball metal layer (UBM) 393 is disposed in the second opening, and electrically connected to thesecond circuit layer 392. Therefore, the second redistribution layer (RDL) 39 is used to re-distribute the position of the contact point of the through via 324, to match the position of electrical contact points of other package. As a result, the stackable package 2 (FIG. 9 ) made by the method according to the present invention is more flexible in application. - As shown in
FIG. 9 and step S30, thesecond carrier 37 and theglue layer 38 are removed, and meanwhile, thestackable package 2 according to the present invention is formed. Preferably, theglue layer 38 can choose to be softened by heated or under ultraviolet ray according to the characteristic of the material of theglue layer 38, so as to remove theglue layer 38. In this embodiment, theglue layer 38 is a peelable material with better thermoplasticity, so that theglue layer 38 can be softened by heating, so as to remove theglue layer 38. However, in other embodiments, theglue layer 38 can be a material that can be softened under ultraviolet ray, so that theglue layer 38 can be softened by providing ultraviolet ray, so as to remove theglue layer 38. Therefore, theglue layer 38 protects thefirst bump 36 during the manufacturing process. -
FIG. 10 shows a flow chart of a method for making a stackable package according to a second embodiment of the present invention.FIGS. 11 to 18 show schematic views of the method for making a stackable package according to the second embodiment of the present invention. The method for making a stackable package according to the second embodiment is substantially the same as the method for making a stackable package according to the first embodiment (FIGS. 3 to 9 ), and the same elements are designated by the same reference numbers. - The difference between the method according to the second embodiment and the method according to the first embodiment is that after the
first carrier 31 is provided (step S31), thechip 32, which does not comprise the conductive via 326 as shown inFIG. 11 , is disposed on thesurface 311 of the first carrier 31 (step S32). Then, the same processes as the method according to the first embodiment are conducted, that is, as shown inFIG. 12 , themolding compound 34 are formed (step S33). Then, as shown inFIG. 13 , thefirst carrier 31 is removed (step S34). Meanwhile, themolding compound 34 is used as a support of thechip 32, therefore the first redistribution layer (RDL) 35 and thefirst bump 36 are formed (step S35), and another carrier is not needed. Then, as shown inFIG. 14 , thesecond carrier 37 is provided (step S36), and thesurface 351 of the first redistribution layer (RDL) 35 is disposed on thesecond carrier 37 by the glue layer 38 (step S37). Then, as shown inFIG. 15 , part of thechip 32 and part of the molding compound 34 (step S38) are removed. - Then, as shown in
FIG. 16 , a through via 324 is formed in the chip 32 (step S39). The through via 324 is connected to theactive circuit layer 323, and exposed to thefirst surface 321 of thechip 32. In the end, the same processes as the method according to the first embodiment are conducted, that is, as shown inFIG. 17 , the second redistribution layer (RDL) 39 is formed (step S40). Then, as shown inFIG. 18 , thesecond carrier 37 and theglue layer 38 are removed (step S41), so as to form thestackable package 2 according to the present invention. - Moreover, as shown in
FIG. 19 , after thestackable package 2 according to the present invention is formed, asecond package 3 is further stacked on thestackable package 2, so as to form a double-layered stacked package. It is understood that, at least one conductive element (for example, a second bump 40) is disposed between and electrically connects thesecond package 3 and the second redistribution layer (RDL) 39 of thestackable package 2. Preferably, athird package 4 can be further stacked on thesecond package 3, so as to form a third-layered stacked package. Preferably, thestackable package 2 is a processor, thesecond package 3 is a radio frequency (RF) device, and thethird package 4 is a memory. However, in other embodiments, as shown inFIG. 20 , thestackable package 2 can further comprise asecond chip 41 disposed side by side with thechip 32, and thesecond chip 41 is also a known-good die. The form of thesecond chip 41 has no limitation, and thesecond chip 41 can comprise a conductive via or not. - Therefore, the second redistribution layer (RDL) 39 is used to re-distribute the position of the contact point of the through via 324, to match the position of electrical contact points of other package. As a result, the stackable package 2 (
FIG. 9 ) made by the method according to the present invention is more flexible in application, for example, thestackable package 2 according to the present invention can be applied to the three following situation. First, themolding compound 34 of thestackable package 2 encapsulates a plurality ofchips 32, and after another package having the same size of thestackable package 2 is stacked thereon, a singulation process is conducted. Second, themolding compound 34 of thestackable package 2 encapsulates a plurality ofchips 32, and after a plurality of chips are stacked thereon, a singulation process is conducted. Third, a singulation process is conducted to thestackable package 2 first, and then, another chip is stacked thereon. Moreover, the through via 324 is formed in thechip 32, and electrically connected to the first redistribution layer (RDL) 35, and an extra element is unnecessary. As a result, the manufacturing cost and the size of the product are reduced. - While several embodiments of the present invention have been illustrated and described, various modifications and improvements can be made by those skilled in the art. The embodiments of the present invention are therefore described in an illustrative but not restrictive sense. It is intended that the present invention should not be limited to the particular forms as illustrated, and that all modifications which maintain the spirit and scope of the present invention are within the scope defined by the appended claims.
Claims (14)
1. A method for making a stackable package, comprising:
(a) providing a first carrier having a surface;
(b) disposing at least one chip on a surface of the first carrier, wherein the chip comprises a first surface, a second surface, an active circuit layer and at least one conductive via, the active circuit layer is disposed in the chip and exposed to the second surface, the conductive via is disposed in the chip and connected to the active circuit layer;
(c) forming a molding compound on the surface of the first carrier, so as to encapsulate the chip, wherein the molding compound comprises a surface attached to the surface of the first carrier;
(d) removing the first carrier, so as to expose the second surface of the chip and the surface of the molding compound;
(e) forming a first redistribution layer (RDL) and at least one first bump, wherein the first redistribution layer (RDL) is disposed on the second surface of the chip and the surface of the molding compound, and electrically connected to the conductive via by the active circuit layer, the first bump is disposed on the first redistribution layer (RDL), and electrically connected to the active circuit layer and the conductive via by the first redistribution layer (RDL);
(f) providing a second carrier;
(g) disposing a surface of the first redistribution layer (RDL) on the second carrier;
(h) removing part of the chip and part of the molding compound, so as to expose the conductive via to the first surface of the chip, and form a through via;
(i) forming a second redistribution layer (RDL) on the first surface of the chip, wherein the second redistribution layer (RDL) is electrically connected to the through via; and
(j) removing the second carrier.
2. The method as claimed in claim 1 , wherein in the step (b), the chip is adhered to the surface of the first carrier by an adhesive, and in the step (d), the method further comprises a step of removing the adhesive.
3. The method as claimed in claim 1 , wherein in the step (g), the surface of the first redistribution layer (RDL) is disposed on the second carrier by a glue layer, and the glue layer encapsulates the first bump, and in the step (j), the method further comprises a step of removing the glue layer.
4. The method as claimed in claim 3 , wherein in the step (g), the glue layer is formed by spin coating.
5. The method as claimed in claim 3 , wherein in step (j), the glue layer is softened by heated or under ultraviolet ray, so as to remove the glue layer.
6. The method as claimed in claim 1 , wherein in the step (h), part of the chip and part of the molding compound are removed by grinding or chemical-mechanical polishing (CMP).
7. The method as claimed in claim 1 , further comprising a step of stacking another package on the second redistribution layer (RDL) after the step (j).
8. A method for making a stackable package, comprising:
(a) providing a first carrier having a surface;
(b) disposing at least one chip on the surface of the first carrier, wherein the chip comprises a first surface, a second surface and an active circuit layer, the active circuit layer is disposed in the chip and exposed to the second surface;
(c) forming a molding compound on the surface of the first carrier, so as to encapsulate the chip, wherein the molding compound comprises a surface attached to the surface of the first carrier;
(d) removing the first carrier, so as to expose the second surface of the chip and the surface of the molding compound;
(e) forming a first redistribution layer (RDL) and at least one first bump, wherein the first redistribution layer (RDL) is disposed on the second surface of the chip and the surface of the molding compound, and electrically connected to the active circuit layer, the first bump is disposed on the first redistribution layer (RDL), and electrically connected to the active circuit layer by the first redistribution layer (RDL);
(f) providing a second carrier;
(g) disposing a surface of the first redistribution layer (RDL) on the second carrier;
(h) removing part of the chip and part of the molding compound;
(i) forming at least one through via in the chip, wherein the through via is connected to the active circuit layer and exposed to the first surface of the chip;
(j) forming a second redistribution layer (RDL) on the first surface of the chip, wherein the second redistribution layer (RDL) is electrically connected to the through via; and
(k) removing the second carrier.
9. The method as claimed in claim 8 , wherein in the step (b), the chip is adhered to the surface of the first carrier by an adhesive, and in the step (d), the method further comprises a step of removing the adhesive.
10. The method as claimed in claim 8 , wherein in the step (g), the surface of the first redistribution layer (RDL) is disposed on the second carrier by a glue layer, and the glue layer encapsulates the first bump, and in the step (k), the method further comprises a step of removing the glue layer.
11. The method as claimed in claim 10 , wherein in the step (g), the glue layer is formed by spin coating.
12. The method as claimed in claim 10 , wherein in step (k), the glue layer is softened by heated or under ultraviolet ray, so as to remove the glue layer.
13. The method as claimed in claim 8 , wherein in the step (h), part of the chip and part of the molding compound are removed by grinding or chemical-mechanical polishing (CMP).
14. The method as claimed in claim 8 , further comprising a step of stacking another package on the second redistribution layer (RDL) after the step (k).
Priority Applications (1)
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US13/560,722 US20130020703A1 (en) | 2009-12-31 | 2012-07-27 | Method for Making a Stackable Package |
Applications Claiming Priority (3)
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TW098146111A TWI401753B (en) | 2009-12-31 | 2009-12-31 | Method for making a stackable package |
TW98146111A | 2009-12-31 | ||
TW098146111 | 2009-12-31 |
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US13/560,722 Continuation US20130020703A1 (en) | 2009-12-31 | 2012-07-27 | Method for Making a Stackable Package |
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US20110159639A1 true US20110159639A1 (en) | 2011-06-30 |
US8252629B2 US8252629B2 (en) | 2012-08-28 |
Family
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US12/856,401 Active 2030-10-02 US8252629B2 (en) | 2009-12-31 | 2010-08-13 | Method for making a stackable package |
US13/560,722 Abandoned US20130020703A1 (en) | 2009-12-31 | 2012-07-27 | Method for Making a Stackable Package |
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TW (1) | TWI401753B (en) |
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Also Published As
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US20130020703A1 (en) | 2013-01-24 |
TWI401753B (en) | 2013-07-11 |
US8252629B2 (en) | 2012-08-28 |
TW201123319A (en) | 2011-07-01 |
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