CN109841576B - 半导体器件、包括其的半导体晶片及半导体封装 - Google Patents
半导体器件、包括其的半导体晶片及半导体封装 Download PDFInfo
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- CN109841576B CN109841576B CN201811432624.5A CN201811432624A CN109841576B CN 109841576 B CN109841576 B CN 109841576B CN 201811432624 A CN201811432624 A CN 201811432624A CN 109841576 B CN109841576 B CN 109841576B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 156
- 239000000758 substrate Substances 0.000 claims abstract description 172
- 230000001681 protective effect Effects 0.000 claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 238000000465 moulding Methods 0.000 claims description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 229910000679 solder Inorganic materials 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 229910052582 BN Inorganic materials 0.000 claims description 6
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 6
- 239000007769 metal material Substances 0.000 claims description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 2
- 238000004806 packaging method and process Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 127
- 235000012431 wafers Nutrition 0.000 description 49
- 238000000034 method Methods 0.000 description 27
- 239000010949 copper Substances 0.000 description 13
- 238000005530 etching Methods 0.000 description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 10
- 229910052782 aluminium Inorganic materials 0.000 description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 10
- 229910052802 copper Inorganic materials 0.000 description 10
- 238000000059 patterning Methods 0.000 description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 239000010937 tungsten Substances 0.000 description 6
- 238000009413 insulation Methods 0.000 description 5
- 230000001902 propagating effect Effects 0.000 description 5
- 239000012212 insulator Substances 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 230000001154 acute effect Effects 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 238000000347 anisotropic wet etching Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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Abstract
本发明提供一种半导体器件、包括其的半导体晶片和半导体封装。该半导体器件包括基板,基板包括第一区域和在俯视图中至少部分地围绕第一区域的第二区域。保护图案设置在基板的第二区域上,并在俯视图中至少部分地围绕基板的第一区域。保护沟槽交叠保护图案并沿着保护图案在俯视图中至少部分地围绕基板的第一区域。保护沟槽的宽度不同于保护图案的宽度。
Description
技术领域
本公开涉及半导体器件,更具体地,涉及具有保护沟槽的半导体器件、包括该半导体器件的半导体晶片以及半导体封装。
背景技术
半导体器件因其小尺寸、多功能性和相对低的制造成本而在电子产业中广泛使用。半导体器件通常包括用于存储数据的存储器、用于处理数据的处理器以及用于同时执行各种功能的混合器件。
随着电子产业的发展,半导体器件正变得更高度地集成并且能够以更快的速度运行。
发明内容
一种半导体器件包括基板,基板包括第一区域和在俯视图中至少部分地围绕第一区域的第二区域。保护图案设置在基板的第二区域上,并在俯视图中至少部分地围绕基板的第一区域。保护沟槽交叠保护图案并沿着保护图案在俯视图中至少部分地围绕基板的第一区域。保护沟槽的宽度不同于保护图案的宽度。
一种半导体封装包括封装基板。半导体器件设置在封装基板上。模制层设置在封装基板上并覆盖半导体器件。该半导体器件包括:基板,包括第一区域和在俯视图中围绕第一区域的第二区域;保护图案,设置在基板的第二区域上;绝缘结构,设置在基板的第一区域和第二区域两者上,绝缘结构至少部分地覆盖保护图案;保护沟槽,在设置于基板的第二区域上的绝缘结构的一部分内;以及连接端子,设置于在基板的第一区域上的绝缘结构的一部分上。保护沟槽设置在保护图案上。保护沟槽的宽度不同于保护图案的宽度。模制层填充保护沟槽。
一种半导体晶片包括基板,基板具有布置成沿第一方向的行和沿交叉第一方向的第二方向的列的多个器件区域。基板还包括限定所述多个器件区域的每个的划线区域。保护图案设置在基板的划线区域上。保护沟槽设置在基板的划线区域上并交叠保护图案。保护沟槽的宽度不同于保护图案的宽度。
附图说明
因为在结合附图考虑时,通过参照以下详细描述,本公开及其许多伴随方面将被更好地理解,所以将更容易获得对本公开及其许多伴随方面的更完整的理解,附图中:
图1是示出根据发明构思的示例性实施方式的半导体晶片的俯视图;
图2是示出图1中的部分A的放大图,示出了根据发明构思的示例性实施方式的半导体晶片和半导体器件;
图3是沿图2的线I-I'截取的剖视图,示出了根据发明构思的示例性实施方式的半导体晶片和半导体器件;
图4是沿图2的线I-I'截取的剖视图,示出了根据发明构思的示例性实施方式的半导体晶片和半导体器件;
图5是沿图2的线I-I'截取的剖视图,示出了根据发明构思的示例性实施方式的半导体晶片和半导体器件;
图6是图1中的部分A的放大图,示出了根据发明构思的示例性实施方式的半导体晶片和半导体器件;
图7是沿图6的线II-II'截取的剖视图,示出了根据发明构思的示例性实施方式的半导体晶片和半导体器件;
图8是图1中的部分A的放大图,示出了根据发明构思的示例性实施方式的半导体晶片和半导体器件;
图9是沿图8的线III-III'截取的剖视图,示出了根据发明构思的示例性实施方式的半导体晶片和半导体器件;
图10是示出根据发明构思的示例性实施方式的包括半导体器件的半导体封装的剖视图;
图11是示出根据发明构思的示例性实施方式的包括半导体器件的半导体封装的剖视图;以及
图12A至12D是沿图2的线I-I'截取的剖视图,示出了根据发明构思的示例性实施方式的制造半导体晶片和半导体器件的方法。
具体实施方式
在描述本公开的在附图中示出的示例性实施方式时,为了清楚起见,采用了特定术语。然而,本公开不旨在限于如此选择的特定术语,并将理解,每个特定元件包括以类似方式操作的所有技术等同物。
图1是示出根据发明构思的示例性实施方式的半导体晶片的俯视图。图2是图1中的部分A的放大图,示出了根据发明构思的示例性实施方式的半导体晶片和半导体器件。图3是沿图2的线I-I'截取的剖视图,示出了根据发明构思的示例性实施方式的半导体晶片和半导体器件。
参照图1至3,半导体晶片1可以包括基板200、绝缘层210、接触插塞220、布线230、保护图案240、绝缘结构260、保护沟槽270、连接端子280和绝缘图案290。基板200可以包括多个器件区域10和设置在器件区域10周围的划线区域20。基板200的器件区域10可以布置在彼此交叉的第一方向X和第二方向Y上。例如,器件区域10可以布置成行与列的阵列。每个器件区域10可以配置有一个或更多个电路、晶体管、布线和/或电容器。基板200的划线区域20可以限定基板200的器件区域10。基板200的划线区域20可以将基板200的器件区域10彼此分开。
绝缘层210和接触插塞220可以设置在基板200的器件区域10和划线区域20两者上。接触插塞220可以设置在绝缘层210中。布线230可以设置在绝缘层210上。下面将进一步详细讨论绝缘层210、接触插塞220和布线230。
保护图案240可以在设置于基板200的划线区域20上的绝缘层210上设置。保护图案240可以围绕基板200的每个器件区域10。保护图案240在俯视图中可以具有环形。保护图案240可以与器件区域10相邻。下面将进一步详细讨论保护图案240。
绝缘结构260可以设置在基板200的器件区域10和划线区域20两者上。绝缘结构260可以至少部分地覆盖布线230和保护图案240。下面将进一步详细讨论绝缘结构260。
保护沟槽270可以设置在可以设置于划线区域20上的绝缘结构260中。保护沟槽270可以设置在保护图案240上并且可以垂直地交叠保护图案240。保护沟槽270可以沿着保护图案240延伸。例如,保护图案240可以围绕基板200的器件区域10。保护图案240可以具有暴露于保护沟槽270的顶表面。保护沟槽270可以具有与保护图案240的宽度W2不同的宽度W1。例如,保护沟槽270的宽度W1可以小于保护图案240的宽度W2(W1<W2)。下面将进一步详细讨论保护沟槽270。
连接端子280和绝缘图案290可以设置在基板200的每个器件区域10上。连接端子280和绝缘图案290可以每个设置在绝缘结构260上。下面将进一步详细讨论连接端子280和绝缘图案290。
半导体晶片1可以包括多个半导体器件100。每个半导体器件100也可以被称为半导体管芯或半导体芯片。在基板200的划线区域20上,可以执行晶片划片工艺以将半导体晶片1切割成多个单独的半导体器件100。例如,晶片划片工艺可以使用刀片沿着半导体晶片1的刻划线5切割半导体晶片1。
通过晶片划片工艺分离的半导体器件100可以包括基板200、绝缘层210、接触插塞220、布线230、保护图案240、绝缘结构260、保护沟槽270、连接端子280和绝缘图案290。
半导体器件100的基板200可以是半导体晶片1的通过晶片划片工艺被切割的部分。基板200可以包括第一区域和第二区域203。基板200的第一区域可以对应于半导体晶片1的器件区域10。附图标记“10”不仅可以指半导体晶片1的器件区域10,而且也可以指基板200的第一区域。基板200的第二区域203可以是半导体晶片1的划线区域20的一部分。基板200的第二区域203可以围绕基板200的第一区域10。基板200可以是或者可以包括含硅、锗或硅锗的半导体基板,绝缘体上硅(SOI)基板或绝缘体上锗(GOI)基板。
绝缘层210可以设置在基板200的第一区域10和第二区域203上。绝缘层210可以包括硅氧化物层和/或硅氮化物层。接触插塞220可以设置在基板200的第一区域10和第二区域203两者上。接触插塞220可以设置在绝缘层210中并且可以穿透绝缘层210。设置在基板200的第一区域10上的接触插塞220可以电连接基板200的第一区域10中的布线,电连接在晶体管与布线之间,和/或电连接在电容器与布线之间。设置在基板200的第二区域203上的接触插塞220可以阻挡或防止在半导体器件100的边缘处发生的裂缝通过绝缘层210传播到基板200的器件区域10中。例如,当执行晶片划片工艺时(例如,当切割绝缘层210时),裂缝可以从刻划线5产生。接触插塞220可以包括铜、铝、钨、钛、钛氮化物、钽和/或钽氮化物。
布线230可以设置在绝缘层210上。布线230可以设置在基板200的第一区域10和第二区域203上。布线230可以电连接到接触插塞220。布线230可以包括金属性材料(例如铜、铝或钨)。
保护图案240可以设置在绝缘层210上。保护图案240可以设置在基板200的第二区域203上。保护图案240可以围绕基板200的第一区域10。当沿着刻划线5执行晶片划片工艺时,保护图案240可以阻挡或防止在刻划线5处产生的裂缝通过绝缘结构260传播到基板200的器件区域10中。保护图案240可以包括金属性材料(例如铜、铝或钨)。
绝缘结构260可以设置在基板200的第一区域10和第二区域203上。绝缘结构260可以至少部分地覆盖布线230和保护图案240。绝缘结构260可以包括顺序地堆叠在绝缘层210上的第一绝缘层261、第二绝缘层263和第三绝缘层266。第一绝缘层261可以是或者可以包括金属间电介质(IMD)层或具有低介电常数的低k电介质层。金属间电介质(IMD)层可以是或者可以包括例如硅氧化物层或碳掺杂的硅氧化物层。第二绝缘层263可以用作第一绝缘层261与第三绝缘层266之间的缓冲物。或者,第二绝缘层263可以被省略。第二绝缘层263可以包括例如SiN(硅氮化物)、SiON(硅氮氧化物)、SiC(硅碳化物)、SiCN(硅碳氮化物)或BN(硼氮化物)。第三绝缘层266可以是或者可以包括硅氧化物层或TEOS(原硅酸四乙酯)层。
保护沟槽270可以设置在基板200的第二区域203上。保护沟槽270可以设置在绝缘结构260中。保护沟槽270可以在沿保护图案240延伸的同时垂直地交叠保护图案240。因此,保护沟槽270可以围绕基板200的第一区域10。当在俯视图中观察时,保护沟槽270可以具有环形。保护沟槽270可以至少部分地暴露保护图案240的顶表面。保护沟槽270可以具有相对于基板200的顶表面倾斜的侧壁,例如,该侧壁以锐角或钝角与基板200的顶表面相交。保护沟槽270可以填充有空气。在一些实施方式中,保护沟槽270可以具有与保护图案240的宽度W2不同的宽度W1。例如,保护沟槽270的宽度W1可以小于保护图案240的宽度W2(W1<W2)。保护沟槽270可以具有保护图案240通过其暴露的底表面,并且保护沟槽270的宽度W1可以对应于该底表面的宽度。
根据发明构思的一些实施方式,因为保护沟槽270设置在保护图案240上,所以当执行晶片划片工艺时(例如,当切割第二绝缘层263和第三绝缘层266时),可以防止从刻划线5产生的裂缝通过第二绝缘层263和第三绝缘层266传播到基板200的器件区域10中。由于保护沟槽270的宽度W1小于保护图案240的宽度W2,所以可以防止裂缝通过保护图案240传播然后到达基板200的器件区域10。
连接端子280可以设置在绝缘结构260上。连接端子280可以局部地设置在基板200的第一区域10上。连接端子280可以包括导电焊盘、焊料球、焊料凸块或导电再分布层。连接端子280可以包括铝(Al)、镍(Ni)和/或铜(Cu)。
绝缘图案290可以设置在绝缘结构260上。绝缘图案290可以局部地设置在基板200的第一区域10上,暴露形成在基板200的第二区域203上的绝缘结构260的顶表面。例如,绝缘图案290可以至少部分地暴露形成在基板200的第二区域203上的第三绝缘层266的顶表面。绝缘图案290可以部分地暴露连接端子280。绝缘图案290可以包括例如硅氧化物层或硅氮化物层。
图4示出沿图2的线I-I'截取的剖视图,显示了根据发明构思的示例性实施方式的半导体晶片和半导体器件。与参照图1至3讨论的部件基本相同的部件在这里可以用相同的附图标记表示,并且到省略了对一个或更多个元件的说明的程度,可以假设这些元件至少类似于已描述的对应元件。
参照图4,残余图案310可以设置在保护沟槽270中。例如,当执行工艺以形成连接端子280时,形成在保护沟槽270中的导电层可以不被去除,而是可以保留,从而形成残余图案310。例如,当执行工艺以形成绝缘图案290时,形成在保护沟槽270中的绝缘层可以不被去除而是可以保留,从而形成残余图案310。因此,残余图案310可以包括与连接端子280或绝缘图案290的材料相同的材料。例如,残余图案310可以包括导电材料(例如铝、镍或铜)或绝缘材料(例如硅氧化物层或硅氮化物层)。
图5是沿图2的线I-I'截取的剖视图,示出了根据发明构思的示例性实施方式的半导体晶片和半导体器件。与参照图1至3讨论的部件基本相同的部件在这里可以由相同的附图标记表示,并且到省略了对一个或更多个元件的说明的程度,可以假设这些元件至少类似于已描述的对应元件。
参照图5,第一残余图案320和第二残余图案330可以设置在保护沟槽270中。第一残余图案320可以设置在保护沟槽270的底表面上,第二残余图案330可以设置在第一残余图案320上。第一残余图案320可以包括与连接端子280的材料相同的材料。第二残余图案330可以包括与绝缘图案290的材料相同的材料。第一残余图案320可以包括铝(Al)、镍(Ni)和/或铜(Cu)。第二残余图案330可以包括例如硅氧化物层或硅氮化物层。
图6是图1中的部分A的放大图,示出了根据发明构思的示例性实施方式的半导体晶片和半导体器件。图7是沿图6的线II-II'截取的剖视图,示出了根据发明构思的示例性实施方式的半导体晶片和半导体器件。与参照图1至3讨论的部件基本相同的部件在这里可以由相同的附图标记表示,并且到省略了对一个或更多个元件的说明的程度,可以假设这些元件至少类似于已描述的对应元件。
参照图6和7,保护图案240可以设置在基板200的划线区域20上。保护图案240可以沿着基板200的划线区域20延伸,围绕基板200的器件区域10。保护图案240可以设置在基板200的在相邻的器件区域10之间的划线区域20的中心部分上。
保护沟槽270可以设置在基板200的划线区域20上。保护沟槽270可以设置在保护图案240上,同时垂直地交叠保护图案240。保护沟槽270可以沿保护图案240延伸。例如,保护沟槽270可以沿着基板200的划线区域20延伸。因此,保护沟槽270可以围绕基板200的器件区域10。保护沟槽270的宽度W1可以小于保护图案240的宽度W2(W1<W2)。
例如,半导体晶片1可以沿着刻划线5被切割,刻划线5沿着保护沟槽270延伸。保护沟槽270的宽度W1可以大于刻划线5的宽度,使得保护沟槽270可以防止从刻划线5产生的裂缝的传播。例如,保护沟槽270和保护图案240可以在执行晶片划片工艺时被切割。
通过晶片划片工艺分离的半导体器件100可以包括基板200、绝缘层210、接触插塞220、布线230、保护图案240、绝缘结构260、保护沟槽270、连接端子280和绝缘图案290。
保护图案240可以设置在基板200的第二区域203上,围绕基板200的第一区域10。保护图案240可以设置在基板200的第二区域203的边缘上。在这样的构造中,保护图案240可以暴露于半导体器件100的侧表面。
保护沟槽270可以设置在绝缘结构260中。保护沟槽270可以设置在基板200的第二区域203上。保护沟槽270可以围绕基板200的第一区域10。保护沟槽270可以设置在保护图案240上,同时垂直地交叠保护图案240。保护沟槽270可以至少部分地暴露保护图案240的顶表面。保护沟槽270可以设置在基板200的第二区域203的边缘上。在这样的构造中,保护沟槽270的侧壁可以形成半导体器件100的侧表面的一部分。半导体器件100的侧表面的该部分可以相对于基板200的顶表面倾斜。
例如,晶片划片工艺之前的保护图案240的宽度W2可以被减小到通过晶片划片工艺分离的半导体器件100中包括的保护图案240的宽度W4。同样地,晶片划片工艺之前的保护沟槽270的宽度W1可以被减小到通过晶片划片工艺分离的半导体器件100中包括的保护沟槽270的宽度W3(W3<W1)。保护沟槽270的宽度W3可以不同于保护图案240的宽度W4。例如,保护沟槽270的宽度W3可以小于保护图案240的宽度W4(W3<W4)。
图8是图1中的部分A的放大图,示出了根据发明构思的示例性实施方式的半导体晶片和半导体器件。图9是沿图8的线III-III'截取的剖视图,示出了根据发明构思的示例性实施方式的半导体晶片和半导体器件。与参照图6和7讨论的部件基本相同的部件在这里可以由相同的附图标记表示,并且到省略了对一个或更多个元件的说明的程度,可以假设这些元件至少类似于已描述的对应元件。
参照图8和9,半导体晶片1可以包括设置在基板200的划线区域20上的第二保护图案340。第二保护图案340可以围绕基板200的每个器件区域10。第二保护图案340可以与保护图案240间隔开。例如,第二保护图案340可以比保护图案240更靠近基板200的器件区域10。
半导体器件100可以以第二保护图案340设置在基板200的第二区域203上这样的方式被构造。第二保护图案340可以围绕基板200的第一区域10。第二保护图案340可以设置在绝缘层210上,并且可以至少部分地被绝缘结构260的第一绝缘层261覆盖。第二保护图案340可以与保护图案240间隔开。第二保护图案340可以比保护图案240更靠近基板200的器件区域10。第二保护图案340可以包括金属性材料(例如铜、铝或钨)。
图10是示出根据发明构思的示例性实施方式的包括半导体器件的半导体封装的剖视图。与参照图2至9讨论的部件基本相同的部件在这里可以由相同的附图标记表示,并且到省略了对一个或更多个元件的说明的程度,可以假设这些元件至少类似于已描述的对应元件。
参照图10,半导体封装1000可以包括以上讨论的半导体器件100。除了半导体器件100之外,半导体封装1000还可以包括封装基板1100、接合线1200和模制层1300。
半导体器件100可以安装在封装基板1100上。半导体器件100可以通过粘合层刚性地接合到封装基板1100。半导体器件100和封装基板1100可以通过接合线1200彼此电连接。每个接合线1200可以连接到以上讨论的半导体器件100的连接端子。模制层1300可以设置在封装基板1100上。模制层1300可以至少部分地覆盖半导体器件100和接合线1200。模制层1300可以设置在以上讨论的半导体器件100的保护沟槽270中。例如,模制层1300可以至少部分地填充保护沟槽270。保护沟槽270可以具有与半导体器件100的保护图案240的宽度不同的宽度。例如,保护沟槽270的宽度可以小于半导体器件100的保护图案240的宽度。与图6和7所示的相同或相似,保护沟槽270和保护图案240可以设置于在半导体器件100中包括的基板200的第二区域203的边缘上。例如,保护沟槽270和保护图案240可以设置在半导体器件100的边缘上。
图11示出显示了根据发明构思的示例性实施方式的包括半导体器件的半导体封装的剖视图。与参照图2至9讨论的部件基本相同的部件在这里可以由相同的附图标记表示,并且到省略了对一个或更多个元件的说明的程度,可以假设这些元件至少类似于已描述的对应元件。
参照图11,半导体封装2000可以包括以上讨论的半导体器件100。除了半导体器件100之外,半导体封装2000还可以包括封装基板2100、焊料球2200和模制层2300。半导体器件100可以安装在封装基板2100上。半导体器件100可以通过焊料球2200刚性地接合到封装基板2100。每个焊料球2200可以设置在半导体器件100的连接端子280上。焊料球2200可以设置在连接端子280与封装基板2100之间。半导体器件100和封装基板2100可以通过焊料球2200彼此电连接。模制层2300可以设置在封装基板2100上。模制层2300可以至少部分地覆盖半导体器件100,并且可以至少部分地填充半导体器件100与封装基板2100之间的空间。模制层2300可以设置在以上讨论的半导体器件100的保护沟槽270中。例如,模制层2300可以至少部分地填充保护沟槽270。保护沟槽270可以具有与半导体器件100的保护图案240的宽度不同的宽度。例如,保护沟槽270的宽度可以小于半导体器件100的保护图案240的宽度。与图6和7所示的相同或相似,保护沟槽270和保护图案240可以设置于在半导体器件100中包括的基板200的第二区域203的边缘上。例如,保护沟槽270和保护图案240可以设置在半导体器件100的边缘上。
图12A至12D是沿图2的线I-I'截取的剖视图,示出了根据发明构思的示例性实施方式的制造半导体晶片和半导体器件的方法。
参照图12A,绝缘层210可以在基板200上形成。基板200可以包括布置在彼此交叉的第一方向X和第二方向Y上的器件区域10、以及限定器件区域10的划线区域20。例如,器件区域10可以布置成行与列的阵列。基板200可以是或者可以包括半导体基板。基板200可以是或者可以包括含硅、锗或硅锗的半导体基板,绝缘体上硅(SOI)基板或绝缘体上锗(GOI)基板。绝缘层210可以形成在基板200的器件区域10和划线区域20上。绝缘层210可以包括例如硅氧化物层或硅氮化物层。
接触插塞220可以在绝缘层210中形成。接触插塞220可以通过蚀刻绝缘层210以形成接触通路孔并用导电材料填充该接触通路孔而形成。接触插塞220可以形成在基板200的器件区域10和划线区域20上。接触插塞220可以包括例如铜、铝、钨、钛、钛氮化物、钽和钽氮化物中的一种或更多种。
布线230和保护图案240可以在绝缘层210上形成。例如,布线230和保护图案240可以通过在绝缘层210上形成金属层并图案化该金属层而形成。或者,布线230和保护图案240可以通过镶嵌工艺形成。布线230可以形成在基板200的器件区域10和划线区域20上。
保护图案240可以形成在基板200的划线区域20上。例如,保护图案240可以形成为围绕基板200的每个器件区域10。保护图案240在俯视图中可以具有环形。例如,保护图案240可以形成为沿着基板200的划线区域20延伸。布线230和保护图案240可以包括例如金属性材料(例如铜、铝或钨)。
绝缘结构260可以在绝缘层210上形成。绝缘结构260可以包括顺序地堆叠在绝缘层210上的第一绝缘层261、第二绝缘层263和第三绝缘层266。第一绝缘层261可以至少部分地覆盖布线230和保护图案240。第一绝缘层261可以是或者可以包括金属间电介质(IMD)层或具有低介质常数的低k电介质层。金属间电介质(IMD)层可以是或者可以包括例如硅氧化物层或碳掺杂的硅氧化物层。第二绝缘层263可以用作第一绝缘层261与第三绝缘层266之间的缓冲物。第二绝缘层263可以被省略。第二绝缘层263可以包括例如SiN、SiON、SiCN或BN(硼氮化物)。第三绝缘层266可以是或者可以包括硅氧化物层或TEOS(原硅酸四乙酯)层。
保护沟槽270可以在设置于基板200的划线区域20上的绝缘结构260中形成。保护沟槽270可以通过在绝缘结构260上形成第一蚀刻掩模图案401并执行蚀刻工艺以蚀刻未被第一蚀刻掩模图案401覆盖的绝缘结构260而形成。该蚀刻工艺可以使用干蚀刻或各向异性湿蚀刻来执行。第一蚀刻掩模图案401可以包括例如光敏聚酰亚胺。在形成保护沟槽270之后,第一蚀刻掩模图案401可以被去除。
保护沟槽270可以形成在保护图案240上,同时垂直地交叠保护图案240。例如,保护沟槽270可以形成为围绕基板200的每个器件区域10。保护沟槽270在俯视图中可以具有环形。例如,保护沟槽270可以形成为沿着基板200的划线区域20延伸。保护沟槽270可以至少部分地暴露保护图案240的顶表面。例如,保护图案240可以在执行蚀刻工艺以形成保护沟槽270时用作蚀刻停止层。
保护沟槽270可以形成为具有比保护图案240的宽度W2小的宽度W1(W1<W2)。第三绝缘层266可以相对于其它层形成得相对较厚,使得保护沟槽270可以具有相对高的深宽比。保护沟槽270可以具有上宽度和小于上宽度的下宽度。保护沟槽270可以具有通过其至少部分地暴露保护图案240的底表面,并且保护沟槽270的宽度W1可以对应于该底表面的宽度。保护沟槽270可以具有相对于基板200的顶表面倾斜的侧壁。
参照图12B,导电层403可以在绝缘结构260上形成。例如,导电层403可以形成为填充保护沟槽270并至少部分地覆盖形成在基板200的器件区域10和划线区域20上的第三绝缘层266的顶表面。导电层403可以包括铝(Al)、镍(Ni)和/或铜(Cu)。
参照图12C,连接端子280可以在基板200的每个器件区域10上形成。连接端子280可以通过图案化导电层403而形成。连接端子280可以局部地形成在基板200的第一区域10上。图案化工艺可以使用湿蚀刻或干蚀刻来执行。图案化工艺可以去除形成在基板200的划线区域20上的导电层403以及形成在基板200的器件区域10上的导电层403的一部分。例如,图案化工艺可以至少部分地暴露形成在基板200的划线区域20上的第三绝缘层266的顶表面、保护沟槽270的侧壁、暴露于保护沟槽270的保护图案240的顶表面、以及形成在基板200的器件区域10上的第三绝缘层266的顶表面的一部分。
当执行图案化工艺时,导电层403可以不被完全从保护沟槽270去除。因此,导电层403的一部分可以留在保护沟槽270中。导电层403的剩余部分可以对应于图4的残余图案310或图5的第一残余图案320。
参照图12D,第四绝缘层405可以在基板200的器件区域10和划线区域20上形成。第二蚀刻掩模图案407可以在基板200的每个器件区域10上形成。第四绝缘层405可以共形地覆盖形成在基板200的器件区域10和划线区域20上的第三绝缘层266的顶表面的至少一部分、保护沟槽270的侧壁、暴露于保护沟槽270的保护图案240的顶表面、以及连接端子280的顶表面和侧表面。第二蚀刻掩模图案407可以至少部分地暴露形成在基板200的划线区域20上的第三绝缘层266的顶表面、保护沟槽270的侧壁、保护图案240的顶表面、以及至少部分地覆盖连接端子280的顶表面的第四绝缘层405。第四绝缘层405可以包括例如硅氧化物层或硅氮化物层。第二蚀刻掩模图案407可以包括例如光敏聚酰亚胺。
返回参照图3,绝缘图案290可以通过对第四绝缘层405的未被第二蚀刻掩模图案407覆盖的部分执行蚀刻工艺而形成。绝缘图案290可以在基板200的第一区域10上局部地形成。绝缘图案290可以至少部分地覆盖形成在基板200的器件区域10上的第三绝缘层266的顶表面和连接端子280的侧表面。绝缘图案290可以不覆盖形成在基板200的划线区域20上的第三绝缘层266的顶表面、保护沟槽270的侧壁以及暴露于保护沟槽270的保护图案240的顶表面。
例如,当执行蚀刻工艺以形成绝缘图案290时,第四绝缘层405可以不被完全从保护沟槽270去除。因此,第四绝缘层405的一部分可以留在保护沟槽270中。第四绝缘层405的剩余部分可以对应于图4的残余图案310或图5的第二残余图案330。
可以对基板200的划线区域20执行晶片划片工艺,因而绝缘结构260、绝缘层210和基板200可以沿着刻划线5被顺序地切割。因此,多个半导体器件100可以彼此分离。
根据发明构思的一些实施方式,基板的划线区域上可以设置交叠保护图案的保护沟槽。即使当在执行晶片划片工艺以切割其中形成保护沟槽的绝缘层时从基板的划线区域上的刻划线产生裂缝时,保护沟槽也可以阻挡或防止裂缝通过绝缘层传播到基板的器件区域中。
虽然已经结合发明构思的在附图中示出的实施方式描述了本发明,但是本领域技术人员将理解,可以进行各种改变和修改而不背离发明构思的技术精神和实质特征。对本领域技术人员将明显的是,可以对发明构思进行各种替换、修改和改变而不背离发明构思的范围和精神。
本申请要求享有2017年11月29日在韩国知识产权局提交的韩国专利申请第10-2017-0161956号的优先权,其全部内容通过引用合并于此。
Claims (23)
1.一种半导体器件,包括:
基板,包括第一区域和在俯视图中至少部分地围绕所述第一区域的第二区域;
保护图案,设置在所述基板的所述第二区域上并且在俯视图中至少部分地围绕所述基板的所述第一区域;以及
保护沟槽,交叠所述保护图案并且沿着所述保护图案在俯视图中至少部分地围绕所述基板的所述第一区域,
其中所述保护沟槽的宽度不同于所述保护图案的宽度,以及
其中所述保护沟槽填充有空气。
2.根据权利要求1所述的半导体器件,其中所述保护沟槽的所述宽度小于所述保护图案的所述宽度。
3.根据权利要求1所述的半导体器件,其中所述保护沟槽暴露所述保护图案的顶表面。
4.根据权利要求1所述的半导体器件,还包括覆盖所述保护图案的绝缘结构,
其中所述保护沟槽设置在所述绝缘结构内。
5.根据权利要求4所述的半导体器件,其中所述绝缘结构包括顺序地堆叠在所述基板上的第一绝缘层、第二绝缘层和第三绝缘层,
其中所述第一绝缘层包括金属间电介质层或具有低介电常数的低k电介质层,
其中所述第二绝缘层包括硅氮化物、硅氮氧化物、硅碳化物、硅碳氮化物或硼氮化物,以及
其中所述第三绝缘层包括硅氧化物层或原硅酸四乙酯层。
6.根据权利要求1所述的半导体器件,还包括第二保护图案,该第二保护图案设置在所述基板的所述第二区域上并且围绕所述基板的所述第一区域,
其中所述第二保护图案离所述基板的所述第一区域比所述保护图案离所述基板的所述第一区域更近。
7.根据权利要求1所述的半导体器件,其中,当在俯视图中看时,所述保护图案和所述保护沟槽设置在所述基板的所述第二区域的边缘上。
8.根据权利要求1所述的半导体器件,其中所述保护沟槽的侧壁相对于所述基板倾斜。
9.根据权利要求1所述的半导体器件,还包括:
绝缘结构,设置在所述基板的所述第一区域和所述第二区域上并且覆盖所述保护图案;
连接端子,设置在所述基板的所述第一区域上的所述绝缘结构上;以及
绝缘图案,设置在所述基板的所述第一区域上的所述绝缘结构上,所述绝缘图案暴露所述连接端子的一部分。
10.根据权利要求1所述的半导体器件,其中所述保护图案包括金属性材料。
11.根据权利要求1所述的半导体器件,还包括在所述保护沟槽内的残余图案,
其中所述残余图案包括金属性材料和/或绝缘材料。
12.一种半导体封装,包括:
封装基板;
半导体器件,设置在所述封装基板上;以及
模制层,设置在所述封装基板上并且覆盖所述半导体器件,
其中所述半导体器件包括:
基板,包括第一区域和在俯视图中围绕所述第一区域的第二区域;
保护图案,设置在所述基板的所述第二区域上;
绝缘结构,设置在所述基板的所述第一区域和所述第二区域两者上,所述绝缘结构至少部分地覆盖所述保护图案;
保护沟槽,在设置于所述基板的所述第二区域上的所述绝缘结构的一部分内;以及
连接端子,设置于在所述基板的所述第一区域上的所述绝缘结构的一部分上,
其中所述保护沟槽设置在所述保护图案上,
其中所述保护沟槽的宽度不同于所述保护图案的宽度,以及
其中所述模制层填充所述保护沟槽。
13.根据权利要求12所述的半导体封装,其中所述保护沟槽的所述宽度小于所述保护图案的所述宽度。
14.根据权利要求12所述的半导体封装,其中所述保护沟槽暴露所述保护图案的顶表面。
15.根据权利要求12所述的半导体封装,其中所述绝缘结构包括顺序地堆叠在所述基板上的第一绝缘层、第二绝缘层和第三绝缘层,
其中所述第一绝缘层包括金属间电介质层或具有低介电常数的低k电介质层,
其中所述第二绝缘层包括硅氮化物、硅氮氧化物、硅碳化物、硅碳氮化物或硼氮化物,以及
其中所述第三绝缘层包括硅氧化物层或原硅酸四乙酯层。
16.根据权利要求12所述的半导体封装,其中所述保护沟槽的侧壁相对于所述半导体器件的所述基板倾斜。
17.根据权利要求12所述的半导体封装,还包括设置在所述连接端子与所述封装基板之间的焊料球,
其中所述焊料球电连接所述连接端子与所述封装基板。
18.根据权利要求12所述的半导体封装,还包括设置在所述连接端子与所述封装基板之间的接合线,
其中所述接合线电连接所述连接端子和所述封装基板。
19.根据权利要求12所述的半导体封装,其中所述保护图案和所述保护沟槽设置在所述基板的所述第二区域的边缘上。
20.一种半导体晶片,包括:
基板,包括多个器件区域,所述多个器件区域布置成沿第一方向的行和沿交叉所述第一方向的第二方向的列,并且所述基板还包括限定所述多个器件区域中的每个的划线区域;
保护图案,设置在所述基板的所述划线区域上;以及
保护沟槽,设置在所述基板的所述划线区域上并且交叠所述保护图案,
其中所述保护沟槽的宽度不同于所述保护图案的宽度,以及
其中所述保护沟槽填充有空气。
21.根据权利要求20所述的半导体晶片,其中所述保护沟槽的所述宽度小于所述保护图案的所述宽度。
22.根据权利要求20所述的半导体晶片,其中所述保护沟槽暴露所述保护图案的顶表面。
23.根据权利要求20所述的半导体晶片,其中所述保护图案和所述保护沟槽沿着所述基板的所述划线区域延伸。
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