CN109962064B - 半导体装置及其制造方法、和包括其的半导体封装件 - Google Patents

半导体装置及其制造方法、和包括其的半导体封装件 Download PDF

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CN109962064B
CN109962064B CN201811267757.1A CN201811267757A CN109962064B CN 109962064 B CN109962064 B CN 109962064B CN 201811267757 A CN201811267757 A CN 201811267757A CN 109962064 B CN109962064 B CN 109962064B
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layer
conductive
semiconductor device
conductive pad
substrate
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CN109962064A (zh
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千镇豪
孙成旻
全炯俊
文光辰
安振镐
李镐珍
藤崎纯史
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

一种半导体装置及其制造方法，所述半导体装置包括：延伸穿过衬底的通孔电极结构；通孔电极结构上的再分布层；以及导电焊盘，该导电焊盘包括延伸穿过再分布层的贯穿部分以及贯穿部分上的突出部分，所述突出部分从再分布层的上表面突出，其中突出部分的上表面的中间区平坦，并且不比突出部分的上表面的边缘区更靠近衬底。

Description

半导体装置及其制造方法、和包括其的半导体封装件
相关申请的交叉引用
于2017年11月2日在韩国知识产权局提交的标题为“半导体装置及其制造方法、和包括其的半导体封装件”的韩国专利申请No.10-2017-0145253以引用方式全文并入本文中。
技术领域
实施例涉及一种半导体装置、一种包括该半导体装置的半导体封装件和一种制造该半导体装置的方法。
背景技术
导电焊盘可形成在一个半导体芯片上的再分布层上，并且可通过导电凸块电连接至另一半导体芯片，从而可制造半导体封装件。
发明内容
可通过提供一种半导体装置实现实施例，该半导体装置包括：延伸穿过衬底的通孔电极结构；通孔电极结构上的再分布层；以及导电焊盘，该导电焊盘包括延伸穿过再分布层的贯穿部分以及贯穿部分上的突出部分，所述突出部分从再分布层的上表面突出，其中突出部分的上表面的中间区平坦，并且不比突出部分的上表面的边缘区更靠近衬底。
可通过提供一种半导体装置实现实施例，该半导体装置包括：延伸穿过衬底的通孔电极结构；通孔电极结构上的再分布层；以及导电焊盘，导电焊盘中的每一个包括延伸穿过再分布层中的一个的贯穿部分以及贯穿部分上的突出部分，突出部分从再分布层的所述一个的上表面突出，其中，再分布层中的至少两个具有彼此不同的厚度，并且其中，再分布层的上表面相对于衬底具有相同高度。
可通过提供一种半导体装置实现实施例，该半导体装置包括：第一半导体芯片，该第一半导体芯片包括延伸穿过衬底的通孔电极结构、通孔电极结构上的再分布层和第一导电焊盘，该第一导电焊盘包括延伸穿过再分布层的贯穿部分和贯穿部分上的突出部分，该突出部分从再分布层的上表面突出，并且突出部分的上表面的中间区平坦并且不比突出部分的上表面的边缘区更靠近衬底；以及第一半导体芯片的一侧上的第二半导体芯片，第二半导体芯片通过第一导电焊盘电连接至第一半导体芯片。
可通过提供一种制造半导体装置的方法实现实施例，该方法包括以下步骤：形成穿过衬底的通孔电极结构；在通孔电极结构上形成再分布层，以使得再分布层包括第一开口；以及形成保护层以覆盖再分布层，以使得保护层包括连接至第一开口的第二开口；以及形成导电焊盘以填充第一开口和第二开口的至少一部分，其中，导电焊盘的上表面的中间区平坦并且不比导电焊盘的上表面的边缘区更靠近衬底。
可通过提供一种制造半导体装置的方法实现实施例，该方法包括以下步骤：形成穿过衬底的通孔电极结构；在通孔电极结构上形成再分布层，以使得再分布层中的每一个包括第一开口；形成保护层以覆盖再分布层，以使得保护层包括连接至第一开口的第二开口；以及形成导电焊盘，所述导电焊盘中的每一个填充第一开口和第二开口的至少一部分，因此导电焊盘中的每一个的上表面的中间区平坦，其中再分布层中的至少两个具有彼此不同的厚度，并且其中导电焊盘的上表面相对于衬底具有相同高度。
附图说明
通过参照附图详细描述示例性实施例，特征将对于本领域技术人员变得清楚，在附图中：
图1A示出了根据示例实施例的半导体装置的剖视图，图1B示出了图1A的区X的放大剖视图；
图2示出了包括多个再分布层和多个第一导电焊盘的第一半导体芯片的剖视图；
图3至图22示出了根据示例实施例的制造半导体装置的方法中的各阶段的平面图和剖视图；
图23示出了根据比较例的半导体装置的剖视图；
图24至图28示出了制造图23的半导体装置的方法中的各阶段的剖视图；
图29A、图29B、图29C和图29D示出了根据示例实施例的半导体装置的第一半导体芯片中的第一导电焊盘的形状的剖视图；
图30示出了根据示例实施例的半导体封装件的剖视图；
图31示出了根据示例实施例的半导体封装件的剖视图；
图32示出了制造图31的半导体封装件的方法中的阶段的剖视图；以及
图33示出了根据示例实施例的半导体封装件的剖视图。
具体实施方式
图1A示出了根据示例实施例的半导体装置的剖视图，并且图1B示出了图1A的区X的放大剖视图。
参照图1A和图1B，半导体装置可包括按次序堆叠并且彼此接合的第一半导体芯片和第二半导体芯片500，它们可通过第一导电焊盘480、第二导电焊盘520和第二导电凸块530彼此电连接。在实施中，第一半导体芯片可包括逻辑芯片，并且第二半导体芯片500可包括存储器芯片，例如，DRAM芯片。
第一半导体芯片可包括衬底100、延伸穿过衬底100的第一通孔电极结构215、第一通孔电极结构215上的第一再分布层、以及第一导电焊盘480，所述第一导电焊盘480包括延伸穿过第一再分布层的贯穿部分480a和位于贯穿部分480a上并从第一再分布层的上表面(例如，远离衬底100的表面)突出的突出部分480b。
第一半导体芯片还可包括第一绝缘夹层160和第二绝缘夹层220、电路元件、接触插塞170、布线240、过孔260、钝化层310、第一保护层400和第一导电凸块280。
衬底100可包括硅、锗、硅-锗、或例如GaP、GaAs、GaSb等的III-V化合物。在实施中，例如，衬底100可为绝缘体上硅(SOI)衬底或绝缘体上锗(GOI)衬底。
衬底100可具有第一表面101和与其相对的第二表面102，并且可包括第一区I和第二区II。第一区I和第二区II可分别用作芯片和划线区。下文中，可将衬底100的第一区I和第二区II以及从衬底100的第一区I和第二区II向上或向下延伸的空间一起分别限定为第一区I和第二区II。
在第一区I中，例如晶体管的电路元件可形成在衬底100的第一表面101上。晶体管可包括具有按次序堆叠的栅极绝缘图案120和栅电极130的栅极结构140以及在衬底100的邻近于栅极结构140的一部分处且邻近于衬底100的第一表面101的杂质区110。栅极间隔件150还可形成在栅极结构140的侧壁上。
栅极绝缘图案120可包括例如氧化硅或金属氧化物的氧化物，栅电极130可包括例如掺杂的多晶硅、金属、金属氮化物和/或金属硅化物等，并且栅极间隔件150可包括例如氮化硅的氮化物。
多个晶体管可形成在第一区I中。在实施中，电路元件可包括例如二极管、电阻器、电感器、电容器等。
第一绝缘夹层160和第二绝缘夹层220可按次序堆叠在衬底100的第一表面101下方(例如，在远离第二半导体芯片500的方向上)。
第一绝缘夹层160可覆盖电路元件，并且可包含或包围延伸穿过第一绝缘夹层160以接触杂质区110的接触插塞170。在实施中，接触插塞170可接触栅极结构140。第一绝缘夹层160可包括例如氧化硅的氧化物，并且接触插塞170可包括例如金属、金属氮化物、金属硅化物、掺杂的多晶硅等。
第二绝缘夹层220可包含或包围位于第二绝缘夹层220中的布线240和过孔260。例如，第二绝缘夹层220可包括掺有氟或碳的氧化硅、多孔氧化硅、旋涂有机聚合物或者例如氢硅倍半环氧乙烷(HSSQ)、甲基倍半硅氧烷(MSSQ)等的无机聚合物。
一条或多条布线240和连接所述多条布线240的过孔260可形成在第二绝缘夹层220中。在实施中，如图所示，布线240包括按次序堆叠的第一布线至第三布线232、234和236，并且过孔260包括按次序堆叠的第一过孔252和第二过孔254。在实施中，可形成处于多个水平高度的多条布线、以及多个过孔。
布线240和过孔260中的每一个可包括导电图案和覆盖导电图案的表面的势垒图案。导电图案可包括例如铜、铝、钨、钛、钽等的金属，并且势垒图案可包括例如氮化钛、氮化钽、氮化钨、氮化铜、氮化铝等的金属氮化物。
第一导电凸块280可接触第三布线236，并且可包括例如银、铜等的金属，或者例如焊料的金属合金。
第一通孔电极结构215可延伸穿过第一绝缘夹层160和衬底100，并且第一通孔电极结构215的一部分可从衬底100的第二表面102暴露出来。在实施中，第一通孔电极结构215可包括通孔电极和覆盖通孔电极的侧壁的绝缘图案185。通孔电极可包括第一导电层200和覆盖第一导电层200的侧壁的第一势垒图案195。
第一导电层200可包括例如铜、铝、钨等的金属，并且第一势垒图案195可包括例如氮化钛、氮化钽、氮化钨、氮化铜、氮化铝等的金属氮化物，并且绝缘图案185可包括例如氧化硅的氧化物或者例如氮化硅的氮化物。
钝化层310可覆盖第一通孔电极结构215的侧壁的在衬底100的第二表面102处暴露的一部分。在实施中，钝化层310可包括在衬底100的第二表面102上按次序堆叠的第一氧化物层、氮化物层和第二氧化物层。
对准键315可形成在第二区II中的钝化层310的一部分上。
第一再分布层可形成在钝化层310上，以接触第一通孔电极结构215。参照图11或图9A、图9B和图9C，第一再分布层可具有在一个方向上延伸的杆形或者其端部在平面图中具有圆形的杆形，并且可包括暴露钝化层310的具有圆形或矩形的第三开口390(参照图10)。
在实施中，第一再分布层可包括按次序堆叠的第二势垒图案345和第二导电层380。第二势垒图案345可包括例如氮化钛、氮化钽、氮化钨、氮化铜、氮化铝等的金属氮化物，第二导电层380可包括例如铜、铝、钨等的金属。
第一保护层400可形成在钝化层310上，并且可覆盖第一再分布层和对准键315。在实施中，第一保护层400可包括第四开口410(参照图12)，第四开口410与将连接至第四开口410的第三开口390重叠，并且在平面图中，第四开口410的面积等于或大于第三开口390的面积。在实施中，第四开口410可具有不垂直于衬底100的上表面的侧壁(例如，侧壁可相对于衬底100的上表面倾斜)。例如，第四开口410的宽度可从其底部朝着顶部(例如，在远离衬底100的方向上)逐渐增大。
在实施中，第一保护层400可包括光敏有机材料或由其形成，并且可包括热固性有机聚合物和光敏材料。例如，热固性有机聚合物可包括聚酰亚胺、酚醛清漆、聚苯并恶唑(PBO)、苯并环丁烯、硅聚合物、环氧聚合物、丙烯酸聚合物等。
第一导电焊盘480可填充第一再分布层中的第三开口390和第一保护层400中的第四开口410的一部分。因此，第一导电焊盘480可包括延伸穿过第一再分布层的贯穿部分480a以及突出部分480b，所述突出部分480b可与贯穿部分480a一体地形成并且从第一再分布层的上表面突出。
在实施中，贯穿部分480a的侧壁可基本垂直于衬底100的上表面，并且突出部分480b的侧壁可相对于衬底100的上表面倾斜。在实施中，突出部分480b的边缘上表面可具有与突出部分480b的侧壁相对的斜坡(例如，当突出部分480b的侧壁向外倾斜时，突出部分480b的上表面的外边缘可在第四开口410中向内倾斜)。
第一导电焊盘480可包括第三导电层460、覆盖第三导电层460的上表面的至少一部分的第一封盖层470和覆盖第三导电层460的底部和侧壁的第三势垒图案425。
在实施中，第三导电层460和第一封盖层470中的每一个的上表面可为平坦的，因此第一导电焊盘480的至少中间上表面可为平坦的。在实施中，第一导电焊盘480的中间上表面可不低于其边缘上表面(例如，衬底100与第一导电焊盘的上表面的中间区相距的距离可等于或大于衬底100与突出部分480b的上表面的外边缘相距的距离)。
在实施中，第一导电焊盘480的上表面可低于覆盖第一导电焊盘480的侧壁的第一保护层400的上表面(例如，第一导电焊盘480的上表面比覆盖第一导电焊盘480的侧壁的第一保护层400的上表面更靠近衬底100)。因此，第一导电焊盘480的第三导电层460的暴露可最小化，从而可防止或减少其氧化。
第二半导体芯片500可包括在其下部的第四布线510，并且可通过按次序堆叠的第二导电焊盘520和第二导电凸块530电连接至第一导电焊盘480。
第一半导体芯片和第二半导体芯片500可通过第一非导电层490彼此接合。在实施中，当第一半导体芯片和第二半导体芯片500彼此接合时，第一导电焊盘480和第二导电凸块530可彼此接触，并且第一导电焊盘480的至少中间上表面是平坦的并且不低于第一导电焊盘480的边缘上表面，从而第一非导电层490可不保留在第一导电焊盘480与第二导电凸块530之间。因此，第一导电焊盘480与第二导电凸块530之间的接触电阻可不增大，并且半导体装置的可靠性可提高，随后将详细解释这一点。
图2示出了包括多个再分布层和多个第一导电焊盘的第一半导体芯片的剖视图。为了方便解释，图2中仅示出了一些元件。
参照图2，当形成多个再分布层时，在它们之间可存在厚度分布或差异，并且覆盖再分布层的保护层可在它们的部分之间具有厚度分布。
图2示出了分别具有第一厚度T1和第二厚度T2的第二再分布层和第三再分布层以及分别具有第三厚度T3和第四厚度T4的第二保护层402和第三保护层404，并且第二保护层402和第三保护层404的上表面分别具有第一高度H1和第二高度H2。第二再分布层和第三再分布层可分别包括具有彼此不同的厚度的第四导电层382和第五导电层384。
可通过电镀工艺从钝化层310(参照图13和图14)的平坦上表面形成延伸穿过第二再分布层和第三再分布层并且向上突出的第三导电焊盘482和第四导电焊盘484，因此，不管第二再分布层和第三再分布层的厚度或者第二保护层402和第三保护层404的厚度和高度如何，第三导电焊盘482和第四导电焊盘484都可具有均匀的厚度或高度，从而第三导电焊盘482和第四导电焊盘484的上表面可共同具有第三高度H3。
例如，不管再分布层的厚度分布、保护层的厚度分布和/或保护层的高度分布如何，多个导电焊盘可具有均匀的厚度。
图3至图22示出了根据示例实施例的制造半导体装置的方法中的各阶段的平面图和剖视图。图9A、图9B、图9C和图11是平面图，图3至图8、图10和图12至图22是剖视图。
参照图3，可在衬底100的第一表面101上形成电路元件和接触插塞170。
可形成用作电路元件的晶体管。晶体管可包括：栅极结构140，其包括按次序堆叠在衬底100的第一表面101上的栅极绝缘图案120和栅电极130；以及在衬底100的邻近于栅极结构140的一部分处掺有杂质的杂质区110。还可在栅极结构140的侧壁上形成栅极间隔件150。
第一绝缘夹层160可形成在衬底100上以覆盖电路元件，并且接触插塞170可穿过第一绝缘夹层160形成以接触杂质区110。
可形成初级通孔电极结构210，并且其可部分地延伸穿过衬底100。
例如，部分地暴露出衬底100的第一区I的第一光致抗蚀剂图案可形成在第一绝缘夹层160和接触插塞170上，并且可利用第一光致抗蚀剂图案作为蚀刻掩模蚀刻第一绝缘夹层160和衬底100，以形成第一沟槽。绝缘层180和第一势垒层190可按次序形成在第一沟槽的内壁上，并且第一导电层200可形成在第一势垒层190上以充分填充第一沟槽。
可将第一导电层200、第一势垒层190和绝缘层180平面化，直至暴露出第一绝缘夹层160的顶表面为止，以形成填充第一沟槽的初级通孔电极结构210。
可在第一绝缘夹层160、接触插塞170和初级通孔电极结构210上形成第二绝缘夹层220，并且可在第一区I中的第二绝缘夹层220中形成一条或多条布线240和连接多条布线240的过孔260。
在图中，示出了按次序堆叠的第一布线至第三布线232、234和236以及按次序堆叠的第一过孔252和第二过孔254。
在实施中，可通过双镶嵌工艺或单镶嵌工艺形成布线240和过孔260。布线240和过孔260中的每一个可包括导电图案和覆盖导电图案的表面的势垒图案。
参照图4，在将第一导电凸块280形成在第二绝缘夹层220上以接触第三布线236的上表面之后，可在第二绝缘夹层220和第三布线236上形成粘合层290，并且处理衬底300可附于粘合层290上。
参照图5，可利用处理衬底300将衬底100翻转，以使得衬底100的第二表面102面朝上(例如，如该图所示)。可去除衬底100的邻近于其第二表面102或在其第二表面102上的一部分，以暴露出初级通孔电极结构210的一部分。因此，可通过例如回蚀工艺或研磨工艺部分地去除衬底100。
参照图6，可在衬底100的第二表面102和初级通孔电极结构210的暴露部分上形成钝化层310，并且可在钝化层310上形成第二光致抗蚀剂图案320。
在实施中，钝化层310可包括按次序堆叠的第一氧化物层、氮化物层和第二氧化物层。
在实施中，第二光致抗蚀剂图案320可形成为其上表面低于钝化层310的位于初级通孔电极结构210的在衬底100的第二表面102上方的暴露部分上的一部分的上表面。在实施中，第二光致抗蚀剂图案320可包括用于第二区II中的对准键的第一开口330。
参照图7，可利用第二光致抗蚀剂图案320作为蚀刻掩模部分地蚀刻钝化层310，以在第二区II中的钝化层310上形成对准键315。
初级通孔电极结构210上的钝化层310的一部分可不被第二光致抗蚀剂图案320覆盖，因此，可部分地蚀刻钝化层310的该部分以使得钝化层310的上表面的高度可降低。
在蚀刻处理之后，可去除第二光致抗蚀剂图案320。
参照图8，可将钝化层310的上部平面化，直至暴露出第一导电层200的上表面为止。
因此，可去除绝缘层180和第一势垒层190的在初级通孔电极结构210的第一导电层200上的一些部分，以分别形成绝缘图案185和第一势垒图案195，并且可形成包括第一导电层200以及按次序堆叠在第一导电层200的侧壁上的第一势垒图案195和绝缘图案185的第一通孔电极结构215。
第一区I中的钝化层310的一部分可通过平面化工艺具有平坦的上表面，并且对准键315可仍保留在第二区II中的钝化层310的一部分上。
在实施中，平面化工艺可包括化学机械抛光(CMP)工艺和/或回蚀工艺。
第二势垒层340和第一种层350可按次序形成在钝化层310上，并且第三光致抗蚀剂图案360可形成在第一种层350上。
第一种层350可包括例如铜、钌、镍、金、钨等的金属。在实施中，可通过物理气相沉积(PVD)工艺形成第一种层350。
第三光致抗蚀剂图案360可包括第二开口370，其在第一区I中的第一通孔电极结构215的上表面上暴露出第一种层350的一部分。
参照图9A、图9B和图9C，第二开口370可具有在一个方向上延伸的杆形或者其端部在平面图中具有圆形的杆形，然而，第二开口370可在其中包括不暴露出第一种层350的非暴露部分370a。
参照图10，可利用第一种层350的暴露部分作为种子来执行电镀工艺，以形成填充第二开口370的第二导电层380。
在实施中，可利用包括含铜离子、钌离子、镍离子、钨离子等的电解质溶液的电镀溶液来执行电镀工艺。
可去除第三光致抗蚀剂图案360，以暴露出第一种层350的一部分，并且可去除第一种层350的暴露部分和其下方的第二势垒层340的一部分。因此，第二势垒层340可转变为第二势垒图案345，并且按次序堆叠的第二势垒图案345和第二导电层380可形成第一再分布层。
参照图11，可穿过第一再分布层形成第三开口390，并且在第二区II中可再次暴露出对准键315。
图11示出了可由图9A的第二开口370形成的第一再分布层的形状。在实施中，第一再分布层可具有图9B和图9C所示的第二开口370的形状。
参照图12，第一保护层400可形成在钝化层310上，以覆盖第一再分布层和对准键315。
在实施中，第一保护层400可包括与第三开口390重叠并且与第三开口390连接的第四开口410，并且在平面图中第四开口410的面积可等于或大于第三开口390的面积。
在实施中，第一保护层400可包括光敏有机材料或由光敏有机材料形成，并且可包括热固性有机聚合物和光敏材料。在实施中，可通过旋涂工艺形成第一保护层400，并且第一保护层400可通过热处理硬化。在实施中，第一保护层400中的第四开口410可通过热处理具有不垂直于衬底100的上表面(而是相对于衬底100的上表面倾斜)的侧壁，因此其宽度可从其底部朝顶部(例如，在远离衬底100的方向上)逐渐增大。
可在第三开口390的底部(即，钝化层310的通过第三开口390暴露的上表面)、第三开口390和第四开口410的内壁以及保护层400的上表面上按次序形成第三势垒层420和第二种层430。
参照图13，可在第二种层430上形成包括第五开口450的第四光致抗蚀剂图案440。
第五开口450可与第四开口410重叠并且可与第四开口410连接。在平面图中，第五开口450可具有与第四开口410的形状和面积基本相同的形状和面积。因此，可通过第五开口450暴露第二种层430在第三开口390和第四开口410的底部和侧壁上的一些部分。
可利用第二种层430的暴露部分作为种子来执行电镀工艺，以形成填充第三开口390和第四开口410的一部分的第三导电层460，并且第一封盖层470可形成在第三导电层460上。
可利用包括含金属离子(例如，铜离子、钌离子、镍离子、钨离子等)和添加剂的电解质溶液的电镀溶液执行电镀工艺。
在实施中，金属离子可包括铜离子和镍离子，因此第三导电层460可包括铜，第一封盖层可包括镍。
在示例实施例中，添加剂至少可包括平衡剂，并且还包括抑制剂和加速剂。平衡剂可包括例如聚酰亚胺、聚酰胺等的聚合物，抑制剂可包括例如聚乙二醇(PEG)的聚合物，并且加速剂可包括有机硫化合物。
平衡剂可主要布置在第四开口410的入口，以延迟金属电镀。加速剂可具有相对小的分子大小，因此可容易地渗入第三开口390。然而，抑制剂可具有相对大的分子大小，因此可不容易地渗入第三开口390和第四开口410，并且可主要布置在第四光致抗蚀剂图案440的上表面上。
因此，金属电镀可在第三开口390中通过加速剂加速，并且可在第四开口410的入口、在第五开口450的侧壁上和在第四光致抗蚀剂图案440的上表面上通过平衡剂和/或抑制剂延迟。因此，当第三开口390和第四开口410的下部被填充时，第三导电层460和第一封盖层470可不形成在第四开口410的上部和第五开口450中，因此，第三导电层460和第一封盖层470中的每一个可具有平坦的上表面。
参照图14，在通过例如灰化工艺和/或剥离工艺去除第四光致抗蚀剂图案440之后，可去除第二种层430的暴露部分和其下方的第三势垒层420的一部分。因此，第三势垒层420可转变为第三势垒图案425。
在实施中，可通过湿蚀刻工艺去除第二种层430的暴露部分和其下方的第三势垒层420的一部分。
第三导电层460、覆盖第三导电层460的上表面的第一封盖层470和覆盖第三导电层460的底部和侧壁的第三势垒图案425可形成第一导电焊盘480。第一导电焊盘480可包括延伸穿过第一再分布层的贯穿部分480a和贯穿部分480a上的从第一再分布层的上表面突出的突出部分480b。
在实施中，第三导电层460和第一封盖层470中的每一个的上表面可基本上平坦，因此第一导电焊盘480的至少中间上表面可基本上平坦。例如，如上所述，第一导电焊盘480的中间上表面可不低于其边缘上表面。
在实施中，第一导电焊盘480的上表面可低于(例如，更靠近衬底100)覆盖第一导电焊盘480的侧壁的第一保护层400的上表面。因此，第一导电焊盘480的第三导电层460的暴露可最小化，从而可有利地防止或减少其氧化。
可通过以上工艺形成第一半导体芯片。
图15示出了执行参照图13示出的电镀工艺直至第一封盖层470的上表面的高度等于第二种层430的上表面的高度为止的情况。
参照图16，第三导电层460的上表面或第一导电焊盘480的上表面可稍高于第一保护层400的上表面。然而，与图14相似，第一导电焊盘480的至少中间上表面可基本上平坦，并且第一导电焊盘480的第三导电层460的暴露可最小化，从而可防止或减少其氧化。
图17示出了执行参照图13示出的电镀工艺直至第三导电层460的上表面的高度等于第二种层430的上表面的高度为止的情况。
参照图18，第三导电层460的上表面或第一导电焊盘480的上表面可稍高于第一保护层400的上表面。然而，与图14相似，第一导电焊盘480的至少中间上表面可基本上平坦，并且第一导电焊盘480的第三导电层460的暴露可最小化，从而可防止或减少其氧化。
图19示出了执行参照图13示出的电镀工艺直至第三导电层460和第一封盖层470填充第五开口450的下部为止的情况。
参照图20，第一导电焊盘480的中间上表面可基本上平坦，然而，第一导电焊盘480的第三导电层460的侧壁可部分地暴露出来。
图21示出了以下情况：当第四光致抗蚀剂图案440的第五开口450与第四开口410重叠并且在平面图中第五开口450的面积大于第四开口410的面积时，执行参照图13示出的电镀工艺直至第三导电层460和第一封盖层470填充第五开口450的下部为止。
参照图22，第一导电焊盘480的整个上表面可基本上平坦，然而，第一导电焊盘480的第三导电层460的侧壁可部分地暴露出来。
下文中，将仅描述参照图13和图14示出的情况。
再参照图1A和图1B，第一非导电层490可形成在第一半导体芯片的第一保护层400和第一导电焊盘480上，第二半导体芯片500可通过第一非导电层490接合至第一半导体芯片上，并且可从第一半导体芯片分开或去除处理衬底300和粘合层290。
第二半导体芯片500可在其中包括第四布线510，并且第二导电焊盘520和第二导电凸块530可按次序形成在第二半导体芯片500上。因此，第二半导体芯片500可通过第二导电焊盘520和第二导电凸块530电连接至第一半导体芯片。
在实施中，第一半导体芯片和第二半导体芯片500可通过热压非导电浆料(TCNCP)方法彼此接合。例如，可在高温下朝着第一半导体芯片的第一导电焊盘480按压第二半导体芯片500的第二导电焊盘520，从而使得第二导电凸块530可接合至第一导电焊盘480。另外，第一非导电层490可填充第一半导体芯片与第二半导体芯片500之间的空间，因此第一半导体芯片和第二半导体芯片500可附接于彼此。
在接合工艺中，具有流动性的第一非导电层490可被挤出第二导电凸块530之外。如上所述，第一导电焊盘480的至少中间上表面可基本上平坦，因此在第一导电焊盘480上可不保留第一非导电层490。因此，在第一导电焊盘480与第二导电凸块530之间可不存在异物，从而第一导电焊盘480与第二导电凸块530之间的接触电阻可不减小，并且半导体装置的可靠性可提高。
下文中，将参照图2描述形成多个再分布层和多个导电焊盘的情况。
当形成多个再分布层(参照图10和图11)时，在所述多个再分布层之间可存在厚度分布或差异，并且保护层(参照图12)在所述多个再分布层上也可具有厚度分布。
图2示出了分别具有第一厚度T1和第二厚度T2的第二再分布层和第三再分布层以及分别具有第三厚度T3和第四厚度T4的第二保护层402和第三保护层404，并且第二保护层402和第三保护层404的上表面分别具有第一高度H1和第二高度H2。第二再分布层和第三再分布层可分别包括具有彼此不同的厚度的第四导电层382和第五导电层384。
当执行参照图13示出的电镀工艺时，可从钝化层310的平坦上表面执行电镀工艺，因此第三导电焊盘482和第四导电焊盘484可具有基本相同的厚度，不管第二再分布层和第三再分布层的厚度或者第二保护层402和第三保护层404的厚度或高度如何。因此，第三导电焊盘482和第四导电焊盘484的上表面可具有基本相同的高度，即，第三高度H3。
例如，不管再分布层的厚度分布、保护层的厚度分布或者保护层的高度分布如何，多个导电焊盘都可具有均匀的厚度。
图23示出了根据比较例的半导体装置的剖视图。除第一导电焊盘之外，该半导体装置可与图1A和图1B的半导体装置基本相同。因此，相同的附图标记指代相同元件，并且本文省略对其的详细描述。
参照图23，半导体装置的第一半导体芯片可包括第四再分布层上的第五导电焊盘485，并且可通过第一非导电层490与第二半导体芯片500接合。第一半导体芯片和第二半导体芯片500可通过第五导电焊盘485和第二导电凸块530彼此电连接。
第四再分布层可包括按次序堆叠的第二势垒图案345和第六导电层385。
第五导电焊盘485可包括第七导电层465、第二封盖层475和第四势垒图案427，并且第五导电焊盘485的中间上表面可为凹进的，以比其边缘上表面更低(例如，更靠近衬底100)。因此，当将第二导电凸块530按压至第五导电焊盘485上时，第一非导电层490的一部分可保留在第二导电凸块530与第五导电焊盘485之间，其可增大它们之间的接触电阻并且降低半导体装置的可靠性。另外，第五导电焊盘485的第七导电层465的上侧壁可暴露出来，从而第七导电层465可由于氧化而变弱。
可通过电镀工艺从通过第四开口410(参照图26)暴露的第四再分布层的上表面形成第五导电焊盘485，直至其形成在第一保护层400的上表面上为止，因此，如果形成多个第四再分布层，则根据第四再分布层的厚度分布和/或第一保护层400的厚度分布，第五导电焊盘485可不形成为具有均匀厚度。下面将详细描述这一点。
图24至图28示出了制造图23的半导体装置的方法的各阶段的剖视图。该方法可包括与参照图3至图22示出的那些基本相同或相似的处理，因此本文可省略对其的详细描述。
执行与参照图3至图7示出的那些基本相同或相似的处理。
参照图24，可执行与参照图8示出的那些基本相同或相似的处理。
然而，作为包括第二开口370的第三光致抗蚀剂图案360的替代，可形成包括第六开口375的第五光致抗蚀剂图案365。与第二开口370不同，在第六开口375中可不包括非暴露部分。
参照图25，可执行与参照图10示出的那些基本相同或相似的处理。
因此，可通过电镀工艺形成第六导电层385以填充第六开口375，并且第四再分布层可与第二势垒图案345一起形成。
参照图26，可执行与参照图12示出的那些基本相同或相似的处理，以在钝化层310上形成第一保护层400来覆盖第四再分布层。
在实施中，第一保护层400可包括第四开口410，其暴露出第四再分布层的第六导电层385的上表面。
第三势垒层420和第二种层430可按次序形成在第六导电层385的暴露的上表面、第四开口410的侧壁和第一保护层400的上表面上。
参照图27，可在第二种层430上形成包括连接至第四开口410的第五开口450的第四光致抗蚀剂图案440，并且可利用第二种层的暴露的部分执行电镀工艺。
第五开口450可与第四开口410重叠并且在平面图中可具有比第四开口410的面积更大的面积，并且可形成第七导电层465和第二封盖层475以填充第四开口410和第五开口450的下部。
可从通过第四开口410和第五开口450的底部和侧壁暴露的第一保护层400的上表面执行电镀工艺，并且第七导电层465和第二封盖层475中的每一个的中间上表面可根据第四开口410的深度而凹进。例如，第七导电层465和第二封盖层475中的每一个的中间上表面可低于其边缘上表面。
参照图28，可执行与参照图14示出的那些基本相同或相似的处理，以去除第四光致抗蚀剂图案440以及其下方的第二种层430的暴露部分和第三势垒层420的一部分。因此，第三势垒层420可转变为第四势垒图案427。
可在第四再分布层上形成包括第七导电层465、第二封盖层475和第四势垒图案427的第五导电焊盘485，并且第五导电焊盘485的中间上表面可低于其边缘上表面。另外，第五导电焊盘485的第七导电层465的上侧壁可暴露出来，从而在氧化下是薄弱的。
可从通过第四开口410暴露的第四再分布层的上表面执行电镀工艺以形成第五导电焊盘485，直至第五导电焊盘485可形成在第一保护层400的上表面上为止，因此，如果形成多个第四再分布层，则根据第四再分布层的厚度分布和/或第一保护层400的厚度分布，第五导电焊盘485可不形成为具有均匀厚度。
再参照图23，可执行与参照图1A和图1B示出的那些基本相同或相似的处理，以完成制造半导体装置。
第五导电焊盘485的中间上表面可为凹进的，并且低于其边缘上表面，因此，当将第二导电凸块530按压至第五导电焊盘485上时，第一非导电层490的一部分可保留在第二导电凸块530与第五导电焊盘485之间。因此，第二导电凸块530与第五导电焊盘485之间的接触电阻可增大，并且半导体装置的可靠性可降低。
图29A、图29B、图29C和图29D示出了根据示例实施例的半导体装置的第一半导体芯片中的第一导电焊盘的形状的剖视图。
在实施中，参照图29A、图29B、图29C和图29D，第一导电焊盘480中的每一个的突出部分480b的至少下侧壁可基本垂直于衬底100的上表面。当执行参照图13和图14示出的电镀工艺时，第一保护层400的第四开口410可具有垂直于衬底100的上表面的侧壁，因此，第一导电焊盘480中的每一个的突出部分480b可具有基本垂直于衬底100的上表面的侧壁。
图30示出了根据示例实施例的半导体封装件的剖视图。该半导体封装件可为包括参照图1A和图1B所示的半导体装置的CMOS图像传感器(CIS)封装件。
参照图30，CIS封装件可包括按次序堆叠的第三半导体芯片600、第一半导体芯片和第二半导体芯片500，并且第一半导体芯片和第二半导体芯片500可如图1A和图1B所示地彼此接合，并且可通过第一导电焊盘480和第二导电焊盘520以及第二导电凸块530彼此电连接。
与图1A和图1B不同，在第一半导体芯片下方可不形成第一导电凸块280，并且第三半导体芯片600和第一半导体芯片可通过晶圆对晶圆接合方法彼此接合。因此，第一半导体芯片中的第三布线236和第三半导体芯片600中的第五布线610可彼此连接，并且第一半导体芯片和第三半导体芯片600的绝缘层可附接于彼此。
在实施中，第三半导体芯片600可包括CIS芯片，第一半导体芯片可包括逻辑芯片，并且第二半导体芯片500可包括例如DRAM芯片的存储器芯片。
图31示出了根据示例实施例的半导体封装件的剖视图。该半导体封装件可为包括参照图1A和图1B所示的半导体装置的集成扇出(INFO)封装件。
参照图31，INFO封装件可包括按次序堆叠的第四保护层780、第三绝缘夹层740和第四半导体芯片710。
再分布层760和第三过孔770可形成在第三绝缘夹层740中。在图中，再分布层760包括按次序堆叠的第六再分布层754和第五再分布层752，然而，本发明构思可不限于此。
可形成包括延伸穿过第六再分布层754的贯穿部分820a和从第六再分布层754的下表面向下突出的突出部分820b的第六导电焊盘820，并且第六导电焊盘820的突出部分820b的侧壁可被第四保护层780覆盖。第六导电焊盘820可包括第八导电层800、第三封盖层810和第五势垒图案795。
半导体封装件还可包括附接于第六导电焊盘820的下表面上的第四导电凸块830、以及与第三绝缘夹层740上的第四半导体芯片710间隔开的第三导电凸块720。第四半导体芯片710和第三导电凸块720的侧壁可由模制元件730(例如，环氧模制化合物(EMC))覆盖。
在实施中，第四半导体芯片710中的每一个可包括逻辑芯片或存储器芯片。
半导体封装件可用作印刷电路板(PCB)。
图32示出了制造图31的半导体封装件的方法中的各阶段的剖视图。
参照图32，可在晶圆700上安装第四半导体芯片710和第三导电凸块720，并且可利用模制元件730将上结构附着于晶圆700。
所述上结构可包括：第三绝缘夹层740，其包含再分布层760和连接再分布层760的第三过孔770；第六导电焊盘820，其延伸穿过再分布层760之一；第四保护层780，其包围第六导电焊盘820的上侧壁；以及第四导电凸块830，其附着于第六导电焊盘820的上表面。
再参照图31，在将晶圆700旋转180度之后，可将晶圆700锯切为包括一个或多个第四半导体芯片710和第三导电凸块720，从而可制造半导体封装件。
图33示出了根据示例实施例的半导体封装件的剖视图。该半导体封装件可为包括参照图1A和图1B所示的半导体装置的高带宽存储器(HBM)封装件。
参照图33，半导体封装件可包括封装件衬底1000、插入件1100、逻辑芯片1200和存储器芯片。半导体封装件还可包括在插入件1100上与逻辑芯片1200间隔开的GPU芯片1300。在附图中，示出了四个存储器芯片，即，第一存储器芯片至第四存储器芯片1400、1500、1600和1700，然而，本发明构思可不限于此。
例如，封装件衬底1000可包括PCB。可在封装件衬底1000下方形成外连接端子1050，因此，半导体封装件可通过外连接端子1050安装在模块衬底上。
第五导电凸块1150可形成在封装件衬底1000与插入件1100之间，第六导电凸块1250可形成在插入件1100与逻辑芯片1200之间，第七导电凸块1350可形成在插入件1100与GPU芯片1300之间，第八导电凸块1450可形成在逻辑芯片1200与第一存储器芯片1400之间，第九导电凸块1550可形成在第一存储器芯片1400与第二存储器芯片1500之间，第十导电凸块1650可形成在第二存储器芯片1500与第三存储器芯片1600之间，并且第十一导电凸块1750可形成在第三存储器芯片1600与第四存储器芯片1700之间。
第六布线至第八布线1110、1120和1130可形成在插入件1100中。第六布线1110可将各个第五导电凸块1150电连接至各个第六导电凸块1250，第七布线1120可将各个第五导电凸块1150电连接至各个第七导电凸块1350，并且第八布线1130可将各个第六导电凸块1250电连接至各个第七导电凸块1350。
逻辑芯片1200可包括第二通孔电极结构1210、第九布线1220、第七再分布层1230、第七导电焊盘1280和第五保护层1240。
第九布线1220可将各个第六导电凸块1250电连接至第二通孔电极结构1210，第七再分布层1230可电连接至第二通孔电极结构1210，第七导电焊盘1280可延伸穿过第七再分布层1230以向上突出，并且第五保护层1240可包围第七导电焊盘1280的上侧壁。第七导电焊盘1280可包括第九导电层1260、第四封盖层1270和第六势垒图案1255。
第一存储器芯片1400可包括彼此电连接的第三通孔电极结构1430、第十布线1410和第八导电焊盘1420，并且可通过第八导电凸块1450电连接至第七导电焊盘1280。另外，逻辑芯片1200和第一存储器芯片1400可通过第二非导电层1290彼此接合。
第二存储器芯片至第四存储器芯片1500、1600和1700可分别包括第四通孔电极结构至第六通孔电极结构1530、1630和1730以及第十一布线至第十三布线1510、1610和1710。
如本领域中常规的那样，按照功能块、单元和/或模块在附图中描述并示出实施例。本领域技术人员应该理解，通过可利用基于半导体的制造技术或者其它制造技术形成的诸如逻辑电路、分立的组件、微处理器、硬连线电路、存储器元件、布线连接等的电子(或光学)电路在物理上实现这些块、单元和/或模块。在通过微处理器或类似元件实现块、单元和/或模块的情况下，可利用软件(例如，微代码)来执行本文讨论的各种功能对所述块、单元和/或模块进行编程并且可通过固件和/或软件可选地驱动所述块、单元和/或模块。可替换地，各个块、单元和/或模块可通过专用硬件来实现，或者实现为用于执行一些功能的专用硬件与用于执行其它功能的处理器(例如，一个或多个编程的微处理器和关联电路)的组合。另外，在不脱离本文的范围的情况下，实施例的各个块、单元和/或模块可在物理上分为两个或更多个相互配合的和分立的块、单元和/或模块。此外，在不脱离本文的范围的情况下，实施例的块、单元和/或模块可在物理上组合为更多个复杂的块、单元和/或模块。
作为总结和回顾，如果异物介于导电凸块与导电焊盘之间，则可能发生粘合失效，并且半导体封装件的可靠性可能降低。
实施例可提供包括再分布层的半导体装置。
实施例可提供具有高可靠性的半导体装置。
实施例可提供具有高可靠性的半导体封装件。
实施例可提供一种制造具有高可靠性的半导体装置的方法。
在根据示例实施例的半导体装置中，在将上下半导体芯片彼此电连接的导电凸块与下半导体芯片之间可不存在异物，因此可减小导电凸块与下半导体芯片之间的接触电阻，并且可提高半导体装置的可靠性。
本文已公开了示例实施例，虽然采用了特定术语，但是仅按照一般和描述性含义而非针对限制的目的使用和解释它们。在一些情况下，如本领域普通技术人员之一在本申请提交时应该清楚的，除非另有说明，否则结合特定实施例描述的特征、特性和/或元件可单独使用或者与结合其它实施例描述的特征、特性和/或元件联合使用。因此，本领域技术人员应该理解，在不脱离所附权利要求阐述的本发明的精神和范围的情况下，可作出各种形式和细节上的改变。

Claims (25)

1.一种半导体装置，包括：
延伸穿过衬底的通孔电极结构；
所述通孔电极结构上的再分布层；以及
导电焊盘，该导电焊盘包括：
贯穿部分,其延伸穿过所述再分布层；以及
所述贯穿部分上的突出部分，所述突出部分从所述再分布层的上表面突出，其中所述突出部分的上表面的中间区平坦，并且不比所述突出部分的上表面的边缘区更靠近所述衬底。
2.根据权利要求1所述的半导体装置，其中，所述导电焊盘的突出部分的侧壁相对于所述衬底的上表面倾斜。
3.根据权利要求2所述的半导体装置，其中，所述导电焊盘的突出部分的上表面的边缘区具有与所述突出部分的侧壁的斜坡相对的斜坡。
4.根据权利要求1所述的半导体装置，其中，所述导电焊盘的突出部分的侧壁垂直于所述衬底的上表面。
5.根据权利要求1所述的半导体装置，其中，所述导电焊盘的贯穿部分的侧壁垂直于所述衬底的上表面。
6.根据权利要求1所述的半导体装置，其中：
所述导电焊盘的贯穿部分的上表面与所述再分布层的上表面共面，并且
所述贯穿部分和所述突出部分彼此一体地形成。
7.根据权利要求1所述的半导体装置，其中，所述导电焊盘包括：
导电层，以及
覆盖所述导电层的底部和侧壁的势垒图案。
8.根据权利要求7所述的半导体装置，其中，所述导电焊盘还包括所述导电层的上表面上的封盖层。
9.根据权利要求8所述的半导体装置，其中，所述封盖层覆盖所述导电层的上表面的中间区而不覆盖所述导电层的上表面的边缘区。
10.根据权利要求8所述的半导体装置，其中：
所述导电层包括铜，
所述势垒图案包括氮化钛，并且
所述封盖层包括镍。
11.根据权利要求1所述的半导体装置，还包括保护层，其覆盖所述再分布层以及所述导电焊盘的突出部分的侧壁的至少一部分。
12.根据权利要求11所述的半导体装置，其中，所述保护层不覆盖所述导电焊盘的上表面。
13.根据权利要求11所述的半导体装置，其中，所述导电焊盘的上表面比所述保护层的上表面更靠近所述衬底。
14.根据权利要求11所述的半导体装置，其中，所述导电焊盘的上表面比所述保护层的上表面更远离所述衬底。
15.根据权利要求11所述的半导体装置，其中，所述保护层包括热固性有机聚合物。
16.一种半导体装置，包括：
延伸穿过衬底的通孔电极结构；
所述通孔电极结构上的再分布层；以及
导电焊盘，所述导电焊盘中的每一个包括：
贯穿部分，其延伸穿过所述再分布层中的一个；以及
所述贯穿部分上的突出部分，所述突出部分从所述再分布层中的所述一个的上表面突出，
其中，所述再分布层中的至少两个具有彼此不同的厚度，并且
其中，所述导电焊盘的上表面相对于所述衬底具有相同高度。
17.根据权利要求16所述的半导体装置，其中：
所述再分布层中的所述至少两个分别是第一再分布层和第二再分布层，并且
所述第一再分布层的厚度大于所述第二再分布层的厚度。
18.根据权利要求17所述的半导体装置，其中：
延伸穿过所述第一再分布层的第一导电焊盘的第一贯穿部分的厚度大于延伸穿过所述第二再分布层的第二导电焊盘的第二贯穿部分的厚度，并且
所述第一导电焊盘的第一突出部分的厚度小于所述第二导电焊盘的第二突出部分的厚度。
19.根据权利要求17所述的半导体装置，还包括保护层，其覆盖所述再分布层以及所述导电焊盘中的每一个的突出部分的侧壁的至少一部分。
20.根据权利要求19所述的半导体装置，其中，所述保护层的上表面不具有均匀的高度。
21.根据权利要求20所述的半导体装置，其中，覆盖所述第一再分布层的所述保护层的第一部分的上表面比覆盖所述第二再分布层的所述保护层的第二部分的上表面更加远离所述衬底。
22.根据权利要求20所述的半导体装置，其中，覆盖所述第一再分布层的所述保护层的第一部分的厚度与覆盖所述第二再分布层的所述保护层的第二部分的厚度相同。
23.根据权利要求20所述的半导体装置，其中，覆盖所述第一再分布层的所述保护层的第一部分的厚度与覆盖所述第二再分布层的所述保护层的第二部分的厚度不同。
24.根据权利要求16所述的半导体装置，其中，所述导电焊盘中的每一个的突出部分的上表面的中间区不比所述突出部分的上表面的边缘区更靠近所述衬底。
25.一种半导体装置，包括：
第一半导体芯片，该第一半导体芯片包括延伸穿过衬底的通孔电极结构、所述通孔电极结构上的再分布层、以及第一导电焊盘，该第一导电焊盘包括：
贯穿部分，其延伸穿过所述再分布层；和
所述贯穿部分上的突出部分，所述突出部分从所述再分布层的上表面突出，并且所述突出部分的上表面的中间区平坦并且不比所述突出部分的上表面的边缘区更靠近所述衬底；以及位于所述第一半导体芯片的一侧的第二半导体芯片，所述第二半导体芯片通过所述第一导电焊盘电连接至所述第一半导体芯片。
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