CN105793964A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN105793964A
CN105793964A CN201480027415.6A CN201480027415A CN105793964A CN 105793964 A CN105793964 A CN 105793964A CN 201480027415 A CN201480027415 A CN 201480027415A CN 105793964 A CN105793964 A CN 105793964A
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China
Prior art keywords
film
metal film
covering
base metal
semiconductor device
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CN201480027415.6A
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Inventor
前川和义
河野祐
河野祐一
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Renesas Electronics Corp
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Renesas Electronics Corp
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Publication of CN105793964A publication Critical patent/CN105793964A/zh
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Abstract

半导体器件具有形成于多层布线层的最上层的焊盘电极(9a)、在焊盘电极(9a)上有开口(11a)的基底绝缘膜(11)、形成在基底绝缘膜(11)上的基底金属膜(UM)、形成在基底金属膜(UM)上的再布线(RM)、和形成为覆盖再布线(RM)的上表面以及侧面的覆盖金属膜(CM)。而且，在再布线(RM)的外侧区域，在形成在再布线(RM)的侧壁上的覆盖金属膜(CM)与基底绝缘膜(11)之间形成有材料不同于再布线(RM)的基底金属膜(UM)和材料不同于再布线(RM)的覆盖金属膜(CM)，在再布线(RM)的外侧区域基底金属膜(UM)与覆盖金属膜(CM)直接接触。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体器件及其制造方法，尤其涉及适用于在半导体基板的主面上所形成的多层布线层的上部具有用金属膜构成的再布线的半导体器件及其制造方法的有效技术。
背景技术
半导体器件中，在形成有例如CMIS(ComplementaryMetalInsulatorSemiconductor，互补金属绝缘体半导体)晶体管等半导体元件的半导体基板的上部用以例如Cu(铜)或Al(铝)为主成分的金属膜形成有多层布线，在多层布线的上部形成有最终钝化膜。
日本特开2003-234348号公报(专利文献1)中公开了下述技术：在最终钝化膜上形成以Cu为主成分的再布线，将形成于最终钝化膜之下的最上层布线的电极焊盘与再布线电连接。
在日本特开2012-4210号公报(专利文献2)的图25中公开了下述构造：线20连接于形成为局部覆盖以Cu为主要成分的再布线15的上表面以及侧面的焊盘18。
在日本特开2000-306938号公报(专利文献3)的摘要中公开了下述内容：通过用在钝化膜6上具有伸出的伸出部位9的屏蔽金属膜8完全覆盖形成于钝化膜4上的由铝合金构成的再布线层6，从而抑制再布线层6发生迁移、腐蚀。
“DevelopmentofhighlyreliableCuwiringofL/S＝1/1μmforchiptochipinterconnection"(非专利文献1)中公开了下述构造：为了提高用SAP(Semi-AdditivePrtocess)法形成的Cu布线的可靠性，在Cu布线的上表面以及侧面设置有用无电解镀敷法形成的金属屏蔽膜。
现有技术文献
专利文献
专利文献1:日本特开2003-234348号公报
专利文献2:日本特开2012-4210号公报
专利文献3:日本特开2000-306938号公报
非专利文献
非专利文献1:T.Kankietal.，“DevelopmentofhighlyreliableCuwiringofL/S＝1/1μmforchiptochipinterconnection"InterconnectTechnologyConference，2012IEEEInternational，4-6June2012
发明内容
发明要解决的课题
本申请的发明人所研究的具有再布线的半导体器件(半导体集成电路装置)具有半导体芯片、连接于半导体芯片的线(wire)和对半导体芯片以及线进行封固的封固体。半导体芯片具有半导体元件、电连接于半导体元件且以Cu为主成分的再布线、和将半导体元件与再布线电连接的由多层布线层构成的布线。再布线连接于焊盘电极即由多层布线层的最上层布线层所形成的布线的一部分。由最上层布线层所形成的布线与再布线之间，通过将由最上层布线层所形成的布线覆盖的表面保护膜与形成于表面保护膜上的第一有机保护膜而电分离，再布线经由设置为将焊盘电极露出的表面保护膜与第一有机保护膜的开口而与焊盘电极电连接。再布线的上表面和侧面被第二有机保护膜覆盖，第二有机保护膜具有将在再布线的上表面形成的外部焊盘电极露出的开口，线通过该开口部连接于再布线。
在半导体芯片形成有多条再布线，再布线的最小线宽为12μm，相邻的再布线的最小间隔为15μm。在再布线的下表面设置有用于形成再布线的由金属膜(例如Cr膜)构成的种子层，但再布线的上表面以及侧面与第二有机保护膜接触。
本申请发明人所研究的半导体器件，要求高耐压性、高可靠性，实施了被称为HAST(HighlyAcceleratedtemperatureandhumidityStressTest)试验的高温高湿气氛中的工作试验。根据本申请发明人的研究，判明：在HAST试验中，在相邻的再布线之间，从一条再布线以树枝状析出Cu，相邻的再布线之间发生耐压劣化或短路，半导体器件的可靠性降低。而且，还发现：Cu的树枝状析出，在表面保护膜与第一有机保护膜的界面或第一有机保护膜与第二有机保护膜的界面发生。
根据本申请发明人的分析，将由Cu构成的再布线覆盖的第一以及第二有机保护膜由聚酰亚胺膜构成，含有水分、卤素离子，所以构成再布线的Cu的表面会被氧化，其结果，产生Cu离子(离子化的Cu)。在上述半导体器件中，相邻再布线的最小间隔(15μm)虽然大，但是被施加高电压，在相邻的再布线之间存在施加高电场的区域，在该区域会发生Cu的树枝状析出。也就是，一般认为：Cu离子在高电场的影响下，在表面保护膜与第一有机保护膜的界面或第一有机保护膜与第二有机保护膜的界面移动(扩散)从而相邻的再布线之间发生耐压劣化或短路，半导体器件的可靠性降低。
本发明的目的在于提供在具有再布线的半导体器件中能够提高可靠性的技术。
本发明的上述以及其他目的和新特征，可根据本说明书的记载以及附图加以明确。
用于解决课题的技术方案
作为一个实施方式的半导体器件具有：形成于多层布线层的最上层的焊盘电极、在焊盘电极上有开口的保护膜、形成在保护膜上的基底金属膜、形成在基底金属膜上的再布线、和形成为覆盖再布线的上表面以及侧面的覆盖金属膜。而且，在再布线的外侧区域，在形成在再布线的侧壁上的覆盖金属膜与保护膜之间，形成有材料不同于再布线的基底金属膜和材料不同于再布线的覆盖金属膜，在再布线的外侧区域基底金属膜与覆盖金属膜直接接触。
发明效果
根据一个实施方式，能够提高具有再布线的半导体器件的可靠性。
附图说明
图1是作为本发明的实施方式1的半导体器件的电路框图。
图2是形成有作为本发明的实施方式1的半导体器件的半导体芯片的整体俯视图。
图3是放大表示图2的一部分的俯视图。
图4是沿图3的A-A线的剖视图。
图5是本实施方式1的半导体器件的制造工序中的剖视图。
图6是相继于图5的半导体器件的制造工序中的剖视图。
图7是相继于图6的半导体器件的制造工序中的剖视图。
图8是相继于图7的半导体器件的制造工序中的剖视图。
图9是相继于图8的半导体器件的制造工序中的剖视图。
图10是相继于图9的半导体器件的制造工序中的剖视图。
图11是相继于图10的半导体器件的制造工序中的剖视图。
图12是相继于图11的半导体器件的制造工序中的剖视图。
图13是相继于图12的半导体器件的制造工序中的剖视图。
图14是作为变形例1的半导体器件的制造工序中的剖视图。
图15是作为变形例2的半导体器件的制造工序中的剖视图。
图16是作为变形例3的半导体器件的制造工序中的剖视图。
图17是作为变形例4的半导体器件的制造工序中的剖视图。
图18是作为比较例的半导体器件的制造工序中的剖视图。
图19是相继于图18的作为比较例的半导体器件的制造工序中的剖视图。
图20是实施方式2的半导体器件的制造工序中的剖视图。
图21是相继于图20的半导体器件的制造工序中的剖视图。
图22是作为变形例5的半导体器件的制造工序中的剖视图。
具体实施方式
在以下的实施方式中，根据需要，为了方便分成多个章节或实施方式进行说明，它们并不是彼此无关的，一方与另一方是部分或全部的变形例、应用例、详细说明、补充说明等关系，除特别明示的情况外。另外，在以下的实施方式中，在言及要素的数量等(包括个数、数值、数量、范围等)的情况下，不限定于该特定数量，既可以在特定数量以上也可以在该特定数量以下，除特别明示以及从原理上明确限定为特定数量等情况外。
进一步，在以下的实施方式中，其构成要素(也包括要素步骤等)，除特别明示以及认为是从原理上必需明确等情况外，并不是必需的。同样，在以下的实施方式中，在言及构成要素等的形状、位置关系等时，包括实质上接近或类似于该形状等的形状，除特别明示以及认为是从原理上就不明确等情况外。这一点对于上述数量等(包括个数、数值、数量、范围等)也是同样的。
以下，基于附图详细地对本发明的实施方式进行说明。此外，在用于说明实施方式的全部附图中，对具有同一功能的部件标注同ー或相关联的符号，省略其重复说明。另外，在存在多个类似部件(部位)的情况下，有时在统称的符号上追加记号来表示单独或特定的部位。另外，在以下的实施方式中，除特别需要时以外原则上不重复对同ー或同样部分的说明。
另外，在实施方式中使用的附图中，即使是剖视图，为了易于读图有时也会省略阴影线。另外，即使是俯视图，为了易于读图有时也会标注阴影线。
另外，在剖视图以及俯视图中，各部位的大小不与实际器件相对应，为了易于读图，有时将特定部位相对较大地显示。另外，在俯视图与剖视图相对应的情况下，有时也改变各部位的大小而表示。
(实施方式1)
本实施方式1以及以下的实施方式的半导体器件(半导体集成电路装置)具有半导体芯片，该半导体芯片例如具有：多个半导体元件、形成于多个半导体元件的上部的多层布线(多层布线)、和连接于多层内的最上层的布线的多条再布线，将多个半导体元件通过所述多层布线以及多条再布线连接而构成。
＜关于半导体器件＞
图1是半导体器件的电路框图。如图1所示，半导体器件具备例如在半导体芯片1A的器件面所形成的输入输出(I/O)电路、模拟电路、CMIS-逻辑电路、功率-MIS电路以及存储器电路，从而构成了半导体器件。
在构成半导体器件的上述电路中，CMIS-逻辑电路由例如工作电压1～3V的CMIS晶体管构成，I/O电路以及存储器电路由例如工作电压1～3V以及5～8V的CMIS晶体管构成。
工作电压1～3V的CMIS晶体管由具有第一栅极绝缘膜的第一n沟道型MISFET(MetalInsulatorSemiconductorFieldEffectTransistor，金属-绝缘体-半导体场效应晶体管)与具有第一栅极绝缘膜的第一p沟道型MISFET构成。另外，工作电压5～8V的CMIS晶体管由具有第二栅极绝缘膜的第二n沟道型MISFET与具有第二栅极绝缘膜的第二p沟道型MISFET构成。第二栅极绝缘膜的膜厚构成为比第一栅极绝缘膜的膜厚。在以下的说明中，将MISFET称为MIS晶体管。
另外，模拟电路由例如工作电压5～8V的CMIS晶体管(或双极性晶体管)、电阻元件和电容元件构成，功率-MIS电路由例如工作电压5～8V的CMIS晶体管和工作电压20V～l00V的高耐压MIS晶体管(高耐压元件)构成。
高耐压MIS晶体管由例如具有第三栅极绝缘膜的第三n沟道型MISFET、或具有第三栅极绝缘膜的第三p沟道型MISFET、或两方构成。构成为，在栅电极与漏极区域之间、或栅电极与源极区域之间施加20V～l00V的电压的情况下，第三栅极绝缘膜的膜厚变得比第二栅极绝缘膜的膜厚厚。
图2是表示半导体芯片1A的一例的整体俯视图，图3是图2的由虚线X包围的区域的放大俯视图，图4是沿图3的A-A线的剖视图。
图2示出在半导体芯片1A的器件面上所形成的再布线RM、RMV、RMS的布局的一例。再布线RM、RMV、RMS与半导体芯片1A的多层布线(图4所示的第一层Al布线5、第二层Al布线7、第三层Al布线9)相比，其膜厚以及布线宽度都大，所以与多层布线相比，为非常低的阻抗。再布线RM、RMV、RMS用作例如信号输入输出用的再布线RM、电源(Vcc、GND)供给用的再布线RMV以及内部电路间的连接用的再布线RMS。
如图2所示，在半导体芯片1A的周边部，配置有构成半导体器件的外部连接端子的多条再布线RM。在构成半导体器件的外部连接端子的再布线RM各自的一端形成有外部焊盘电极18，另一端如图3、4所示连接于在最上层的布线所形成的焊盘电极9a。外部焊盘电极18没有特别限定，沿半导体芯片1A的各边配置成ー列。此外，外部焊盘电极18当然也可以沿半导体芯片1A的各边配置成锯齿状、或配置成3列以上。也就是，再布线RM是例如构成图1的输入输出(I/O)电路的信号输入输出用的再布线。
另外，图2所示的再布线RMV是电源(Vcc、GND)供给用的再布线。在再布线RMV的一端形成有外部焊盘电极18，另一端连接于在半导体芯片1A内的电源布线上所形成的焊盘电极9a，所以能够以低阻抗将从半导体芯片1A外部供给的电源(Vcc、GND)电压供给到半导体芯片1A内的多条电源布线。
另外，图2所示的再布线RMS用作将在半导体芯片1A所形成的电路之间或元件之间连接起来的布线。因此，在再布线RMS不形成外部焊盘电极18。再布线RMS的两端连接于在布线上所形成的焊盘电极9a。
图3是示出相邻的2条信号输出输出用的再布线RM的放大俯视图。相邻的2条再布线RM具有相互相同的平面形状，所以以位于纸面上部的再布线RM为例进行说明。再布线RM沿纸面的X方向延伸，在其另一端电连接于在纸面的X方向上延伸的布线9的焊盘电极9a。在再布线RM的另一端形成有外部焊盘电极18。再布线RM具有第一俯视图案P1，基底金属膜UM以及覆盖金属膜CM具有第二俯视图案P2。第一俯视图案P1与第二俯视图案P2为相似形状，第二俯视图案P2具有将第一俯视图案P1放大后的形状。在再布线RM的整个周围，配置有由基底金属膜UM以及覆盖金属膜CM构成的伸出部PP。也就是，若将第一俯视图案P1按伸出部PP的宽度S3扩大则成为第二俯视图案P2。
另外，再布线RM的最小布线宽度L为例如12μm，相邻的再布线RM的最小布线间隔S1为15μm，相邻的伸出部PP之间的最小间隔S2为10μm，伸出部PP的伸出量S3为2.5μm。
理想地，遍及再布线RM的整个周围，伸出部PP的伸出量S3相等，但是第二俯视图案P2如果相对于第一俯视图案P1例如向X方向按α偏离也可以。在第二俯视图案P2相对于第一俯视图案P1向X方向按α偏离的情况下，第一俯视图案P1的右侧边的伸出量成为S3R＝(S3+α)，左侧边的伸出量成为S3L＝(S3-α)。
在本实施方式1中，确保伸出量S3足够，减少侧的伸出量S3L＝(S3-α)比图4所示的在再布线RM的侧面上所形成的覆盖金属膜CM的膜厚大。
如图4所示，在由例如p型单晶硅构成的半导体基板1P形成有p型阱2P、n型阱2N以及元件分离槽3，由例如氧化硅膜构成的元件分离绝缘膜3a埋入元件分离槽3的内部。
在上述p型阱2P内形成有n沟道型MIS晶体管(Qn)。n沟道型MIS晶体管(Qn)形成于由元件分离槽3规定的活性区域，具有在p型阱2P内所形成的源极区域ns以及漏极区域nd、和在p型阱2P上隔着栅极绝缘膜ni所形成的栅电极ng。另外，在上述n型阱2N内形成有p沟道型MIS晶体管(Qp)，该p沟道型MIS晶体管(Qp)具有源极区域ps以及漏极区域pd和在n型阱2N上隔着栅极绝缘膜pi所形成的栅电极pg。
在上述n沟道型MIS晶体管(Qn)以及p沟道型MIS晶体管(Qn)的上部，形成有将半导体元件之间连接起来的由金属膜构成的布线。将半导体元件之间连接起来的布线，一般具有3层～10层左右的多层布线构造，但是图4中作为多层布线的一例示出了由以Al合金为主体的金属膜构成的3层布线层(第一层Al布线5、第二层Al布线7、第三层Al布线9)。所谓布线层，在总结表示用各布线层形成的多条布线的情况下使用。关于布线层的膜厚，第二层的布线层比第一层的布线层厚，第三层的布线层比第二层的布线层厚。
在n沟道型MIS晶体管(Qn)以及p沟道型MIS晶体管(Qn)与第一层Al布线5之间、第一层Al布线5与第二层Al布线7之间、以及第二层Al布线7与第三层Al布线9之间，分别形成有由氧化硅膜等构成的层间绝缘膜4、6、8和将3层布线之间电连接的插塞p1、p2、p3。
上述层间绝缘膜4形成于半导体基板上1P上使得覆盖例如半导体元件，第一层Al布线5形成在该层间绝缘膜4上。第一层Al布线5经由例如形成于层间绝缘膜4的插塞p1而电连接于作为半导体元件的n沟道型MIS晶体管(Qn)的源极区域ns、漏极区域nd、栅电极ng。另外，第一层Al布线5经由形成于层间绝缘膜4的插塞p1电连接于作为半导体元件的p沟道型MIS晶体管(Qp)的源极区域ps、漏极区域pd、栅电极pg。栅电极ng、pg与第一层Al布线5的连接未图示。
第二层Al布线7经由例如形成于层间绝缘膜6的插塞p2电连接于第一层Al布线5。第三层Al布线9经由例如形成于层间绝缘膜8的插塞p3电连接于第二层Al布线7。插塞p1、p2、p3由金属膜、例如W(钨)膜构成。
此外，在用通过化学机械研磨法(CMP法)用以Cu为主体的金属膜形成多层布线(3层布线)的情况下，当然也可以用将布线和插塞一体形成的双镶嵌构造(DualDamascene)法来形成。另外，层间绝缘膜4、6、8由氧化硅膜(SiO2)构成，但是当然也可以用含碳的氧化硅膜(SiOC膜)、含氮和碳的氧化硅膜(SiCON膜)、含氟的氧化硅膜(SiOF膜)的单层膜或层叠层构成。
在多层布线的最上层的布线层即上述第三层Al布线9的上部，作为最终钝化膜，形成有例如氧化硅膜、氮化硅膜等单层膜、或由2层这样的膜构成的表面保护膜(保护膜、绝缘膜)10。而且，在形成于该表面保护膜10的焊盘开口(开口)10a的底部露出的最上层的布线层即第三层Al布线9，构成Al焊盘即焊盘电极(电极焊盘、第一电极焊盘)9a。
上述第三层Al布线9不限于焊盘电极9a，可构成例如与焊盘电极9a形成为一体的布线、不连接于焊盘电极9a的布线等。不连接于焊盘电极9a的布线，用作将半导体元件之间或电路之间电连接而构成半导体集成电路的布线。
在上述表面保护膜10之上，在焊盘开口10a的上方形成有作为具有开口11a的绝缘膜的基底绝缘膜(有机保护膜、绝缘膜)11。另外，在基底绝缘膜11之上，形成有穿过基底绝缘膜11的开口11a、以及表面保护膜10的焊盘开口10a电连接于焊盘电极9a的再布线RM。开口11a比焊盘开口10a大，在焊盘开口10a的全周，规定焊盘开口10a的表面保护膜10的上表面(表面)从开口11a露出。再布线RM形成在焊盘开口10a以及开口11a的内部以完全填埋焊盘开口10a以及开口11a，进一步在基底绝缘膜11之上延伸。
基底金属膜UM介于焊盘电极9a与再布线RM之间。基底金属膜UM与焊盘电极9a接触并电连接，在表面保护膜10的焊盘开口10a以及基底绝缘膜11的开口11a沿表面保护膜10的侧面(侧壁)以及上表面还有基底绝缘膜11的侧面(侧壁)形成，进一步在基底绝缘膜11的上表面延伸。基底金属膜UM具有上表面和下表面，上表面与再布线RM接触，下表面与焊盘电极9a、表面保护膜10以及基底绝缘膜11接触。基底金属膜UM用3层构造的基底屏蔽膜构成，从焊盘电极9a侧起由第一基底屏蔽膜UMl、第二基底屏蔽膜UM2以及第三基底屏蔽膜UM3构成，后文也将记述。因此，所谓基底金属膜UM的上表面意味着第三基底屏蔽膜UM3的上表面，所谓下表面意味着第一基底屏蔽膜UMl的下表面。第一基底屏蔽膜UMl、第二基底屏蔽膜UM2以及第三基底屏蔽膜UM3例如依次由钛(Ti)膜、氮化钛(TiN)膜以及钛(Ti)膜构成，这些膜的膜厚依次设为10nm、50nm以及10nm。该膜厚为基底绝缘膜11的上表面上的膜厚。
另外，再布线RM具有上表面、下表面以及侧面，再布线RM的下表面与基底金属膜UM的上表面接触。再布线RM是以铜(Cu)为主成分的铜膜，用种子膜RMl与镀敷膜RM2的层叠构造构成。因此，所谓再布线RM的下表面意味着种子膜RMl的下表面，所谓上表面意味着镀敷膜RM2的上表面。另外，所谓再布线RM的侧面(侧壁)意味着种子膜RMl与镀敷膜RM2的层叠构造的侧面(侧壁)。种子膜RMl以及镀敷膜RM2的膜厚分别为250nm以及6μm。附带提一下，第三层AI布线9的膜厚为400nm～600nm，所以再布线RM为第三层Al布线9，若换言之则为具有形成有焊盘电极9a的布线9的10倍以上的膜厚的低电阻布线。也就是，再布线RM的膜厚比形成有焊盘电极9a的布线9的膜厚厚。优选是再布线RM的膜厚为形成有焊盘电极9a的布线9的膜厚的10倍以上。
形成有覆盖金属膜CM，使得其与再布线RM的上表面以及侧面接触以完全覆盖再布线RM。覆盖金属膜CM覆盖再布线RM的整个上表面以及整个侧面。覆盖金属膜CM完全覆盖构成再布线RM的种子膜RMl的侧面(侧壁)以及镀敷膜RM2的侧面(侧壁)。覆盖金属膜CM具有上表面和下表面，覆盖金属膜CM的下表面与再布线RM的上表面以及再布线RM的侧面接触，在再布线RM的外侧区域(未形成再布线RM的区域)，与基底金属膜UM的上表面直接接触。
基底金属膜UM以及覆盖金属膜CM，具有从再布线RM的侧面(严格而言是再布线RM的侧面的下端部分)向再布线RM的外侧区域(未形成再布线RM的区域)伸出的伸出部PP，在伸出部PP，基底金属膜UM的上表面与覆盖金属膜CM的下表面直接接触。另外，伸出部PP的伸出量S3比在再布线RM的侧面(侧壁)上形成的覆盖金属膜CM的膜厚大，例如为2.5μm。也就是，俯视图中，作为伸出部PP的顶端的基底金属膜UM以及覆盖金属膜CM的端部，与在再布线RM的侧面(侧壁)上形成的覆盖金属膜CM相比更靠再布线RM的外侧。另外，伸出部PP形成为俯视图中遍及再布线RM的全周。伸出量S3为伸出部PP的宽度，意味着再布线RM的外侧区域中从再布线RM的端部至基底金属膜UM或覆盖金属膜CM的端部的距离。
覆盖金属膜CM由第一覆盖屏蔽膜CMl以及第二覆盖屏蔽膜CM2的层叠构造构成，第一覆盖屏蔽膜CM1的下表面与再布线RM的上表面以及侧面接触，进一步，与基底金属膜UM的上表面(正确的是第三基底屏蔽膜UM3的上表面)接触，后文也将记述。覆盖金属膜CM的下表面意味着第一覆盖屏蔽膜CMl的下表面，上表面意味着第二覆盖屏蔽膜CM2的上表面。第一覆盖屏蔽膜CMl由钛(Ti)膜构成，其膜厚为50nm，第二覆盖屏蔽膜CM2有钯(Pd)膜构成，其膜厚为175nm。该膜厚为再布线RM的上表面上的膜厚。
另外，通过将构成基底金属膜UM的第三基底屏蔽膜UM3和构成覆盖金属膜CM的第一覆盖屏蔽膜CMl设为由同一材质形成的膜(具体为钛(Ti)膜)，从而在伸出部PP能够使基底金属膜UM与覆盖金属膜CM的粘接性牢固，减低构成再布线RM的铜的移动(扩散)。
另外，在伸出部PP，成为在基底金属膜UM上层叠有覆盖金属膜CM的构造，所以在再布线RM的外侧区域的伸出部PP基底金属膜UM的膜厚与覆盖金属膜CM的膜厚之和，比被再布线RM和基底绝缘膜11夹着的基底金属膜UM的膜厚厚。另外，在再布线RM的外侧区域的伸出部PP处的基底金属膜UM的膜厚与第一覆盖屏蔽膜CMl的膜厚之和，比被再布线RM和基底绝缘膜11夹着的基底金属膜UM的膜厚厚。
形成有保护膜12使得其整体覆盖再布线RM。保护膜12具有将再布线RM的上表面(正确的是覆盖金属膜CM的上表面、第二覆盖屏蔽膜CM2的上表面)部分露出的开口12a，再布线RM的露出部分成为外部焊盘电极18。
在此，基底绝缘膜11以及保护膜12均可以使用有机膜、例如聚酰亚胺系树脂、苯并环丁烯系树脂、丙烯酸系树脂、环氧系树脂、硅系树脂等。
此外，基底金属膜UM以及覆盖金属膜CM防止构成再布线RM的铜(Cu)膜变为铜离子而向外部移动(扩散)，由不同于再布线RM的材料(其他材料)构成。另外，基底金属膜UM以及覆盖金属膜CM不含铜(Cu)膜。
另外，以信号输入输出用的再布线RM为例进行了说明，但是电源供给用的再布线RMV以及将电路之间或元件之间连接起来的再布线RMS也是与再布线RM同样的构造。
＜半导体器件的特征＞
以下，说明本实施方式1的半导体器件的主要特征。
由铜膜构成的再布线RM被覆盖再布线RM的下表面且由不同于再布线RM的材料构成的基底金属膜UM和覆盖再布线RM的上表面以及侧面且由不同于再布线RM的材料构成的覆盖金属膜CM完全包围。而且，在再布线RM的外侧区域，基底金属膜UM和覆盖金属膜CM具有伸出部PP,在伸出部PP基底金属膜UM与覆盖金属膜CM直接接触。通过这样的构造，即使在相邻的再布线RM之间施加了电场，也能够防止由于构成再布线RM的铜向再布线RM的外侧区域移动(扩散)而发生相邻的再布线RM之间的耐压劣化或短路。另外，能够防止构成基底绝缘膜11或保护膜12的聚酰亚胺膜所含的水分、卤素离子等进入由铜膜构成的再布线RM中，所以能够防止铜膜氧化，能够防止相邻的再布线RM之间的耐压劣化或短路。
上述伸出部的伸出量比覆盖再布线RM的侧面的覆盖金属膜LCM的膜厚大。另外，在伸出量由于第二图案相对于第一图案的偏离而减少了的情况下，减少了的伸出量也比覆盖再布线RM的侧面的覆盖金属膜CM的膜厚大，所以即使在有制造偏差的情况下，也能够防止相邻再布线RM之间的耐压劣化或短路。能够防止构成再布线RM的铜膜的氧化。
另外，将成为基底金属膜UM的上表面的基底屏蔽膜和成为覆盖金属膜的下表面的覆盖屏蔽膜设为由同一材质构成的膜。因此，能够在伸出部提高基底金属膜UM与覆盖金属膜CM的粘接性，能够充分防止构成再布线RM的铜向再布线RM的外侧区域移动(扩散)，所以能够防止相邻的再布线RM之间的耐压劣化或短路、还有再布线RM的氧化。
另外，伸出部PP形成为在俯视图中遍及再布线RM的全周，所以能够在所有方向上防止与相邻的再布线RM之间的耐压劣化或短路还有再布线的氧化。
在俯视图中，用具有比第一俯视图案P1(其具有由铜膜构成的再布线RM)大的第二俯视图案P2的基底金属膜UM与覆盖金属膜CM将再布线RM完全包入其中，在再布线RM的外侧区域，基底金属膜UM的上表面与覆盖金属膜CM的下表面直接接触。通过该构造，即使相邻的再布线RM之间被施加了高电场，也能够防止再布线RM的氧化，防止相邻的再布线RM之间的耐压劣化或短路。另外，即使构成再布线RM的铜膜氧化而产生了铜离子，也能够防止铜离子向再布线RM的外侧移动(扩散)。
另外，在第一俯视图案P1的全周，第二俯视图案P2比第一俯视图案P1大，所以能够在所有方向上防止与相邻的再布线RM之间的耐压劣化或短路。
＜半导体器件的制造方法＞
接下来，关于本实施方式1的半导体器件的制造方法进行说明，以作为本实施方式1的特征的再布线的制造方法为中心进行说明。再布线的制造方法与图4所示的截面相对应。
图5～图13是本实施方式1的半导体器件的制造工序中的剖视图。
图5示出准备形成有多层布线层和焊盘电极的半导体基板的工序。在半导体基板1P形成了p沟道型MIS晶体管(Qp)以及n沟道型MIS晶体管(Qn)后，形成有由多层布线层构成的布线。具体而言，如图4中说明的那样，形成有3层布线层(第一层Al布线5、第二层Al布线7、第三层Al布线9)。而且，在第三层Al布线9的上部形成有表面保护膜10，表面保护膜10具有焊盘开口10a，作为最上层布线层的第三层Al布线9的从焊盘开口10a露出的部分，成为焊盘电极9a。图5所示的截面构造与图4中说明了的截面构造相同。
图6示出基底绝缘膜11、基底金属膜UM以及种子膜RMl的形成工序。首先，在表面保护膜10上形成基底绝缘膜11，作为基底绝缘膜11使用感光性聚酰亚胺树脂。在表面保护膜10上涂敷感光性聚酰亚胺，进行曝光使焊盘开口10a以及焊盘电极9a露出后，进行固化(cure)使其固化。也就是，形成具有比焊盘开口10a以及焊盘电极9a大的开口11a的基底绝缘膜11。
接下来，形成(堆积)经由开口11a、焊盘开口10a电连接于焊盘电极9a的基底金属膜UM以及种子膜RMl。构成基底金属膜UM的第一基底屏蔽膜UMl、第二基底屏蔽膜UM2以及第三基底屏蔽膜UM3，适于依次按5～50nm的膜厚形成钛(Ti)膜、按10～100nm的膜厚形成氮化钛(TiN)膜、按5～50nm的膜厚形成钛(Ti)膜。在此，作为一例将钛(Ti)膜设为10nm、将氮化钛(TiN)膜设为50nm将钛(Ti)膜设为10nm。该第一基底屏蔽膜UMl、第二基底屏蔽膜UM2以及第三基底屏蔽膜UM3例如通过溅射法形成。接着，利用溅射法在第三基底屏蔽膜UM3上形成由铜(Cu)膜构成的种子膜RMl。种子膜RMl设为250nm左右的膜厚。
图7示出再布线RM的形成工序的镀敷工序。在种子膜RM1之上，形成露出再布线RM的形成区域且覆盖不形成再布线RM的区域的抗蚀剂掩膜(抗蚀剂图案)PR1。也就是，抗蚀剂掩膜PR1成为第一俯视图案P1的反转图案，具有与第一俯视图案P1相对应的开口。接下来，将基底金属膜UM以及种子膜RMl作为种子层，通过电解(电)镀敷法选择性地在从抗蚀剂掩膜PR1露出的区域的种子膜RMl上形成由铜(Cu)膜构成的镀敷膜RM2。镀敷膜RM2的膜厚例如设为约6μm。镀敷膜RM2的膜厚设为2μm～10μm的范围即可，若镀敷膜RM2的膜厚过薄则再布线RM的电阻变高，所以应该设为能满足器件要求的电阻值的膜厚，一般来说一定程度的膜厚是必需的。但是，若过厚则晶片的反翘变大，用之后的光刻蚀、加工装置而发生输送错误，加工变得困难，发生制造成本增加、生产率降低的弊端。此外，例如，基底金属膜UM等在图案化前后标注同样的符号。通过该工序，形成具有第一俯视图案P1的镀敷膜RM2。
图8示出作为再布线RM的形成工序的种子膜RMl的去除(加工)工序。在镀敷膜RM2形成后，去除抗蚀剂掩膜PR1。接下来，通过去除从镀敷膜RM2露出的区域的种子膜RMl，从而在镀敷膜RM2之下剩余具有与镀敷膜RM2相同的俯视图案的图案化后的种子膜RMl。通过该工序，形成具有第一俯视图案P1并由种子膜RMl与镀敷膜RM2的层叠构造构成的再布线RM。
此时，从镀敷膜RM2露出的区域(若换言之则为再布线RM的外侧区域)的基底金属膜UM，未被去除而是保留下来，这很重要。其中，重要的是基底金属膜UM保留在从镀敷膜RM2露出的区域，例如，也可以通过蚀刻将从镀敷膜RM2露出的区域的基底金属膜UM按膜厚的一半左右的量去除。也就是，也可以将从镀敷膜RM2露出的区域的基底金属膜UM的膜厚设为用镀敷膜RM2覆盖的区域的基底金属膜UM的膜厚的一半左右。通过使从镀敷膜RM2露出的区域的基底金属膜UM的膜厚变薄，能够防止基底金属膜UM从基底绝缘膜11剥离。通过降低基底金属膜UM的膜厚，能够得到能够降低基底金属膜UM所具有的应力以减少其从基底绝缘膜11剥离的情况这一效果。在此，蚀刻设为以镀敷膜RM2或种子膜RM1为硬掩膜并包含氯系气体的干式蚀刻。
图9示出形成覆盖金属膜CM的工序的一部分。形成(堆积)覆盖金属膜CM使得其完全覆盖再布线RM的上表面以及侧面。被图案化前的覆盖金属膜CM称为覆盖金属材料膜。覆盖金属膜CM由多层覆盖屏蔽膜构成。为了形成覆盖金属膜CM，而依次形成第一覆盖屏蔽膜(第一覆盖金属材料膜)CM1、第二覆盖屏蔽膜(第二覆盖金属材料膜)CM2以及第三覆盖屏蔽膜(第三覆盖金属材料膜)CM3。此外，在本实施方式1中，将第三覆盖屏蔽膜CM3也作为覆盖金属膜CM的一部分处理。第一覆盖屏蔽膜CM1、第二覆盖屏蔽膜CM2以及第三覆盖屏蔽膜CM3适于分别按10～200nm的膜厚形成钛(Ti)膜、按10～200nm的膜厚形成钯(Pd)膜、按10～200nm的膜厚形成钛(Ti)膜。在此，作为一例，将下层的钛(Ti)膜设为10nm、将钯(Pd)膜设为50nm、将上层的钛(Ti)膜设为175nm。第一覆盖屏蔽膜CM1，第二覆盖屏蔽膜CM2以及第三覆盖屏蔽膜CM3，为了完全覆盖再布线RM的侧面，可以采用CVD法等保形(conformal)的成膜方法，但不限于此。
在此，通过将与第三基底屏蔽膜UM3接触的第一覆盖屏蔽膜CM1设为与第三基底屏蔽膜UM3的膜同一材质的膜，从而能够在伸出部PP提高第三基底屏蔽膜UM3与第一覆盖屏蔽膜CMl的粘接性。若换言之，则通过使成为层叠构造的基底金属膜UM的上表面的膜与成为层叠构造的覆盖金属膜CM的下表面的膜的材质相同，从而能够在伸出部PP提高基底金属膜UM与覆盖金属膜CM的粘接性，能够防止构成再布线RM的铜离子向外部移动(扩散)，能够防止水分等从基底绝缘膜11或保护膜12侵入。
另外，可以是：在第一覆盖屏蔽膜CMl的成膜前对再布线RM以及基底金属膜UM(特别是第三基底屏蔽膜UM3)的表面实施氢等离子处理，去除再布线RM的上表面以及侧面还有基底金属膜UM的上表面的氧化膜而使其洁净化，提高基底金属膜UM与覆盖金属膜CM的粘接性。
接下来，如图9所示，在第三覆盖屏蔽膜CM3上形成抗蚀剂掩膜PR2。抗蚀剂掩膜PR2与第二俯视图案P2相对应，成为在俯视图中覆盖再布线RM以及再布线RM周围的伸出部PP并将此外部分露出的图案。
图10示出相继于图9的形成覆盖金属膜CM的工序的一部分工序。通过干式蚀刻或湿式蚀刻将从抗蚀剂掩膜PR2露出的区域的第三覆盖屏蔽膜CM3去除，形成具有第二俯视图案P2的第三覆盖屏蔽膜CM3。由钛(Ti)膜构成的第三覆盖屏蔽膜CM3使用氨过氧化氢溶液(アンモニア過水溶液)进行湿式蚀刻。也就是，使用抗蚀剂掩膜PR2对第三覆盖屏蔽膜CM3进行图案化。
接下来，去除抗蚀剂掩膜PR2。接着，将图案化后的由钛(Ti)膜构成的第三覆盖屏蔽膜CM3作为硬掩膜而对第二覆盖屏蔽膜CM2进行蚀刻，形成具有第二俯视图案P2的第二覆盖屏蔽膜CM2。由钯(Pd)膜构成的第二覆盖屏蔽膜CM2，使用碘化钾溶液进行湿式蚀刻，但也可以用干式蚀刻法进行蚀刻。也就是，将第三覆盖屏蔽膜CM3作为掩膜，对第二覆盖屏蔽膜CM2进行图案化(蚀刻)。
即使对第三覆盖屏蔽膜CM3以及第二覆盖屏蔽膜CM2实施了湿式蚀刻，在作为再布线RM的外侧区域的伸出部PP存在有基底金属膜UM，在伸出部PP覆盖金属膜CM与基底金属膜UM直接接触，所以蚀刻液不会浸入再布线RM。
图11示出相继于图10的形成覆盖金属膜CM的工序的一部分以及基底金属膜UM的加工工序。进行蚀刻将第三覆盖屏蔽膜CM3以及从第二覆盖屏蔽膜CM2露出的区域的第一覆盖屏蔽膜CM1和基底金属膜UM去除，使基底绝缘膜11的上表面露出。用钛(Ti)膜以及氮化钛(TiN)膜形成了第一覆盖屏蔽膜CMl以及基底金属膜UM，所以，能够通过使用例如氨过氧化氢溶液的湿式蚀刻将第一覆盖屏蔽膜CMl以及基底金属膜UM去除以形成具有第二俯视图案P2的第一覆盖屏蔽膜CMl以及基底金属膜UM。此时，用钛(Ti)膜形成的第三覆盖屏蔽膜CM3也同时被去除，第二覆盖屏蔽膜CM2的上表面露出。通过设定第三覆盖屏蔽膜CM3的膜厚使得其蚀刻时间与第一覆盖屏蔽膜CMl以及基底金属膜UM的时刻时间大致相同，从而能够降低第一覆盖屏蔽膜CMl以及基底金属膜UM相对于第二覆盖屏蔽膜CM2的端部的侧向蚀刻。
经过上述工序，覆盖相邻的再布线RM的上表面以及侧面覆う覆盖金属膜CM与同下表面接触的基底金属膜UM分离开，形成具有相同的第二俯视图案P2的覆盖金属膜CM和基底金属膜UM。在此，所谓“相同”也包括由上述侧向蚀刻导致的尺寸差异的情况。
即使对第三覆盖屏蔽膜CM3、第一覆盖屏蔽膜CMl以及基底金属膜UM实施了湿式蚀刻，在作为再布线RM的外侧区域的伸出部PP存在有基底金属膜UM，在伸出部PP覆盖金属膜CM与基底金属膜UM直接接触，所以蚀刻液不会浸入再布线RM。
图12示出保护膜12的形成工序。形成覆盖再布线RM的上表面以及侧面并具有将在再布线RM的上表面设置的外部焊盘电极18露出的开口12a的保护膜12。保护膜12比再布线RM的膜厚厚，在相邻的再布线RM之间的区域与基底绝缘膜11的上表面接触。作为保护膜12，使用例如感光性聚酰亚胺树脂。在再布线RM上涂敷感光性聚酰亚胺，进行曝光而形成使外部焊盘电极18露出的开口12a，之后进行固化使之固化。
图13示出半导体芯片1A的封装工序。上述工序之后，将半导体芯片1A搭载到晶片焊盘部(diepad)25D上并用线27将再布线RM与引线25L连接，之后用封固体(封固树脂)26将引线25L的一部分(内引线部)、晶片焊盘部25D、半导体芯片1A以及线27封固，从而完成本实施方式1的半导体器件(半导体集成电路装置)。
如图13所示，具有多条再布线RM的半导体芯片1A被搭载于晶片焊盘部25D，通过线27电连接于多个引线25L。引线25L的一部分(内引线部)、晶片焊盘部25D、半导体芯片1A以及线27由例如热固性环氧树脂等封固体(封固树脂)26封固。另外，封固体26中，除环氧树脂之外还含有氧化硅(SiO2)等填料。引线25具有从被封固体26覆盖的内引线部延伸到封固体26外侧的外引线部。
线27的一端连接于图4或图12所示的在半导体芯片1A的再布线RM的上表面所形成的外部焊盘电极18，另一端连接于引线25L的内引线部。晶片焊盘部25D以及多个引线25L例如由铜(Cu)或42号合金(铁镍合金)构成，线27由铜(Cu)构成。
在外部焊盘电极18的表面露出由钯(Pd)膜构成的第二覆盖屏蔽膜CM2，由铜构成的线27键合于由钯(Pd)膜构成的第二覆盖屏蔽膜CM2，所以能够成为稳定且具有足够结合强度的接合，能够成为共同(share)强度高的高可靠性的键合。
此外，作为线27，也可以使用在表面覆盖有钯(Pd)的铜线(Pd涂层Cu线)、金线(Au线)。
作为第一覆盖屏蔽膜CMl用了钛(Ti)膜，但是也可以是以Ni、Mo、W、Co、Ru、Ta等为主成分的合金、这些金属的层叠膜。另外，作为第三基底屏蔽膜UM3用了钛(Ti)膜，但是也可以是以Ni、Mo、W、Co、Ru、Ta等金属、其氮化物、碳化物等以这些金属为主成分的合金、这些金属的层叠膜。
＜半导体器件的制造方法的特征＞
以下，对本实施方式1的半导体器件的制造方法的主要特征进行说明。
如利用图10以及图11说明了的那样，在第二覆盖屏蔽膜CM2的蚀刻工序还有第一覆盖屏蔽膜CMl以及第三覆盖屏蔽膜CM3的蚀刻工序中，基底金属膜UM从再布线RM下连续延伸到作为再布线RM的外侧区域的伸出部PP。另外，基底金属膜UM存在于在再布线RM的侧面(侧壁)上所形成的覆盖金属膜CM与基底绝缘膜11之间。因此，在上述两个蚀刻工序中，能够防止形成再布线RM的铜(Cu)膜剥离这一不良情况发生。接下来，对于其效果进行说明。
图18和图19是作为本实施方式1的比较例的半导体器件的制造工序中的剖视图。
图18示出相继于利用图8说明了的种子膜RMl的去除工序而去除了从镀敷膜RM2露出的区域的基底金属膜UM的状态。不同于上述本实施方式1的制造方法，为了在去除种子膜RMl后，将从镀敷膜RM2或种子膜RMl露出的区域的基底金属膜UM完全去除，必需在基底金属膜UM的蚀刻工序中进行过量蚀刻。也就是，如图18所示发生基底金属膜UM的端部从再布线RM的端部后退的侧向蚀刻，再布线RM成为从基底金属膜UM的端部以帽檐状拱出的构造。
接下来，如图19所示将覆盖金属膜CM堆积到再布线RM的上表面以及侧面上，但通过本申请发明人的研究，判明了：在图19的用虚线Y包围的部分发生被称为“断头(段切れ)”的覆盖金属膜CM的不连续部分。另外，判明：该断头是由于上述基底金属膜UM的侧向蚀刻而发生的，以及在覆盖金属膜CM的蚀刻工序中，蚀刻液从断头部浸入再布线RM或再布线RM下的基底金属膜UM，再布线RM的一部分会剥离。
在比较例中，在除去种子膜RM1后，连续地将从镀敷膜RM2露出的区域的基底金属膜UM完全去除。但是，在本实施方式1中，金属膜UM残留至将再布线RM的外侧区域的覆盖金属膜CM去除的阶段，相继于覆盖金属膜CM的去除(也可以是同一工序)，将再布线RM的外侧区域的基底金属膜UM去除，所以能够防止上述断头，能够防止再布线RM的剥离。
另外，由钯(Pd)膜构成的第二覆盖屏蔽膜CM2在外部焊盘电极18的表面露出，由铜构成的线27键合于由钯(Pd)膜构成的第二覆盖屏蔽膜CM2，所以能够进行稳定且具有足够结合强度的接合。
＜变形例1＞
图14是作为本实施方式1的变形例1的半导体器件的制造工序中的剖视图。
在半导体芯片1B的制造方法中，在利用图8说明了的种子膜RMl的去除工序和利用图9说明了的覆盖金属膜CM的形成工序之间，追加使再布线RM的侧面(侧壁)成为正锥形的工序。具体而言，通过对再布线RM实施氩(Ar)溅射蚀刻，能够得到剖视侧面成为正锥形的梯形形状的再布线RMa。所谓梯形形状也可以说是再布线RMa的下表面比上表面宽的形状、或者剖视下表面的宽度比上表面的宽度大的形状。另外，再布线RMa成为种子膜RMla与镀敷膜RM2a的层叠构造，种子膜RMla与镀敷膜RM2a的侧面成为连续的正锥形。
在利用图7说明了的电解镀敷法形成了镀敷膜RM2的情况下，抗蚀剂掩膜PR1的侧面成为正锥形，所以镀敷膜RM2侧侧面成为倒锥形，镀敷膜RM2的剖视形状成为倒梯形形状。通过本申请发明人的研究，判明了：在侧面为倒锥形的情况下，形成为覆盖再布线RM的侧面的覆盖金属膜CM的覆盖性降低，成为伴有不连续部或针孔的覆盖金属膜CM。因此，在覆盖金属膜CM的湿式蚀刻工序中蚀刻液浸入再布线RM，会发生再布线RM的侧面被蚀刻的(异常蚀刻)现象。
通过使再布线RM的侧面成为正锥形，从而能够防止覆盖金属膜CM的不连续部或针孔的发生，能够防止再布线RM的异常蚀刻。
在上述工序之后，粘接进行实施方式1的覆盖金属膜CM的形成工序。
<变形例2>
图15是作为本实施方式1的变形例2的半导体器件的制造工序中的剖视图。
在半导体芯片1C的制造方法中，在利用图8说明了的种子膜RMl的去除工序与利用图9说明了的覆盖金属膜CM的形成工序之间，追加对再布线RM的肩部或整个侧面倒圆角的工序。具体而言，通过对再布线RM实施回流焊(reflow)(热处理)，能够成为肩部带圆角的再布线RMb。通过例如氢气(H2)等离子处理、在氢气(H2)气氛中在300℃～450℃左右的温度下进行退火从而使再布线RM的铜膜表面的氧化膜还原，在此基础上，在300℃～450℃下进行退火对铜膜进行回流焊。另外，再布线RMb成为种子膜RMlb与镀敷膜RM2b的层叠构造。
再布线RM的肩部变圆、侧面变得平滑，从而能够提高覆盖金属膜CM的覆盖性，防止由于覆盖金属膜CM的不连续部或针孔引发的再布线RM的异常蚀刻。
在上述工序之后，粘接进行实施方式1的覆盖金属膜CM的形成工序。
＜变形例3＞
图16是作为本实施方式1的变形例3的半导体器件的制造工序中的剖视图。
图16示出作为图4所示的半导体芯片1A的变形例的半导体芯片1D，不同于半导体芯片1A之处是在表面保护膜10上不隔着基底绝缘膜11就配置有再布线RM。基底金属膜UM与焊盘电极9a接触而电连接，在表面保护膜10的焊盘开口10a、表面保护膜10的侧壁以及上表面延伸。基底金属膜UM的下表面与表面保护膜10的上表面接触。与再布线RM的下表面接触的基底金属膜UM以及覆盖金属膜CM与实施方式1相同。另外，其他构造、制造方法也与实施方式1相同。
通过设为再布线RM的下表面用基底金属膜UM覆盖、上表面以及侧面用覆盖金属膜CM完全覆盖、基底金属膜UM与覆盖金属膜CM在伸出部PP直接接触的构造，能够防止构成再布线RM的铜成为铜离子向外部移动(扩散)。另外，能够防止构成再布线RM的铜膜由于保护膜12或封固体26所含的水分、卤素离子等而氧化。也就是，能够提高相邻再布线RM间的电气可靠性，所以可以省略图4所示的基底绝缘膜11。
在再布线RM以及表面保护膜上设置有由有机膜构成的保护膜12，所以即使如图13所示用含氧化硅的封固体26将半导体芯片1D封固了，也能够防止由于封固体26与表面保护膜10接触引发的表面保护膜10的裂缝。
另外，如上所述，能够提高相邻再布线RM间的电气可靠性，所以不仅基底绝缘膜11也可以省略保护膜12。即使封固体26含有水分、卤素离子，通过设为上述构造也能够防止水分、卤素离子侵入再布线RM中。
＜变形例4＞
图17是作为本实施方式1的变形例4的半导体器件的制造工序中的剖视图。
图17是用图13说明了的封装工序的变形例。在将半导体芯片1A隔着粘接层39搭载于布线基板30上并用线37连接再布线RM与键合指(BondingFinger)32后，用封固体(封固树脂)38封固布线基板30的上表面侧、半导体芯片1A以及线37，从而完成变形例4的半导体器件(半导体集成电路装置)。
如图17所示，关于布线基板30，在由绝缘层构成的核心层31的上表面具有由导体层构成的多键合指32，在下表面具有由导体层构成的多个焊盘33。多个键合指32之间以及多个焊盘33之间，通过由绝缘层构成的固体抗蚀剂35而电绝缘。进一步，键合指32与焊盘33经由形成于核心层31的由导体层构成的过孔内布线34电连接，在焊盘33连接有由钎料构成的凸块电极36。进一步，封固体38由热固化性环氧树脂等构成，含有氧化硅(SiO2)等填料。
线37的一端连接于图4或图16所示的在半导体芯片1A的再布线RM的上表面所形成的外部焊盘电极18。另一端连接于键合指32。线27是铜(Cu)线，但也可以使用表面覆盖有钯(Pd)的铜线(Pd涂层Cu线)、金线(Au线)。
另外，对外部焊盘电极18与键合指32之间用线电连接的例子进行了说明，但也可以在再布线RM的上表面的外部焊盘电极18形成钎料球、用钎料球对外部焊盘电极18与键合指32之间进行电连接。该情况下，也可以使半导体芯片1A形成有再布线RM一侧与布线基板30的上表面侧相对，用钎料球将外部焊盘电极18与键合指32之间连接起来。
此外，也可以取代半导体芯片1A设为半导体芯片1B～1F。
(实施方式2)
实施方式2与实施方式1的半导体器件的制造方法的变形例相对应。
图20以及图21是实施方式2的半导体器件的制造工序中的剖视图。为了与实施方式1的半导体器件区别开，将实施方式2的半导体器件表示为半导体芯片1E。对与实施方式1的制造方法共用的部分标注同样的符号。
接着实施方式1的利用图8说明了的种子膜RMl的去除工序，将从种子膜RMl露出的区域的基底金属膜UM去除。不同于实施方式1的制造方法，为了在去除种子膜RMl后将从种子膜RMl露出的区域的基底金属膜UM完全去除，在基底金属膜UM的蚀刻工序中必需进行过量蚀刻。也就是，如图20所示发生基底金属膜UMa的端部从再布线RM的端部后退的侧向蚀刻，再布线RM成为从基底金属膜UMa的端部帽檐状拱出的构造。也就是，在再布线RM上出现拱出部，在再布线RM与基底绝缘膜11之间出现空间(槽、间隔)。再布线RM是种子膜RMl与镀敷膜RM2的层叠构造，基底金属膜UMa是第一基底屏蔽膜UM1a、第二基底屏蔽膜UM2a以及第三基底屏蔽膜UM3a的层叠构造。
接下来，对再布线RM实施蚀刻，切入再布线RM直至再布线RM的侧面与基底金属膜UMa的侧面一致、或者直至变得比基底金属膜UMa的侧面靠再布线RM的内部侧。也就是，通过蚀刻将上述拱起部去除。这样一来，如图21所示，形成具有与基底金属膜UMa的侧面一致的侧面的再布线RMc。再布线RMc成为种子膜RM1c与镀敷膜RM2c的层叠构造。另外，如上所述，优选是再布线RMc的侧面比基底金属膜UMa的侧面靠再布线RMc的内部侧。
此外，上述对于基底金属膜UM的湿式蚀刻使用例如氨过氧化氢溶液。而且，对于再布线RM的蚀刻可以是湿式蚀刻或干式蚀刻的任一方。
在上述蚀刻工序后，实施实施方式1的覆盖金属膜CM的形成工序以后的工序完成具有半导体芯片1E的半导体器件，但是因为去除了上述拱起部，所以能够防止由于覆盖金属膜CM的断头引发的再布线RMc的剥离。而且，可以形成覆盖金属膜CM的下表面与基底金属膜UM的侧面或上表面接触的构造，所以能够防止构成再布线RMc的铜膜的氧化或铜离子的移动(扩散)。
<变形例5>
変形例5与实施方式2的半导体器件的制造方法的变形例相对应。
图22是作为实施方式2的变形例5的半导体器件的制造工序中的剖视图。为了与实施方式2的半导体器件区別开，将变形例5的半导体器件表示为半导体芯片1F。对与实施方式1或2的制造方法共用的部分标注同样的符号。
在实施方式2中，在利用图20说明了的基底金属膜UM的蚀刻工序后，为了填埋再布线RM的拱出部之下的空间，对再布线RM实施溅射蚀刻。通过对图20所示的再布线RM实施氩(Ar)溅射蚀刻，能够得到如图22所示剖视侧面成为正锥形的梯形形状的再布线RMd。进一步，在氩溅射蚀刻的工序中，能够用再沉淀物(再附着物)13填埋再布线RMc的拱出部与基底绝缘膜11之间。再布线RMd是种子膜RMld与镀敷膜RMld的层叠构造。
在上述溅射蚀刻工序后，实施实施方式1的覆盖金属膜CM的形成工序以后的工序从而完成具有半导体芯片1F的半导体器件、上述空间被填埋，所以能够防止覆盖金属膜CM的断头，能够防止再布线RMd剥离。
以上，基于实施方式详细地对由本发明者实现的发明进行了说明，但是本发明当然不限定于上述实施方式，其可以在不脱离其主旨的范围内进行变更。
例如，在实施方式2也可以取代将拱出部蚀刻去除的作法，而实施变形例2的回流，从而消除再布线RM的拱出部与基底绝缘膜11之间的空间。另外，也可以在实施方式2或变形例5的半导体芯片1E或1F应用变形例4的封装工序。
此外，下面记载上述实施方式所记载的内容的一部分。
【附记1】
一种半导体器件的制造方法，包括：
(a)在半导体基板的主面上形成焊盘电极的工序；
(b)在所述焊盘电极上形成有开口的第一绝缘膜的工序；
(c)在所述第一绝缘膜上形成经由所述开口与所述焊盘电极电连接的基底金属膜的工序；
(d)在所述基底金属膜上形成经由所述基底金属膜与所述焊盘电极电连接的再布线的工序；以及
(e)形成覆盖所述再布线的上表面以及侧面的覆盖金属膜的工序，
所述工序(d)包括：
(d-1)在所述基底金属膜上形成经由所述基底金属膜与所述焊盘电极电连接的所述再布线的工序；
(d-2)对从所述再布线露出的区域的所述基底金属膜进行完全蚀刻的工序；以及
(d-3)之后，对所述再布线进行湿式蚀刻使其后退的工序，
所述工序(e)包括：
(e-1)在所述半导体基板的整个主面上形成覆盖屏蔽膜的工序；以及
(e-2)通过对所述覆盖屏蔽膜进行图案化而形成所述覆盖金属膜的工序。
【附记2】
在上述附记1所记载的半导体器件的制造方法中，
所述再布线由Cu膜构成，所述焊盘电极由Al膜构成。
【附记3】
在上述附记1所记载的半导体器件的制造方法中，
所述再布线的膜厚比所述焊盘电极的膜厚厚，所述焊盘电极在多层布线层中最厚。
【附记4】
一种半导体器件，具有：
半导体基板；
形成在所述半导体基板上的多层布线层；
形成于所述多层布线层的最上层的焊盘电极；
在所述焊盘电极上有开口的绝缘膜；
形成在所述绝缘膜上且具有第一下表面和第一上表面的基底金属膜；
形成于所述基底金属膜的所述第一上表面且具有第二下表面、第二上表面和侧面的再布线；以及
形成为覆盖所述再布线的所述第二上表面以及所述侧面且具有第三下表面和第三上表面的覆盖金属膜，
所述再布线具有第一俯视图案，
所述基底金属膜以及所述覆盖金属膜具有比所述第一俯视图案大的第二俯视图案，
在所述再布线的外侧，所述基底金属膜的所述第一上表面与所述覆盖金属膜的所述第三下表面接触。
【附记5】
在上述附记4所记载的半导体器件中，
在所述第一俯视图案的整个周围，所述第二俯视图案比所述第一俯视图案大，
在所述再布线的外侧，所述基底金属膜的所述第一上表面与所述覆盖金属膜的所述第三下表面接触。
符号说明
CM覆盖金属膜
CMl、CM2、CM3覆盖屏蔽膜
PP伸出部
PR抗蚀剂掩膜
p1、p2、p3插塞
P1第一俯视图案
P2第二俯视图案
Qnn沟道型MIS晶体管
Qpp沟道型MIS晶体管
RM、RMa、RMb、RMc、RMd、RMS、RMV再布线
RMl种子膜
RM2镀敷膜
UM基底金属膜
UMa、UMl、UM2、UM3基底屏蔽膜
1A、1B、1C、1D、1E、1F半导体芯片
1P半导体基板
2Pp型阱
2Nn型阱
3元件分离槽
3a元件分离绝缘膜
4、6、8层间绝缘膜
5、7、9Al布线
9a焊盘电极
10表面保护膜
10a焊盘开口
11基底绝缘膜
11a开口
12保护膜
13再附着物
18外部焊盘电极
25D晶片焊盘部
25L引线
26、38封固体
27、37线
30布线基板
31核心层
32键合指
33焊盘
34过孔内布线
35固体抗蚀剂
36凸起电极
39粘接层

Claims (19)

1.一种半导体器件，具有：
半导体基板；
形成在所述半导体基板上的多层布线层；
形成于所述多层布线层的最上层的焊盘电极；
在所述焊盘电极上有开口的绝缘膜；
形成在所述绝缘膜上的基底金属膜；
形成在所述基底金属膜上的再布线；以及
形成为覆盖所述再布线的上表面以及侧面的覆盖金属膜，
在所述再布线的外侧区域，在形成在所述再布线的侧壁上的所述覆盖金属膜与所述绝缘膜之间，形成有所述基底金属膜，
所述再布线与所述基底金属膜由不同材料形成，
所述再布线与所述覆盖金属膜由不同材料形成，
在所述再布线的外侧区域，所述基底金属膜与所述覆盖金属膜直接接触。
2.根据权利要求1所述的半导体器件，其中，
存在于所述再布线的外侧区域的所述基底金属膜的膜厚与所述覆盖金属膜的膜厚之和，比所述再布线之下的所述基底金属膜的膜厚厚。
3.根据权利要求1所述的半导体器件，其中，
所述覆盖金属膜由包含第一覆盖屏蔽膜、第二覆盖屏蔽膜的层叠膜形成，
所述第一覆盖屏蔽膜是Ti膜，
所述第二覆盖屏蔽膜是Pd膜，
所述基底金属膜是含Ti膜以及TiN膜的层叠膜。
4.根据权利要求1所述的半导体器件，其中，
所述再布线以Cu为主成分而构成，
所述焊盘电极以Al为主成分而构成，
所述再布线的膜厚比所述焊盘电极的膜厚厚。
5.根据权利要求3所述的半导体器件，其中，
在形成在所述再布线上的所述第二覆盖金属膜上有铜线。
6.一种半导体器件的制造方法，包括：
(a)准备半导体基板的工序，所述半导体基板具有多层布线层和形成于所述多层布线层的最上层的焊盘电极；
(b)形成在所述焊盘电极上有第一开口的第一绝缘膜的工序；
(c)在所述第一绝缘膜上形成经由所述第一开口与所述焊盘电极电连接的基底金属膜的工序；
(d)在所述基底金属膜上形成经由所述基底金属膜与所述焊盘电极电连接的再布线的工序；以及
(e)形成覆盖所述再布线的上表面以及侧面的覆盖金属膜的工序，
所述工序(e)包括：
(e-1)在所述半导体基板的主面上形成覆盖金属材料膜的工序；以及
(e-2)通过对所述第一绝缘膜上的所述覆盖金属材料膜进行蚀刻，形成所述覆盖金属膜的工序，
所述工序(e-2)中的所述蚀刻，在所述基底金属膜的一部分存在于所述再布线的外侧区域的状态下实施，
在所述工序(e-2)之后，在所述再布线的外侧区域，所述基底金属膜与所述覆盖金属膜直接接触。
7.根据权利要求6所述的半导体器件的制造方法，其中，
所述再布线与所述基底金属膜由不同材料形成，
所述再布线与所述覆盖金属膜由不同材料形成。
8.根据权利要求6所述的半导体器件的制造方法，其中，
所述覆盖金属膜材料由包含第一覆盖屏蔽膜、第二覆盖屏蔽膜以及第三覆盖屏蔽膜的层叠膜形成，
所述基底金属膜与所述第三覆盖屏蔽膜含同一材料。
9.根据权利要求6所述的半导体器件的制造方法，其中，
所述工序(d)包括：
(d-1)在所述基底金属膜上形成种子膜的工序；
(d-2)在所述种子膜上形成使所述种子膜的一部分露出的抗蚀剂图案的工序；
(d-3)在从所述抗蚀剂图案露出的所述种子膜上通过电镀形成所述再布线的工序；
(d-4)将所述抗蚀剂图案去除的工序；以及
(d-5)将所述再布线的外侧区域的所述种子膜去除的工序，
在所述工序(e)中，
所述覆盖金属膜形成为覆盖所述种子膜的侧面。
10.根据权利要求6所述的半导体器件的制造方法，其中，
所述工序(e-2)包含进行所述基底金属膜的湿式蚀刻的工序。
11.根据权利要求6所述的半导体器件的制造方法，其中，
所述再布线以Cu为主成分而构成，
所述焊盘电极以Al为主成分而构成，
所述再布线的膜厚比所述焊盘电极的膜厚厚。
12.根据权利要求6所述的半导体器件的制造方法，其中，
在所述第一绝缘膜与所述焊盘电极之间形成有第二绝缘膜，
所述第二绝缘膜在所述第一绝缘膜的所述第一开口内具有比所述第一开口小的第二开口。
13.根据权利要求6所述的半导体器件的制造方法，其中，
在所述工序(e)后进一步具有在所述覆盖金属膜上形成具有第三开口的第三绝缘膜的工序，
所述第一绝缘膜与所述第三绝缘膜分别含聚酰亚胺膜。
14.根据权利要求6所述的半导体器件的制造方法，其中，
将铜线连接于所述再布线之上的所述覆盖金属膜。
15.根据权利要求6所述的半导体器件的制造方法，其中，
在所述工序(d)后且在所述工序(e)前，进一步具有将所述基底金属膜的一部分蚀刻的工序。
16.一种半导体器件的制造方法，具有：
(a)准备半导体基板的工序；
(b)在所述半导体基板上形成绝缘膜的工序；
(c)在所述绝缘膜上形成基底金属膜的工序；
(d)在所述基底金属膜上形成再布线的工序；
(e)以覆盖所述再布线的上表面以及侧面的方式，在所述绝缘膜上依次形成第一覆盖屏蔽膜、第二覆盖屏蔽膜以及第三覆盖屏蔽膜的工序；
(f)使用抗蚀剂掩膜，在所述再布线的上表面上以及侧面上保留所述第三覆盖屏蔽膜、同时对在所述绝缘膜上形成的所述第三覆盖屏蔽膜进行图案化的工序；
(g)将所述抗蚀剂掩膜去除的工序；
(h)将图案化后的所述第三覆盖屏蔽膜作为掩膜，对在所述绝缘膜上形成的所述第二覆盖屏蔽膜进行蚀刻的工序；以及
(i)对所述再布线上表面上以及侧面上的所述第三覆盖屏蔽膜进行蚀刻，并且对所述绝缘膜上的所述第一覆盖屏蔽膜以及所述基底金属膜进行蚀刻的工序。
17.根据权利要求16所述的半导体器件的制造方法，其中，
在所述工序(i)后，在所述再布线的外侧区域且为所述绝缘膜上的区域，存在有所述基底金属膜与所述第一覆盖屏蔽膜，
存在于所述再布线的外侧区域的所述基底金属膜的膜厚与所述第一覆盖屏蔽膜的膜厚之和，比所述再布线下的所述基底金属膜的膜厚厚。
18.根据权利要求16所述的半导体器件的制造方法，其中，
所述第一、第二以及第三覆盖屏蔽膜分别为Ti膜，Pd膜以及Ti膜，
所述基底金属膜是含Ti膜、TiN膜以及Ti膜的层叠膜。
19.根据权利要求16所述的半导体器件的制造方法，其中，
在所述(i)工序后，在所述再布线的上表面形成的所述第二覆盖屏蔽膜露出，
在所述(i)工序后，进一步具有(j)工序：在所述第二覆盖屏蔽膜上形成铜线。
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