CN109273483A - 显示基板及其制备方法和显示装置 - Google Patents
显示基板及其制备方法和显示装置 Download PDFInfo
- Publication number
- CN109273483A CN109273483A CN201710584603.4A CN201710584603A CN109273483A CN 109273483 A CN109273483 A CN 109273483A CN 201710584603 A CN201710584603 A CN 201710584603A CN 109273483 A CN109273483 A CN 109273483A
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- Prior art keywords
- metal layer
- layer
- base plate
- pad
- display base
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- 238000002360 preparation method Methods 0.000 title abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 175
- 239000002184 metal Substances 0.000 claims abstract description 175
- 239000004020 conductor Substances 0.000 claims abstract description 39
- 238000005260 corrosion Methods 0.000 claims abstract description 34
- 230000007797 corrosion Effects 0.000 claims abstract description 34
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 40
- 239000010936 titanium Substances 0.000 claims description 40
- 229910052719 titanium Inorganic materials 0.000 claims description 40
- 238000000034 method Methods 0.000 claims description 35
- 229910052782 aluminium Inorganic materials 0.000 claims description 28
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 28
- 239000004411 aluminium Substances 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 17
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 14
- 239000010931 gold Substances 0.000 claims description 14
- 229910052737 gold Inorganic materials 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 239000000853 adhesive Substances 0.000 claims description 10
- 230000001070 adhesive effect Effects 0.000 claims description 10
- 239000004332 silver Substances 0.000 claims description 8
- 229910052709 silver Inorganic materials 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 7
- 239000007769 metal material Substances 0.000 claims description 7
- 239000000203 mixture Substances 0.000 claims description 5
- 229910003437 indium oxide Inorganic materials 0.000 claims description 3
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 3
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims description 3
- 229910001887 tin oxide Inorganic materials 0.000 claims description 3
- 239000002245 particle Substances 0.000 abstract description 10
- 239000010410 layer Substances 0.000 description 308
- 239000010405 anode material Substances 0.000 description 12
- 239000000758 substrate Substances 0.000 description 9
- 238000005530 etching Methods 0.000 description 8
- 238000000059 patterning Methods 0.000 description 8
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 6
- 239000011159 matrix material Substances 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
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- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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Abstract
本公开提供显示基板及其制备方法和显示面板。显示基板包括:显示区;和在所述显示区之外的焊盘区。所述焊盘区包括至少一个焊盘。所述焊盘包括:金属层,所述金属层包括第一金属层和层叠在所述第一金属层上的第二金属层,其中所述第二金属层的抗腐蚀性强于所述第一金属层的抗腐蚀性;以及导电材料层,所述导电材料层覆盖所述金属层的侧表面。本公开可以在不增加工艺步骤和成本的情况下避免使焊盘的第二金属层出现坍塌变成移动的导电颗粒,使不同信号线之间发生短路的问题。
Description
技术领域
本公开涉及有机发光显示技术领域,更具体地,涉及一种显示基板及其制备方法和显示装置。
背景技术
用于显示装置的焊盘通常包括金属层如源/漏极金属层。金属层通常包括第一金属层和在层叠在所述第一金属层上的第二金属层,其中所述第一金属层的抗腐蚀性弱于所述第二金属层的抗腐蚀性。例如,金属层是包括抗腐蚀性较强的金属层、抗腐蚀性较弱的导电金属层和抗腐蚀性较强的金属层的多层结构,例如钛层、铝层和钛层的多层结构。焊盘在经过电极刻蚀工艺之后,会导致抗腐蚀性较弱的第一金属层如铝层出现底切而使得此多层结构很不稳定。例如,抗腐蚀性较强的第二金属层如钛层会在其后的工艺中出现坍塌,变成移动的导电颗粒,会使不同信号线之间发生短路。
为了防止出现上述问题,通常采用像素定义层材料如聚酰亚胺或亚克力对焊盘的边缘进行覆盖。但是,由于像素定义层一般都较厚,为了不影响焊接质量,需要对覆盖焊盘区的像素定义层进行薄化。这样的薄化需要采用半色调掩模进行,然后再沉积导电材料层和进行导电材料层的刻蚀,因此成本增加并且工艺变得复杂。
发明内容
鉴于现有技术中的一个或多个问题,本公开提供了一种显示基板及其制备方法和显示装置,其可以避免使抗腐蚀性较弱的第一金属层如铝层出现底切,从而避免使抗腐蚀性较强的第二金属层如钛层在其后的工艺中出现坍塌变成移动的导电颗粒,使不同信号线之间发生短路的问题。在一些实施例中,本公开的显示基板的制备方法不会增加工艺步骤和成本。
在本公开的一个方面,提供一种显示基板,包括:
显示区;和
在所述显示区之外的焊盘区,
其中所述焊盘区包括至少一个焊盘,所述焊盘包括:
金属层,所述金属层包括第一金属层和层叠在所述第一金属层上的第二金属层,其中所述第二金属层的抗腐蚀性强于所述第一金属层的抗腐蚀性;以及
导电材料层,所述导电材料层覆盖所述金属层的侧表面。
根据本公开的另一个实施方案,所述显示区包括显示电极,其中所述焊盘的所述导电材料层与所述显示区的所述显示电极同层设置。
根据本公开的另一个实施方案,所述显示电极包括阳极,其中所述焊盘的所述导电材料层与所述阳极同层设置。
根据本公开的另一个实施方案,所述显示区还包括源/漏极,其中所述焊盘的所述金属层与所述显示区的所述源/漏极同层设置。根据本公开的另一个实施方案,所述第一金属层包含铝,并且所述第二金属层包含钛。
根据本公开的另一个实施方案,所述金属层还包括第三金属层,其中所述第一金属层层叠在所述第三金属层上,所述第三金属层的抗腐蚀性强于所述第一金属层的抗腐蚀性。
根据本公开的另一个实施方案,所述第一金属层包含铝,以及所述第二金属层和所述第三金属层均包含钛。
根据本公开的另一个实施方案,所述导电材料层是包括透明导电氧化物层、金属材料层和透明导电氧化物层的多层结构。
根据本公开的另一个实施方案,所述透明导电氧化物层包括下列各项组成的组中的任何一项:氧化铟、氧化锡、氧化锡铟、及其任何两种或更多种的混合物。
根据本公开的另一个实施方案,所述金属材料层包含银。
根据本公开的另一个实施方案,所述透明导电氧化物层包含氧化锡铟,并且所述金属材料层包含银。
根据本公开的另一个实施方案,所述焊盘还包括包含金球的异向导电胶,其中所述第二金属层与所述包含金球的异向导电胶接触。
在公开的另一方面,提供一种显示装置,包括上面中任何一项所述的显示基板。
在公开的再一方面,提供一种用于制备显示基板的方法,所述显示基板包括显示区和在所述显示区之外的焊盘区,所述方法包括以下步骤:
在焊盘区形成金属层,所述金属层包括第一金属层和层叠在所述第一金属层上的第二金属层,其中所述第二金属层的抗腐蚀性强于所述第一金属层的抗腐蚀性;
在所述第二金属层上形成导电材料层;
在所述导电材料层上涂布光刻胶;
用掩模覆盖所述金属层的侧表面进行曝光、显影和刻蚀,以保留所述侧表面上的导电材料层;和
去除所述金属层的所述侧表面上的光刻胶。
根据本公开的一个实施方案,所述显示区包括显示电极,以及所述焊盘区的所述导电材料层与所述显示区的所述显示电极同时形成。
根据本公开的另一个实施方案,所述显示电极包括阳极,以及所述焊盘区的所述导电材料层与所述显示区的所述阳极同时形成。
根据本公开的另一个实施方案,所述显示区还包括源/漏极,以及所述焊盘区的所述金属层和所述显示区的所述源/漏极同时形成。
根据本公开的另一个实施方案,所述方法还包括:在将所述金属层的所述侧表面上的所述掩模去除之后,在所述第二金属层上形成包含金球的异向导电胶。
由本公开所述的显示基板及其制备方法和显示装置,可以避免使抗腐蚀性较弱的第一金属层如铝层出现底切,从而避免使抗腐蚀性较强的第二金属层如钛层在其后的工艺中出现坍塌变成移动的导电颗粒,使不同信号线之间发生短路的问题。在一些实施例中,本公开的显示基板制备方法不会增加工艺步骤和成本。
在所述金属层是包括钛层、铝层和钛层的多层结构的情况下,由本公开所述的显示基板及其制备方法和显示装置,可以避免使中间的铝层出现底切,从而避免使上层的钛层在其后的工艺中出现坍塌变成移动的导电颗粒,使不同信号线之间发生短路的问题。
另外,覆盖所述金属层的所述侧表面的导电材料层也属于导电接触区,可以进一步提高所述金属层的导电性。
附图说明
为了更清楚地说明本公开实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本公开的示例性实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是示意性地表示在显示基板的焊盘的金属层在没有保护的情况下经过刻蚀后的剖视图。
图2是示意性地表示用像素定义层材料如聚酰亚胺或亚克力对焊盘的边缘进行覆盖时的显示基板的剖视图。
图3A~3C是示意性地表示根据本公开的一个实施方案,用于制备显示基板的方法的各个工艺步骤后的显示基板的剖视图,其中图3A是涂布光刻胶的步骤之后的剖视图;图3B是曝光、显影和刻蚀的步骤的剖视图;和图3C是去除光刻胶步骤的剖视图。
图4是示意性地表示根据本公开的一个实施方案的显示基板的剖视图。
具体实施方式
下面将结合本公开的具体实施方案,对本公开实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施方案和/或实施例仅仅是本公开一部分实施方案和/或实施例,而不是全部的实施方案和/或实施例。基于本公开中的实施方案和/或实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施方案和/或所有其他实施例,都属于本公开保护的范围。
在本公开中,如果没有具体指明,层或膜可以互换地使用;并且焊盘有时也称作焊垫。术语“第一”、“第二”和“第三”仅用于描述目的,而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此,限定有“第一”、“第二”或“第三”的特征可以明示或者隐含地包括一个或者更多个该特征。
在本公开的一个方面,可以提供一种显示基板。所述显示基板包括:显示区;和在所述显示区之外的焊盘区。所述焊盘区包括至少一个焊盘。所述焊盘包括:金属层和导电材料层。所述金属层包括第一金属层和层叠在所述第一金属层上的第二金属层。所述第二金属层的抗腐蚀性强于所述第一金属层的抗腐蚀性。所述导电材料层覆盖所述金属层的侧表面。
根据本公开的一个实施方案,所述显示区可以包括显示电极。所述焊盘的所述导电材料层与所述显示区的所述显示电极同层设置。
根据本公开的另一个实施方案,所述显示电极包括阳极,其中所述焊盘的所述导电材料层与所述阳极同层设置。
根据本公开的另一个实施方案,所述显示区还包括源/漏极,其中所述焊盘的所述金属层与所述显示区的所述源/漏极同层设置。
以下,为了举例说明本公开,以金属层是与显示基板的源/漏极同层形成的源/漏极金属层并且是包括钛层、铝层和钛层的三层结构;显示电极是阳极;导电材料层是与阳极同层或同一构图工艺形成的阳极材料层;导电材料层和阳极是包含ITO层、银层和ITO层的三层结构为例并且结合附图进行说明,但本公开不限于此。例如,金属层可以是包括铝层和覆盖铝层的钛层的双层结构。再例如,显示电极也可以是阴极,导电材料层也可以选择与阴极相同的材料来同层或同一构图工艺形成。
因此,在以下描述中,金属层有时也称作源/漏极金属层,并且导电材料层有时也称作阳极材料层,显示电极有时也称作阳极。
图1是示意性地表示在显示基板200的焊盘100的金属层在没有保护的情况下经过阳极刻蚀后的剖视图。
如图1所示,显示基板200可以包括焊盘区1000,和在所述焊盘区1000之外的显示区2000。焊盘区1000可以包括至少一个焊盘100。焊盘100可以包括第一基板10、形成在第一基板10上的绝缘层20、在绝缘层20上的金属层30(源/漏极金属层30)。显示区2000可以包括在绝缘层20上的薄膜晶体管(TFT)90和显示电极80如阳极80。TFT 90可以包括栅极91、层间介质层92、有源层93、源极94和漏极96。源极94或漏极96可以与显示电极80如阳极80连接。在图1中,漏极96与阳极80连接。金属层30可以是包括抗腐蚀性较强的第三金属层32、抗腐蚀性较弱的第一金属层34和抗腐蚀性较强的第二金属层36的多层结构,例如第一钛层32、铝层34和第二钛层36的多层结构。第一金属层34位于第三金属层32和第二金属层36之间。焊盘100在经过显示装置的阳极刻蚀之后,会导致中间的第一金属层如铝层34出现底切而使得此多层结构很不稳定。例如,上层的第二金属层36如第二钛层36会在其后的工艺中出现坍塌,变成移动的导电颗粒,会导致不同信号线之间发生短路。
图2是示意性地表示用像素定义层材料如聚酰亚胺或亚克力对焊盘100的边缘进行覆盖时的显示基板200的剖视图。与图1中相同的部件由相同的附图标记表示;并且不再对其详细描述。
为了防止出现结合图1中所述的问题,采用像素定义层材料如聚酰亚胺或亚克力对焊盘100的边缘进行覆盖。但是,由于像素定义层70一般都较厚,为了不影响焊接质量,需要对覆盖焊盘区1000的像素定义层进行薄化,以形成薄化的像素定义层75。这样的薄化需要采用半色调掩模进行,然后再沉积阳极80和进行阳极80刻蚀,因此成本增加并且工艺变得复杂。
图3A~3C是示意性地表示根据本公开的一个实施方案,用于制备显示基板200的方法的各个工艺步骤后的显示基板200的剖视图,其中图3A是涂布光刻胶50的步骤之后的剖视图;图3B是曝光、显影和刻蚀的步骤的剖视图;和图3C是去除光刻胶50步骤的剖视图。与图1和2中相同的部件由相同的附图标记表示;并且不再对其详细描述。
如图3A所示,本公开用于制备显示基板200的方法包括以下步骤:
在焊盘区1000形成金属层30;金属层30包括第一金属层34和层叠在第一金属层34上的第二金属层36,其中第二金属层36的抗腐蚀性强于第一金属层34的抗腐蚀性;
在第二金属层36上形成导电材料层40;和
在导电材料层40上涂布光刻胶50。
如图3B所示,所述方法还可以包括:用掩模覆盖金属层30的侧表面进行曝光、显影和刻蚀,以保留金属层30的侧表面上的阳极材料层40。
如图3C示,所述方法还可以包括:去除金属层30的侧表面上的光刻胶50。
显示区可以包括显示电极80。焊盘区1000的导电材料层40可以与显示区2000的显示电极80同时形成,即采用同一构图工艺形成。在形成显示电极80的同时,也形成了导电材料层40。在包括导电材料层40和显示电极80的整个层上涂布光刻胶50。用掩模覆盖金属层30的侧表面和显示电极80进行曝光、显影和刻蚀,以保留金属层30的侧表面上的阳极材料层40和显示区2000的显示电极80。
显示电极可以包括阳极80。焊盘区1000的导电材料层40与显示区2000的阳极80同时形成,即采用同一构图工艺形成。在形成阳极80的同时,也形成了导电材料层40。在包括导电材料层40和阳极80的整个层上涂布光刻胶50。用掩模覆盖金属层30的侧表面和阳极80进行曝光、显影和刻蚀,以保留金属层30的侧表面上的阳极材料层40和显示区2000的阳极80。
显示区还可以包括源极94/漏极96。焊盘区1000的金属层30和显示区2000的源/漏极同时形成,即采用同一构图工艺形成。
如此,可以避免使第一金属层如铝层34在阳极刻蚀时出现底切。由此,避免了使第二金属层如第二钛层36在其后的工艺中出现坍塌变成移动的导电颗粒,使不同信号线之间发生短路的问题。另外,覆盖金属层30的侧表面的阳极材料层40也属于导电接触区,可以进一步提高金属层30的导电性。
图4是示意性地表示根据本公开的一个实施方案的显示基板200的剖视图。
如图4中所示,本公开的显示基板200可以包括焊盘区1000,和在所述焊盘区1000之外的显示区2000。焊盘区1000可以包括至少一个焊盘100。在图4中,示出了两个焊盘100。焊盘100可以包括第一基板10、形成在第一基板10上的绝缘层20、在绝缘层20上的金属层30(源/漏极金属层30)。显示区2000可以包括在绝缘层20上的TFT 90和显示电极80如阳极80。TFT 90可以包括栅极91、层间介质层92、有源层93、源极94和漏极96。源极94或漏极96可以与显示电极80如阳极80连接。在图4中,漏极96与阳极80连接。金属层30可以是包括抗腐蚀性较强的第三金属层32、抗腐蚀性较弱的第一金属层34和抗腐蚀性较强的第二金属层36的多层结构,例如第一钛层32、铝层34和第二钛层36的多层结构。第一金属层34位于第三金属层32和第二金属层36之间。
虽然在图4中示出了第一钛层32、滤层34和第二钛层36的三层结构,但本领域技术人员应当理解,金属层30也可以是仅包括抗腐蚀性较弱的第一金属层34和抗腐蚀性较强的第二金属层36的双层结构。第二金属层36覆盖第一金属层34。例如,金属层30可以是铝层34和钛层36的双层结构。钛层36覆盖铝层34。
如图4所示,金属层30的侧表面被阳极材料层40覆盖。这样,可以避免使第一金属层如铝层34在阳极刻蚀时出现底切。由此,避免了使第二金属层如第二钛层36在其后的工艺中出现坍塌变成移动的导电颗粒,使不同信号线之间发生短路的问题。另外,覆盖金属层30的侧表面的阳极材料层40也属于导电接触区,可以进一步提高金属层30的导电性。
根据本公开的一个实施方案,金属层30可以是包括第一钛层32、铝层34和第二钛层36的多层结构。铝层34位于第一钛层32和第二钛层36之间。第一钛层32的厚度可以为400至铝层34的厚度可以为4000至第二钛层的厚度可以为400至第一钛层32和第二钛层36的厚度可以相同或不同。
根据本公开的一个实施方案,在金属层30是铝层34和钛层36的双层结构的情况下,钛层36的厚度可以为400至并且铝层34的厚度可以为4000至
根据本公开的另一个实施方案,阳极材料层40可以是包括第一透明导电氧化物层、金属材料层和第二透明导电氧化物层的多层结构。金属材料层位于第一透明导电氧化物层和第二透明导电氧化物层之间。第一透明导电氧化物层的厚度可以为50至金属材料层的厚度可以为800至第二透明导电氧化物层的厚度可以为50至第一透明导电氧化物层和第二透明导电氧化物层的厚度可以相同或不同。
根据本公开的另一个实施方案,第一和第二透明导电氧化物层中的透明导电氧化物可以相同或不同,并且第一和第二透明导电氧化物层可以包括由下列各项组成的组中的任何一项:氧化铟、氧化锡、氧化锡铟、及其任何两种或更多种的混合物。
根据本公开的另一个实施方案,金属材料层可以包括银,例如是银。例如,阳极材料层可以包括第一氧化锡铟(ITO)层、银层和第二氧化锡铟(ITO)层。银层位于第一ITO层和第二ITO层之间。
根据本公开的另一个实施方案,显示基板200可以是有源矩阵发光基板或无源矩阵发光基板。
根据本公开的另一个实施方案,焊盘100还可以包括在第二金属层36上的包含金球65的异向导电胶60。第二金属层36与包含金球65的异向导电胶60接触。
本公开的焊盘可以用于连接集成电路板或柔性印刷电路板,例如与集成电路板或柔性印刷电路板的焊盘150电连接。
根据本公开的另一个实施方案,显示区包括显示电极80。焊盘100的导电材料层40与显示区的显示电极80同层设置或同一构图工艺形成。如此,可以在不增加工艺步骤和成本的情况下形成焊盘100的导电材料层40。
根据本公开的另一个实施方案,显示电极包括阳极80。焊盘的阳极材料层40与阳极80同层设置或同一构图工艺形成。如此,可以在不增加工艺步骤和成本的情况下形成焊盘100的阳极材料层40。
根据本公开的另一个实施方案,显示区还包括源极94/漏极96。焊盘100的金属层30与显示区的源极94/漏极96同层设置或同一构图工艺形成。如此,可以在不增加工艺步骤和成本的情况下形成焊盘100的金属层30。
根据本公开的另一个实施方案,用于制备显示基板200的方法还可以包括:在将金属层30的侧表面上的掩模去除之后,在第二金属层36上形成包含金球65的异向导电胶60。
本公开的焊盘100可以通过异向导电胶60连接集成电路板或柔性印刷电路板,例如与集成电路板或柔性印刷电路板的焊盘150电连接。
本公开的显示装置可以包括本公开的显示基板。
本公开的显示基板可以包括有源矩阵发光基板或无源矩阵发光基板。本发明的显示装置可以包括有源矩阵发光显示装置和无源矩阵发光显示装置。
由本公开的显示基板200及其制备方法和显示装置,可以在不增加工艺步骤和成本的情况下避免使中间的第一金属层如铝层34出现底切。由此,避免了使上层的第二金属层如第二钛层36在其后的工艺中出现坍塌变成移动的导电颗粒,使不同信号线之间发生短路的问题。
在金属层30是包括第一钛层32、铝层34和第二钛层36的多层结构的情况下,由本公开的显示基板200及其制备方法和显示装置,可以避免使中间的铝层34出现底切。由此,避免了使第二钛层36在其后的工艺中出现坍塌变成移动的导电颗粒,使不同信号线之间发生短路的问题。
另外,覆盖金属层30的侧表面的导电材料层40如阳极导电材料40也属于导电接触区,可以进一步提高金属层30的导电性。
显然,本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开的精神和范围。这样,倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内,则本公开也意图包含这些改动和变型在内。
Claims (18)
1.一种显示基板,包括:
显示区;和
在所述显示区之外的焊盘区,
其中所述焊盘区包括至少一个焊盘,所述焊盘包括:
金属层,所述金属层包括第一金属层和层叠在所述第一金属层上的第二金属层,其中所述第二金属层的抗腐蚀性强于所述第一金属层的抗腐蚀性;以及
导电材料层,所述导电材料层覆盖所述金属层的侧表面。
2.根据权利要求1所述的显示基板,其中所述显示区包括显示电极,其中所述焊盘的所述导电材料层与所述显示区的所述显示电极同层设置。
3.根据权利要求2所述的显示基板,其中所述显示电极包括阳极,其中所述焊盘的所述导电材料层与所述阳极同层设置。
4.根据权利要求1所述的显示基板,其中所述显示区还包括源/漏极,其中所述焊盘的所述金属层与所述显示区的所述源/漏极同层设置。
5.根据权利要求1所述的显示基板,其中所述第一金属层包含铝,并且所述第二金属层包含钛。
6.根据权利要求1所述的显示基板,其中所述金属层还包括第三金属层,其中所述第一金属层层叠在所述第三金属层上,所述第三金属层的抗腐蚀性强于所述第一金属层的抗腐蚀性。
7.根据权利要求6所述的显示基板,其中所述第一金属层包含铝,以及所述第二金属层和所述第三金属层均包含钛。
8.根据权利要求1所述的显示基板,其中所述导电材料层是包括透明导电氧化物层、金属材料层和透明导电氧化物层的多层结构。
9.根据权利要求8所述的显示基板,其中所述透明导电氧化物层包括下列各项组成的组中的任何一项:氧化铟、氧化锡、氧化锡铟、及其任何两种或更多种的混合物。
10.根据权利要求8所述的显示基板,其中所述金属材料层包含银。
11.根据权利要求8所述的显示基板,其中所述透明导电氧化物层包含氧化锡铟,并且所述金属材料层包含银。
12.根据权利要求1所述的显示基板,其中所述焊盘还包括包含金球的异向导电胶,其中所述第二金属层与所述包含金球的异向导电胶接触。
13.一种显示装置,包括根据权利要求1至12中任何一项所述的显示基板。
14.一种用于制备显示基板的方法,所述显示基板包括显示区和在所述显示区之外的焊盘区,所述方法包括以下步骤:
在焊盘区形成金属层,所述金属层包括第一金属层和层叠在所述第一金属层上的第二金属层,其中所述第二金属层的抗腐蚀性强于所述第一金属层的抗腐蚀性;
在所述第二金属层上形成导电材料层;
在所述导电材料层上涂布光刻胶;
用掩模覆盖所述金属层的侧表面进行曝光、显影和刻蚀,以保留所述侧表面上的导电材料层;和
去除所述金属层的所述侧表面上的光刻胶。
15.根据权利要求14所述的方法,其中所述显示区包括显示电极,以及所述焊盘区的所述导电材料层与所述显示区的所述显示电极同时形成。
16.根据权利要求15所述的方法,其中所述显示电极包括阳极,以及所述焊盘区的所述导电材料层与所述显示区的所述阳极同时形成。
17.根据权利要求14所述的方法,其中所述显示区还包括源/漏极,以及所述焊盘区的所述金属层和所述显示区的所述源/漏极同时形成。
18.根据权利要求14所述的方法,还包括:在将所述金属层的所述侧表面上的所述掩模去除之后,在所述第二金属层上形成包含金球的异向导电胶。
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JP2020526778A (ja) | 2020-08-31 |
WO2019015270A1 (zh) | 2019-01-24 |
CN109273483B (zh) | 2021-04-02 |
US10756034B2 (en) | 2020-08-25 |
JP7113757B2 (ja) | 2022-08-05 |
US20190189573A1 (en) | 2019-06-20 |
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EP3457438A1 (en) | 2019-03-20 |
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