WO2019015270A1 - 显示基板及其制备方法和显示装置 - Google Patents

显示基板及其制备方法和显示装置 Download PDF

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Publication number
WO2019015270A1
WO2019015270A1 PCT/CN2018/072071 CN2018072071W WO2019015270A1 WO 2019015270 A1 WO2019015270 A1 WO 2019015270A1 CN 2018072071 W CN2018072071 W CN 2018072071W WO 2019015270 A1 WO2019015270 A1 WO 2019015270A1
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Prior art keywords
layer
metal
display
conductive material
pad
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PCT/CN2018/072071
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English (en)
French (fr)
Inventor
黄炜赟
青海刚
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/092,721 priority Critical patent/US10756034B2/en
Priority to JP2018552877A priority patent/JP7113757B2/ja
Priority to EP18780011.5A priority patent/EP3457438A4/en
Publication of WO2019015270A1 publication Critical patent/WO2019015270A1/zh

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Definitions

  • the present disclosure relates to the field of organic light emitting display technology, and more particularly to a display substrate, a method of fabricating the same, and a display device.
  • the pad for the display device includes a metal sub-layer having a weaker corrosion resistance which is exposed at the edge of the pad and may cause damage to the exposed metal sub-layer when performing an electrode etching process on the electrode in the display region , thereby damaging the pads and the display device.
  • the edges of the pads are usually covered with a pixel defining layer material such as polyimide or acrylic.
  • a pixel defining layer material such as polyimide or acrylic.
  • the pixel defining layer is generally thick, in order not to affect the soldering quality, it is necessary to thin the pixel defining layer covering the pad region. Such thinning requires a halftone mask, and then a layer of a conductive material is deposited and an etching of the layer of the conductive material is performed, so that the cost increases and the process becomes complicated.
  • a display substrate including:
  • the pad region includes at least one pad, the pad comprising:
  • a metal layer comprising a first metal sub-layer and a second metal sub-layer laminated on the first metal sub-layer, wherein the second metal sub-layer is more resistant to corrosion than the first metal Sub-layer corrosion resistance;
  • the display area includes a display electrode, wherein the conductive material layer of the pad is disposed in the same layer as the display electrode of the display area.
  • the display electrode includes an anode, wherein the conductive material layer of the pad is disposed in the same layer as the anode.
  • the display region includes a transistor including a source and a drain, wherein the metal layer of the pad is the same as the source and drain of the display region Layer settings.
  • the first metal sublayer comprises aluminum and the second metal sublayer comprises titanium.
  • the metal layer further includes a third metal sublayer, wherein the first metal sublayer is laminated on the third metal sublayer, and the third metal sublayer is resistant to corrosion It is stronger than the corrosion resistance of the first metal sublayer.
  • the first metal sublayer comprises aluminum, and the second metal sublayer and the third metal sublayer each comprise titanium.
  • the conductive material layer is a multilayer structure including a first transparent conductive oxide layer, a metal material layer, and a second transparent conductive oxide layer.
  • the first or second transparent conductive oxide layer comprises any one of the group consisting of indium oxide, tin oxide, indium tin oxide, and any two or A mixture of more species.
  • the metal material layer contains silver.
  • the first or second transparent conductive oxide layer comprises indium tin oxide
  • the metal material layer comprises silver
  • the pad further includes an anisotropic conductive paste including a gold ball, wherein the second metal sublayer is in contact with the anisotropic conductive paste containing a gold ball.
  • a display device comprising the display substrate of any of the above.
  • a method for preparing a display substrate including a display area and a pad area outside the display area comprising the steps of:
  • the metal layer comprising a first metal sub-layer and a second metal sub-layer laminated on the first metal sub-layer, wherein the second metal sub-layer is more resistant to corrosion than Corrosion resistance of the first metal sublayer;
  • a layer of conductive material is formed, the layer of conductive material covering a side surface of the metal layer.
  • forming the conductive material layer includes:
  • the remaining photoresist is removed.
  • the method further includes the step of, after the developing, further retaining a photoresist covering a portion of the pre-formed conductive material layer in the display region, thereby removing remaining light After engraving, a portion of the layer of pre-formed conductive material in the display region forms a display electrode.
  • the display electrode includes an anode, and the conductive material layer of the pad region is formed simultaneously with the anode of the display region.
  • the display region further includes a source and a drain, and the metal layer of the pad region and the source and drain of the display region are simultaneously formed.
  • the method further includes forming an anisotropic conductive paste comprising a gold ball on the second metal sub-layer after etching the exposed portion of the pre-formed conductive material layer.
  • FIG. 1 is a cross-sectional view schematically showing an etched metal layer of a pad of a display substrate without protection.
  • FIG. 2 is a cross-sectional view schematically showing a display substrate when a periphery of a pad is covered with a pixel defining layer material such as polyimide or acryl.
  • FIG. 3A to 3E are cross-sectional views schematically showing a display substrate after respective process steps of a method for preparing a display substrate according to an embodiment of the present disclosure, wherein FIG. 3A is a cross-sectional view after the step of applying a photoresist; 3B is a cross-sectional view showing a step of masking a photoresist using a mask; FIG. 3C is a cross-sectional view showing a step of exposing a portion of the pre-formed conductive material layer after exposure and development; FIG. 3D is a cross-sectional view of etching the pre-formed conductive material layer; and FIG. A cross-sectional view of the glue step.
  • FIG. 4 is a cross-sectional view schematically showing a display substrate according to an embodiment of the present disclosure.
  • first”, “second” and “third” are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining “first”, “second” or “third” may include one or more of the features either explicitly or implicitly.
  • Pads for display devices typically include a metal layer.
  • the metal layer generally includes a first metal sub-layer and a second metal sub-layer laminated on the first metal sub-layer, wherein the first metal sub-layer is less resistant to corrosion than the second metal sub-layer Corrosion resistance.
  • the metal layer is a first conductive metal sublayer including a weak corrosion resistance, a second metal sublayer having a strong corrosion resistance for corrosion resistance thereon, and a substrate for reinforcement thereto
  • the combined corrosion-resistant multilayer structure of the third metal sub-layer such as a multilayer structure of a titanium layer, an aluminum layer, and a titanium layer.
  • the first metal sub-layer such as the aluminum layer having weak corrosion resistance in the pad in the pad region may be undercut, which makes the multilayer structure unstable.
  • a second metal sub-layer such as a titanium layer, which is more resistant to corrosion, collapses in subsequent processes and becomes a moving conductive particle, which causes a short circuit between different signal lines.
  • the present disclosure provides a display substrate, a method of fabricating the same, and a display device, which can avoid undercutting a first metal sub-layer such as an aluminum layer having weak corrosion resistance, thereby It is avoided that the corrosion-resistant second metal sub-layer such as the titanium layer collapses into a moving conductive particle in a subsequent process, causing a short circuit between different signal lines.
  • the method of making the display substrate of the present disclosure does not increase process steps and costs.
  • a display substrate can be provided.
  • the display substrate includes: a display area; and a pad area outside the display area.
  • the pad region includes at least one pad.
  • the pad includes a metal layer and a layer of conductive material.
  • the metal layer includes a first metal sub-layer and a second metal sub-layer laminated on the first metal sub-layer. The corrosion resistance of the second metal sublayer is stronger than the corrosion resistance of the first metal sublayer.
  • the layer of conductive material covers a side surface of the metal layer.
  • the display area may include a display electrode.
  • the conductive material layer of the pad is disposed in the same layer as the display electrode of the display area.
  • the display electrode includes an anode, wherein the conductive material layer of the pad is disposed in the same layer as the anode.
  • the display region further includes a source and a drain, wherein the metal layer of the pad is disposed in the same layer as the source and drain of the display region.
  • the metal layer is a layer formed in the same layer as the source and drain of the transistor in the display substrate and is included a three-layer structure of a titanium layer, an aluminum layer and a titanium layer;
  • the display electrode is an anode;
  • the conductive material layer is an anode material layer formed in the same layer and in the same patterning process as the anode;
  • the conductive material layer and the anode are composed of an ITO layer, a silver layer and ITO
  • the transistor can be, for example, a thin film transistor (TFT).
  • the metal layer can be a two-layer structure comprising an aluminum layer and a titanium layer overlying the aluminum layer.
  • the display electrode can also be a cathode, and the layer of conductive material can also be selected from the same material as the cathode to be formed in the same layer and in the same patterning process.
  • metal layers are sometimes also referred to as source and drain metal layers
  • conductive material layers are sometimes referred to as anode material layers
  • display electrodes are sometimes referred to as anodes.
  • FIG. 1 is a cross-sectional view schematically showing a process in which a metal layer of a pad 100 of a display substrate is etched through an anode in a display region without protection.
  • the display substrate may include a pad region 1000, and a display region 2000 outside the pad region 1000.
  • Pad area 1000 can include at least one pad 100.
  • the pad 100 may include a base substrate 10, an insulating layer 20 formed on the base substrate 10, and a metal layer 30 on the insulating layer 20 (three-layer structure, which may correspond to a source in the display area 2000 described below) And the drain metal layers 94, 96, the same sub-layer is represented by the same legend).
  • the display region 2000 may include a thin film transistor (TFT) 90 on the insulating layer 20 and a display electrode 80 such as an anode 80.
  • the display electrode can be, for example, a pixel electrode.
  • the TFT 90 may include a gate electrode 91, an interlayer dielectric layer 92, an active layer 93, a source electrode 94, and a drain electrode 96.
  • Source 94 or drain 96 may be coupled to display electrode 80, such as anode 80.
  • the drain 96 can be connected to the anode 80.
  • the metal layer 30 may be a multilayer structure including a third metal sublayer 32 which is more resistant to corrosion, a first metal sublayer 34 which is less resistant to corrosion, and a second metal sublayer 36 which is more resistant to corrosion, such as The multilayer structure of the first titanium layer 32, the aluminum layer 34, and the second titanium layer 36.
  • the first metal sub-layer 34 is between the third metal sub-layer 32 and the second metal sub-layer 36.
  • the pad 100 after passing through the etching process on the anode of the display device, causes an undercut of the intermediate first metal sub-layer such as the aluminum layer 34, making the multilayer structure unstable.
  • the second metal sub-layer 36 of the upper layer, such as the second titanium layer 36 may collapse during subsequent processes, becoming moving conductive particles, which may cause short circuits between different signal lines.
  • FIG. 2 is a cross-sectional view schematically showing a display substrate when an edge of the pad 100 is covered with a pixel defining layer material such as polyimide or acryl.
  • a pixel defining layer material such as polyimide or acryl.
  • the edges of the pads 100 are covered with a pixel defining layer material such as polyimide or acryl.
  • a pixel defining layer material such as polyimide or acryl.
  • the pixel defining layer 70 is generally thick, in order not to affect the soldering quality, the pixel defining layer covering the pad region 1000 needs to be thinned to form a thinned pixel defining layer 75.
  • Such thinning requires, for example, a halftone mask, so the cost increases and the process becomes complicated.
  • 150, 65, 60 in the figure respectively represent pads, gold balls, and anisotropic conductive paste of another circuit board such as a flexible printed circuit board (FPC).
  • FIGS. 3A to 3E are cross-sectional views schematically showing a display substrate after respective process steps of a method for preparing a display substrate, in which FIG. 3A is a cross-sectional view after the step of coating the photoresist 50, according to an embodiment of the present disclosure.
  • Figure 3B is a cross-sectional view showing a step of masking a photoresist using a mask
  • Figure 3C is a cross-sectional view showing a step of exposing a portion of the pre-formed conductive material layer after exposure and development
  • Figure 3D is a cross-sectional view of etching a layer of a pre-formed conductive material
  • Figure 3E is a view of removing light A cross-sectional view of the 50 step of engraving.
  • the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals; and detailed description thereof will not be repeated.
  • the method of the present disclosure for preparing a display substrate includes the following steps:
  • a metal layer 30 is formed in the pad region 1000; the metal layer 30 includes a first metal sub-layer 34 and a second metal sub-layer 36 laminated on the first metal sub-layer 34, wherein the second metal sub-layer 36 is highly resistant to corrosion Corrosion resistance to the first metal sub-layer 34;
  • a photoresist 50 is coated on the pre-formed conductive material layer 40.
  • the photoresist 50 is then masked by a mask M.
  • the occluded portion is the portion of the layer of pre-formed conductive material that is not desired to be etched away. In the figure, it is above the side surface of the metal layer 30, that is, the conductive material layer 40 that is intended to remain on the side of the metal layer 30.
  • a portion of the pre-formed conductive material layer 40 is subsequently exposed, developed, and exposed, wherein at least a photoresist that covers the pre-formed conductive material layer 40 on the side surface of the metal layer 30 remains after the development. 50, and at least removing the photoresist covering the pre-formed conductive material layer on a portion of the top surface of the metal layer.
  • the pre-formed conductive material layer 40 is subsequently etched.
  • the conductive material of the portion covered by the photoresist is retained and the other portions are etched away.
  • Figures 3A-3E also schematically illustrate one embodiment of a method of preparation including other components.
  • Display area 2000 can include display electrode 80.
  • the conductive material layer 40 of the pad region 1000 may be formed simultaneously with the display electrode 80 of the display region 2000, that is, formed in the same layer and formed using the same patterning process.
  • the pre-formed conductive material layer 40 extends to a portion of the display region 2000 where the display electrode 80 is to be formed.
  • the pad region 1000 and the prefabricated conductive material layer in the display region 2000 are continuous, they may be discontinuous. They may be formed in the same layer in one step such as a deposition step, but may also be formed separately.
  • a mask is also disposed over the photoresist 50 at a portion of the display electrode. As shown in FIG.
  • the display electrode can include an anode 80.
  • the conductive material layer 40 of the pad region 1000 and the anode 80 of the display region 2000 may be formed simultaneously, that is, formed in the same layer and formed using the same patterning process.
  • the pre-formed conductive material layer 40 extends to the portion of the display region 2000 where the anode 80 is to be formed.
  • the pad region 1000 and the prefabricated conductive material layer in the display region 2000 are continuous, they may be discontinuous. They may be formed in the same layer in one step such as a deposition step, but may also be formed separately.
  • a portion of the anode 80 is also provided with a mask over the photoresist 50. As shown in FIG.
  • the metal layer 30 of the pad region 1000 may be formed simultaneously with the source and drain electrodes in the transistor of the display region 2000, that is, formed in the same layer and formed using the same patterning process.
  • the anode material layer 40 covering the side surface of the metal layer 30 also belongs to the conductive contact region, and the conductivity of the metal layer 30 can be further improved.
  • FIG. 4 is a cross-sectional view schematically showing a display substrate according to an embodiment of the present disclosure.
  • the display substrate of the present disclosure may include a pad region 1000, and a display region 2000 outside the pad region 1000.
  • Pad area 1000 can include at least one pad 100.
  • the pad 100 may include a base substrate 10, an insulating layer 20 formed on the base substrate 10, and a metal layer 30 on the insulating layer 20.
  • the display area 2000 may include a TFT 90 on the insulating layer 20 and a display electrode 80 such as an anode 80.
  • the TFT 90 may include a gate electrode 91, an interlayer dielectric layer 92, an active layer 93, a source electrode 94, and a drain electrode 96. Source 94 or drain 96 may be coupled to display electrode 80, such as anode 80.
  • the drain 96 can be connected to the anode 80.
  • the metal layer 30 may be a multilayer structure including a third metal sublayer 32 which is more resistant to corrosion, a first metal sublayer 34 which is less resistant to corrosion, and a second metal sublayer 36 which is more resistant to corrosion, such as The multilayer structure of the first titanium layer 32, the aluminum layer 34, and the second titanium layer 36.
  • the first metal sub-layer 34 is between the third metal sub-layer 32 and the second metal sub-layer 36.
  • the metal layer 30 may also include only weak corrosion resistance.
  • the two-layer structure of the first metal sub-layer 34 and the second metal sub-layer 36 which is more resistant to corrosion.
  • the second metal sub-layer 36 covers the first metal sub-layer 34.
  • the metal layer 30 may be a two-layer structure of the aluminum layer 34 and the titanium layer 36. Titanium layer 36 covers aluminum layer 34.
  • the side surface of the metal layer 30 is covered by the anode material layer 40.
  • the anode material layer 40 covering the side surface of the metal layer 30 also belongs to the conductive contact region, and the conductivity of the metal layer 30 can be further improved.
  • the metal layer 30 may be a multilayer structure including the first titanium layer 32, the aluminum layer 34, and the second titanium layer 36.
  • Aluminum layer 34 is between first titanium layer 32 and second titanium layer 36.
  • the first titanium layer 32 may have a thickness of 400 to
  • the aluminum layer 34 may have a thickness of 4000
  • the thickness of the second titanium layer may be 400 to
  • the thicknesses of the first titanium layer 32 and the second titanium layer 36 may be the same or different.
  • the thickness of the titanium layer 36 may be 400 to And the thickness of the aluminum layer 34 can be 4000 to
  • the anode material layer 40 may be a multilayer structure including a first transparent conductive oxide layer, a metal material layer, and a second transparent conductive oxide layer.
  • the metal material layer is between the first transparent conductive oxide layer and the second transparent conductive oxide layer.
  • the thickness of the first transparent conductive oxide layer may be 50 to
  • the thickness of the metal material layer can be 800 to
  • the thickness of the second transparent conductive oxide layer may be 50 to
  • the thicknesses of the first transparent conductive oxide layer and the second transparent conductive oxide layer may be the same or different.
  • the transparent conductive oxides in the first and second transparent conductive oxide layers may be the same or different, and the first and second transparent conductive oxide layers may include a group consisting of the following Any of: indium oxide, tin oxide, indium tin oxide, and a mixture of any two or more thereof.
  • the metal material layer may include silver, such as silver.
  • the anode material layer may include a first indium tin oxide (ITO) layer, a silver layer, and a second indium tin oxide (ITO) layer.
  • the silver layer is between the first ITO layer and the second ITO layer.
  • the display substrate may be an active matrix light emitting substrate or a passive matrix light emitting substrate.
  • the pad 100 may also be bonded to the pad 150 of another circuit board by the anisotropic conductive paste 60 including the gold ball 65 on the second metal sub-layer 36.
  • the second metal sub-layer 36 is in contact with the anisotropic conductive paste 60 containing the gold balls 65.
  • the pads of the present disclosure can be used to connect an integrated circuit board or a flexible printed circuit board, such as electrically connected to pads 150 of an integrated circuit board or flexible printed circuit board.
  • the display area includes the display electrode 80.
  • the conductive material layer 40 of the pad 100 is disposed in the same layer as the display electrode 80 of the display region and formed by the same patterning process. As such, the conductive material layer 40 of the pad 100 can be formed without increasing process steps and costs.
  • the display electrode includes an anode 80.
  • the anode material layer 40 of the pad is disposed in the same layer as the anode 80 and formed by the same patterning process. As such, the anode material layer 40 of the pad 100 can be formed without increasing process steps and costs.
  • the display region further includes a transistor such as a TFT, and the transistor includes a source 94/drain 96.
  • the metal layer 30 of the pad 100 is disposed in the same layer as the source 94/drain 96 of the display region and formed by the same patterning process. As such, the metal layer 30 of the pad 100 can be formed without increasing process steps and costs.
  • the method for preparing a display substrate may further include forming a gold ball 65 on the second metal sub-layer 36 after removing the photoresist on the side surface of the metal layer 30.
  • Anisotropic conductive paste 60 may be formed on the second metal sub-layer 36 after removing the photoresist on the side surface of the metal layer 30.
  • the pad 100 of the present disclosure may be connected to an integrated circuit board or a flexible printed circuit board by an anisotropic conductive paste 60, such as electrically connected to pads 150 of an integrated circuit board or a flexible printed circuit board.
  • the display device of the present disclosure may include the display substrate of the present disclosure.
  • the display substrate of the present disclosure may include an active matrix light emitting substrate or a passive matrix light emitting substrate.
  • the display device of the present disclosure may include an active matrix light emitting display device and a passive matrix light emitting display device.
  • the display substrate of the present disclosure its preparation method and display device, undercutting of the intermediate first metal sub-layer such as the aluminum layer 34 can be avoided without increasing the number of process steps and costs.
  • the problem that the second metal sub-layer of the upper layer, such as the second titanium layer 36, collapses into moving conductive particles in the subsequent process, causing a short circuit between the different signal lines is avoided.
  • the intermediate aluminum layer 34 can be avoided by the display substrate of the present disclosure, the method of manufacturing the same, and the display device. An undercut appears. Thereby, the problem that the second titanium layer 36 is collapsed into a moving conductive particle in the subsequent process to cause a short circuit between the different signal lines is avoided.
  • the conductive material layer 40 covering the side surface of the metal layer 30, such as the anode conductive material 40 also belongs to the conductive contact region, and the conductivity of the metal layer 30 can be further improved.
  • the display substrate, the preparation method thereof and the display device of the present disclosure can avoid undercutting the first metal sub-layer such as the aluminum layer with weak corrosion resistance, thereby avoiding the second metal sub-layer with strong corrosion resistance. For example, in the subsequent process, the titanium layer collapses into a moving conductive particle, causing a short circuit between different signal lines.
  • the display substrate fabrication method of the present disclosure does not increase process steps and costs.
  • the metal layer is a multilayer structure including a titanium layer, an aluminum layer, and a titanium layer
  • the preparation method thereof, and the display device can avoid the undercut of the intermediate aluminum layer, thereby It is avoided that the upper titanium layer collapses into a moving conductive particle in a subsequent process, causing a short circuit between different signal lines.
  • the conductive material layer covering the side surface of the metal layer also belongs to the conductive contact region, and the conductivity of the metal layer can be further improved.

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Abstract

显示基板及其制备方法和显示装置，显示基板包括：显示区(2000)；和在所述显示区(2000)之外的焊盘区(1000)。所述焊盘区(1000)包括至少一个焊盘(100)。所述焊盘(100)包括：金属层(30)，所述金属层(30)包括第一金属亚层(34)和层叠在所述第一金属亚层(34)上的第二金属亚层(36)，其中所述第二金属亚层(36)的抗腐蚀性强于所述第一金属亚层(34)的抗腐蚀性；以及导电材料层(40)，所述导电材料层(40)覆盖所述金属层(30)的侧表面。

Description

显示基板及其制备方法和显示装置
相关申请的交叉引用
本公开要求2017年7月17日递交的中国专利申请号201710584603.4的优先权，其全部内容过引用结合在此。
技术领域
本公开涉及有机发光显示技术领域，更具体地，涉及一种显示基板及其制备方法和显示装置。
背景技术
用于显示装置的焊盘包括具有较弱抗腐蚀性的金属亚层，其在焊盘边缘暴露当对显示区域中的电极进行电极刻蚀工艺时，可能会对暴露的该金属亚层形成伤害，进而损害焊盘和显示装置。
为了防止出现上述问题，通常采用像素定义层材料如聚酰亚胺或亚克力对焊盘的边缘进行覆盖。但是，由于像素定义层一般都较厚，为了不影响焊接质量，需要对覆盖焊盘区的像素定义层进行薄化。这样的薄化需要采用半色调掩模进行，然后再沉积导电材料层和进行导电材料层的刻蚀，因此成本增加并且工艺变得复杂。
发明内容
在本公开的一个方面，提供一种显示基板，包括：
显示区；和
在所述显示区之外的焊盘区，
其中所述焊盘区包括至少一个焊盘，所述焊盘包括：
金属层，所述金属层包括第一金属亚层和层叠在所述第一金属亚层上的第二金属亚层，其中所述第二金属亚层的抗腐蚀性强于所述第一金属亚层的抗腐蚀性；以及
导电材料层，所述导电材料层覆盖所述金属层的侧表面。
根据本公开的另一个实施方案，所述显示区包括显示电极，其中所述焊盘的所述导电材料层与所述显示区的所述显示电极同层设置。
根据本公开的另一个实施方案，所述显示电极包括阳极，其中所述焊盘的所述导电材料层与所述阳极同层设置。
根据本公开的另一个实施方案，所述显示区包括晶体管，所述晶体管包括源极和漏极，其中所述焊盘的所述金属层与所述显示区的所述源极和漏极同层设置。
根据本公开的另一个实施方案，所述第一金属亚层包含铝，并且所述第二金属亚层包含钛。
根据本公开的另一个实施方案，所述金属层还包括第三金属亚层，其中所述第一金属亚层层叠在所述第三金属亚层上，所述第三金属亚层的抗腐蚀性强于所述第一金属亚层的抗腐蚀性。
根据本公开的另一个实施方案，所述第一金属亚层包含铝，以及所述第二金属亚层和所述第三金属亚层均包含钛。
根据本公开的另一个实施方案，所述导电材料层是包括第一透明导电氧化物层、金属材料层和第二透明导电氧化物层的多层结构。
根据本公开的另一个实施方案，所述第一或第二透明导电氧化物层包括下列各项组成的组中的任何一项：氧化铟、氧化锡、氧化锡铟、及其任何两种或更多种的混合物。
根据本公开的另一个实施方案，所述金属材料层包含银。
根据本公开的另一个实施方案，所述第一或第二透明导电氧化物层包含氧化锡铟，并且所述金属材料层包含银。
根据本公开的另一个实施方案，所述焊盘还包括包含金球的异向导电胶，其中所述第二金属亚层与所述包含金球的异向导电胶接触。
在公开的另一方面，提供一种显示装置，包括上面中任何一项所述的显示基板。
在公开的再一方面，提供一种用于制备显示基板的方法，所述显示基板包括显示区和在所述显示区之外的焊盘区，所述方法包括以下步骤：
在焊盘区形成金属层，所述金属层包括第一金属亚层和层叠在所述第一金属亚层上的第二金属亚层，其中所述第二金属亚层的抗腐蚀性强于所 述第一金属亚层的抗腐蚀性；
形成导电材料层，所述导电材料层覆盖所述金属层的侧表面。
根据本公开的一个实施方案，形成导电材料层包括：
形成预制导电材料层，所述预制导电材料层至少覆盖所述金属层的顶表面和侧表面；
在所述预制导电材料层上涂布光刻胶；
用掩模对所述光刻胶进行曝光、显影并暴露所述预制导电材料层的一部分，其中在所述显影后至少保留遮盖所述金属层的侧表面上的预制导电材料层的光刻胶，并且至少去除遮盖所述金属层的一部分顶表面上的预制导电材料层的光刻胶；
刻蚀所述预制导电材料层的暴露的部分；和
去除剩余的光刻胶。
根据本公开的一个实施方案，所述方法还包括以下步骤：在所述显影后，还保留遮盖所述显示区中的所述预制导电材料层的一部分的光刻胶，从而在去除剩余的光刻胶后，在所述显示区中的所述预制导电材料层的部分形成显示电极。
根据本公开的另一个实施方案，所述显示电极包括阳极，以及所述焊盘区的所述导电材料层与所述显示区的所述阳极同时形成。
根据本公开的另一个实施方案，所述显示区还包括源极和漏极，以及所述焊盘区的所述金属层和所述显示区的所述源极和漏极同时形成。
根据本公开的另一个实施方案，所述方法还包括：在刻蚀所述预制导电材料层的暴露的部分之后，在所述第二金属亚层上形成包含金球的异向导电胶。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的示例性实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是示意性地表示在显示基板的焊盘的金属层在没有保护的情况下经过刻蚀后的剖视图。
图2是示意性地表示用像素定义层材料如聚酰亚胺或亚克力对焊盘的边缘进行覆盖时的显示基板的剖视图。
图3A～3E是示意性地表示根据本公开的一个实施方案，用于制备显示基板的方法的各个工艺步骤后的显示基板的剖视图，其中图3A是涂布光刻胶的步骤之后的剖视图；图3B是使用掩模遮盖光刻胶的步骤的剖视图；图3C是曝光显影之后暴露部分预制导电材料层的步骤的剖视图；图3D是蚀刻预制导电材料层的剖视图；且图3E是去除光刻胶步骤的剖视图。
图4是示意性地表示根据本公开的一个实施方案的显示基板的剖视图。
具体实施方式
下面将结合本公开的具体实施方案，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施方案和/或实施例仅仅是本公开一部分实施方案和/或实施例，而不是全部的实施方案和/或实施例。基于本公开中的实施方案和/或实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施方案和/或所有其他实施例，都属于本公开保护的范围。
在本公开中，如果没有具体指明，层或膜可以互换地使用；并且焊盘有时也称作焊垫。术语“第一”、“第二”和“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”或“第三”的特征可以明示或者隐含地包括一个或者更多个该特征。
用于显示装置的焊盘通常包括金属层。金属层通常包括第一金属亚层和在层叠在所述第一金属亚层上的第二金属亚层，其中所述第一金属亚层的抗腐蚀性弱于所述第二金属亚层的抗腐蚀性。例如，金属层是包括抗腐蚀性较弱的第一导电金属亚层、在其上的用于抗腐蚀的抗腐蚀性较强的第二金属亚层、和在其下的用于增强到基板的结合性的抗腐蚀性较强的第三金属亚层的多层结构，例如钛层、铝层和钛层的多层结构。当对显示区域中的电极进行电极刻蚀工艺时，会导致焊盘区域中的焊盘中抗腐蚀性较弱 的第一金属亚层如铝层出现底切而使得此多层结构很不稳定。例如，抗腐蚀性较强的第二金属亚层如钛层会在其后的工艺中出现坍塌，变成移动的导电颗粒，会使不同信号线之间发生短路。
鉴于相关技术中的一个或多个问题，本公开提供了一种显示基板及其制备方法和显示装置，其可以避免使抗腐蚀性较弱的第一金属亚层如铝层出现底切，从而避免使抗腐蚀性较强的第二金属亚层如钛层在其后的工艺中出现坍塌变成移动的导电颗粒，使不同信号线之间发生短路的问题。在一些实施例中，本公开的显示基板的制备方法不会增加工艺步骤和成本。
在本公开的一个方面，可以提供一种显示基板。所述显示基板包括：显示区；和在所述显示区之外的焊盘区。所述焊盘区包括至少一个焊盘。所述焊盘包括：金属层和导电材料层。所述金属层包括第一金属亚层和层叠在所述第一金属亚层上的第二金属亚层。所述第二金属亚层的抗腐蚀性强于所述第一金属亚层的抗腐蚀性。所述导电材料层覆盖所述金属层的侧表面。
根据本公开的一个实施方案，所述显示区可以包括显示电极。所述焊盘的所述导电材料层与所述显示区的所述显示电极同层设置。
根据本公开的另一个实施方案，所述显示电极包括阳极，其中所述焊盘的所述导电材料层与所述阳极同层设置。
根据本公开的另一个实施方案，所述显示区还包括源极和漏极，其中所述焊盘的所述金属层与所述显示区的所述源极和漏极同层设置。
以下，为了举例说明本公开，以以下情况为例并且结合附图进行说明，但本公开不限于此：金属层是与显示基板中的晶体管的源极和漏极同层形成的层并且是包括钛层、铝层和钛层的三层结构；显示电极是阳极；导电材料层是与阳极同层且同一构图工艺形成的阳极材料层；导电材料层和阳极是包含ITO层、银层和ITO层的三层结构。晶体管可以例如是薄膜晶体管(TFT)。在备选的实例中，金属层可以是包括铝层和覆盖铝层的钛层的双层结构。在备选的实例中，显示电极也可以是阴极，导电材料层也可以选择与阴极相同的材料来同层且同一构图工艺形成。
因此，在以下描述中，金属层有时也称作源极和漏极金属层，并且导 电材料层有时也称作阳极材料层，显示电极有时也称作阳极。
在显示基板的一般制备过程中，当对显示区中的电极进行电极刻蚀工艺时，焊盘区中已经形成的金属层中不耐腐蚀的部分会遭受腐蚀。图1是示意性地表示在显示基板的焊盘100的金属层在没有保护的情况下经过对显示区中的阳极进行刻蚀工艺后的剖视图。
如图1所示，显示基板可以包括焊盘区1000，和在所述焊盘区1000之外的显示区2000。焊盘区1000可以包括至少一个焊盘100。焊盘100可以包括衬底基板10、形成在衬底基板10上的绝缘层20、在绝缘层20上的金属层30(三亚层结构，其可以对应于下述的显示区2000中的源极和漏极金属层94、96，相同亚层用相同图例表示)。显示区2000可以包括在绝缘层20上的薄膜晶体管(TFT)90和显示电极80如阳极80。显示电极可以是例如像素电极。TFT 90可以包括栅极91、层间介质层92、有源层93、源极94和漏极96。源极94或漏极96可以与显示电极80如阳极80连接。漏极96可以与阳极80连接。金属层30可以是包括抗腐蚀性较强的第三金属亚层32、抗腐蚀性较弱的第一金属亚层34和抗腐蚀性较强的第二金属亚层36的多层结构，例如第一钛层32、铝层34和第二钛层36的多层结构。第一金属亚层34位于第三金属亚层32和第二金属亚层36之间。焊盘100在经过对显示装置的阳极进行刻蚀工艺之后，会导致中间的第一金属亚层如铝层34出现底切而使得此多层结构很不稳定。例如，上层的第二金属亚层36如第二钛层36会在其后的工艺中出现坍塌，变成移动的导电颗粒，会导致不同信号线之间发生短路。
图2是示意性地表示用像素定义层材料如聚酰亚胺或亚克力对焊盘100的边缘进行覆盖时的显示基板的剖视图。与图1中相同的部件由相同的附图标记表示；并且不再对其详细描述。
为了防止出现结合图1中所述的问题，采用像素定义层材料如聚酰亚胺或亚克力对焊盘100的边缘进行覆盖。但是，由于像素定义层70一般都较厚，为了不影响焊接质量，需要对覆盖焊盘区1000的像素定义层进行薄化，以形成薄化的像素定义层75。这样的薄化需要例如采用半色调掩 模进行，因此成本增加并且工艺变得复杂。图中的150、65、60分别表示另一电路板如柔性印刷电路板(FPC)的焊盘、金球和异向导电胶。
图3A～3E是示意性地表示根据本公开的一个实施方案，用于制备显示基板的方法的各个工艺步骤后的显示基板的剖视图，其中图3A是涂布光刻胶50的步骤之后的剖视图；图3B是使用掩模遮盖光刻胶的步骤的剖视图；图3C是曝光显影之后暴露部分预制导电材料层的步骤的剖视图；图3D是蚀刻预制导电材料层的剖视图；且图3E是去除光刻胶50步骤的剖视图。与图1和2中相同的部件由相同的附图标记表示；并且不再对其详细描述。
首先以图3A-3E的左侧的焊盘区1000来说明本公开的方法的一个实施方案。
如图3A所示，本公开用于制备显示基板的方法包括以下步骤：
在焊盘区1000形成金属层30；金属层30包括第一金属亚层34和层叠在第一金属亚层34上的第二金属亚层36，其中第二金属亚层36的抗腐蚀性强于第一金属亚层34的抗腐蚀性；
在第二金属亚层36上形成预制导电材料层40；和
在预制导电材料层40上涂布光刻胶50。
如图3B所示，随后，用掩模M对所述光刻胶50进行遮挡。遮挡的部位是不想要刻蚀掉的预制导电材料层的部分。在图中，其在金属层30的侧表面的上方，即想要保留在金属层30的侧面上的导电材料层40。
如图3C示，随后，曝光、显影并暴露所述预制导电材料层40的一部分，其中在所述显影后至少保留遮盖所述金属层30的侧表面上的预制导电材料层40的光刻胶50，并且至少去除遮盖所述金属层的一部分顶表面上的预制导电材料层的光刻胶。
如图3D所示，随后，对预制导电材料层40进行刻蚀。受光刻胶遮盖的部分的导电材料得以保留，其他部分被刻蚀掉。
如图3E所示，随后，去除剩余的光刻胶50。
本发明的方法可以结合显示基板的其他部件的制备工艺。图3A-3E也示意性地表示了包括其他部件的制备方法的一个实施方案。
现在结合图右侧的显示区2000进行说明。
显示区2000可以包括显示电极80。焊盘区1000的导电材料层40可以与显示区2000的显示电极80同时形成，即同层形成且采用同一构图工艺形成。如图3A所示，预制导电材料层40延伸至显示区2000中要形成显示电极80的部分。虽然在此显示焊盘区1000与显示区2000中预制导电材料层是连续的，但也可以是不连续的。它们可以在一个步骤如沉积步骤中同层形成，但也可以分别形成。如图3B所示，在显示电极的部分也在光刻胶50上方设置掩模。如图3C所示，进行曝光和显影，保留金属层30侧表面的光刻胶和显示电极80处的光刻胶。如图3D所示，刻蚀除去多余的预制导电材料层，保留金属层30侧表面的导电材料层40和显示电极80处的导电材料。如图3E所示，除去剩余的光刻胶50，在形成覆盖金属层30的侧表面的导电材料层40的同时，形成显示电极80。
显示电极可以包括阳极80。焊盘区1000的导电材料层40与显示区2000的阳极80可以同时形成，即同层形成且采用同一构图工艺形成。如图3A所示，预制导电材料层40延伸至显示区2000中要形成阳极80的部分。虽然在此显示焊盘区1000与显示区2000中预制导电材料层是连续的，但也可以是不连续的。它们可以在一个步骤如沉积步骤中同层形成，但也可以分别形成。如图3B所示，在阳极80的部分也在光刻胶50上方设置掩模。如图3C所示，进行曝光和显影，保留金属层30侧表面的光刻胶和阳极80处的光刻胶。如图3D所示，刻蚀除去多余的预制导电材料层，保留金属层30侧表面的导电材料层40和阳极80处的导电材料。如图3E所示，除去剩余的光刻胶50，在形成覆盖金属层30的侧表面的导电材料层40的同时，形成阳极80。
此前，焊盘区1000的金属层30可以和显示区2000的晶体管中的源极和漏极同时形成，即同层形成且采用同一构图工艺形成。
如此，可以避免使第一金属亚层如铝层34在对阳极进行刻蚀工艺时出现底切。由此，避免了使第二金属亚层如第二钛层36在其后的工艺中出现坍塌变成移动的导电颗粒，使不同信号线之间发生短路的问题。另外，覆盖金属层30的侧表面的阳极材料层40也属于导电接触区，可以进一步提高金属层30的导电性。
图4是示意性地表示根据本公开的一个实施方案的显示基板的剖视图。
如图4中所示，本公开的显示基板可以包括焊盘区1000，和在所述焊盘区1000之外的显示区2000。焊盘区1000可以包括至少一个焊盘100。焊盘100可以包括衬底基板10、形成在衬底基板10上的绝缘层20、在绝缘层20上的金属层30。任选地，显示区2000可以包括在绝缘层20上的TFT 90和显示电极80如阳极80。TFT 90可以包括栅极91、层间介质层92、有源层93、源极94和漏极96。源极94或漏极96可以与显示电极80如阳极80连接。漏极96可以与阳极80连接。金属层30可以是包括抗腐蚀性较强的第三金属亚层32、抗腐蚀性较弱的第一金属亚层34和抗腐蚀性较强的第二金属亚层36的多层结构，例如第一钛层32、铝层34和第二钛层36的多层结构。第一金属亚层34位于第三金属亚层32和第二金属亚层36之间。
虽然在图4中示出了第一钛层32、滤层34和第二钛层36的三层结构，但本领域技术人员应当理解，金属层30也可以是仅包括抗腐蚀性较弱的第一金属亚层34和抗腐蚀性较强的第二金属亚层36的双层结构。第二金属亚层36覆盖第一金属亚层34。例如，金属层30可以是铝层34和钛层36的双层结构。钛层36覆盖铝层34。
如图4所示，金属层30的侧表面被阳极材料层40覆盖。这样，可以避免使第一金属亚层如铝层34在对阳极进行刻蚀工艺时出现底切。由此，避免了使第二金属亚层如第二钛层36在其后的工艺中出现坍塌变成移动的导电颗粒，使不同信号线之间发生短路的问题。另外，覆盖金属层30的侧表面的阳极材料层40也属于导电接触区，可以进一步提高金属层30的导电性。
根据本公开的一个实施方案，金属层30可以是包括第一钛层32、铝层34和第二钛层36的多层结构。铝层34位于第一钛层32和第二钛层36之间。第一钛层32的厚度可以为400至
Figure PCTCN2018072071-appb-000001
铝层34的厚度可以为4000至
Figure PCTCN2018072071-appb-000002
第二钛层的厚度可以为400至
Figure PCTCN2018072071-appb-000003
第一钛层32和第二钛层36的厚度可以相同或不同。
根据本公开的一个实施方案，在金属层30是铝层34和钛层36的双层结构的情况下，钛层36的厚度可以为400至
Figure PCTCN2018072071-appb-000004
并且铝层34的厚度可以为4000至
Figure PCTCN2018072071-appb-000005
根据本公开的另一个实施方案，阳极材料层40可以是包括第一透明导电氧化物层、金属材料层和第二透明导电氧化物层的多层结构。金属材料层位于第一透明导电氧化物层和第二透明导电氧化物层之间。第一透明导电氧化物层的厚度可以为50至
Figure PCTCN2018072071-appb-000006
金属材料层的厚度可以为800至
Figure PCTCN2018072071-appb-000007
第二透明导电氧化物层的厚度可以为50至
Figure PCTCN2018072071-appb-000008
第一透明导电氧化物层和第二透明导电氧化物层的厚度可以相同或不同。
根据本公开的另一个实施方案，第一和第二透明导电氧化物层中的透明导电氧化物可以相同或不同，并且第一和第二透明导电氧化物层可以包括由下列各项组成的组中的任何一项：氧化铟、氧化锡、氧化锡铟、及其任何两种或更多种的混合物。
根据本公开的另一个实施方案，金属材料层可以包括银，例如是银。例如，阳极材料层可以包括第一氧化锡铟(ITO)层、银层和第二氧化锡铟(ITO)层。银层位于第一ITO层和第二ITO层之间。
根据本公开的另一个实施方案，显示基板可以是有源矩阵发光基板或无源矩阵发光基板。
根据本公开的另一个实施方案，焊盘100还可以通过在第二金属亚层36上的包含金球65的异向导电胶60与另一电路板的焊盘150粘合。第二金属亚层36与包含金球65的异向导电胶60接触。
本公开的焊盘可以用于连接集成电路板或柔性印刷电路板，例如与集成电路板或柔性印刷电路板的焊盘150电连接。
根据本公开的另一个实施方案，显示区包括显示电极80。焊盘100的导电材料层40与显示区的显示电极80同层设置且同一构图工艺形成。如此，可以在不增加工艺步骤和成本的情况下形成焊盘100的导电材料层40。
根据本公开的另一个实施方案，显示电极包括阳极80。焊盘的阳极材料层40与阳极80同层设置且同一构图工艺形成。如此，可以在不增加工艺步骤和成本的情况下形成焊盘100的阳极材料层40。
根据本公开的另一个实施方案，显示区还包括晶体管如TFT，晶体管包括源极94/漏极96。焊盘100的金属层30与显示区的源极94/漏极96同层设置且同一构图工艺形成。如此，可以在不增加工艺步骤和成本的情况下形成焊盘100的金属层30。
根据本公开的另一个实施方案，用于制备显示基板的方法还可以包括：在将金属层30的侧表面上的光刻胶去除之后，在第二金属亚层36上形成包含金球65的异向导电胶60。
本公开的焊盘100可以通过异向导电胶60连接集成电路板或柔性印刷电路板，例如与集成电路板或柔性印刷电路板的焊盘150电连接。
本公开的显示装置可以包括本公开的显示基板。
本公开的显示基板可以包括有源矩阵发光基板或无源矩阵发光基板。本公开的显示装置可以包括有源矩阵发光显示装置和无源矩阵发光显示装置。
由本公开的显示基板及其制备方法和显示装置，可以在不增加工艺步骤和成本的情况下避免使中间的第一金属亚层如铝层34出现底切。由此，避免了使上层的第二金属亚层如第二钛层36在其后的工艺中出现坍塌变成移动的导电颗粒，使不同信号线之间发生短路的问题。
在金属层30是包括第一钛层32、铝层34和第二钛层36的多层结构的情况下，由本公开的显示基板及其制备方法和显示装置，可以避免使中间的铝层34出现底切。由此，避免了使第二钛层36在其后的工艺中出现坍塌变成移动的导电颗粒，使不同信号线之间发生短路的问题。
另外，覆盖金属层30的侧表面的导电材料层40如阳极导电材料40也属于导电接触区，可以进一步提高金属层30的导电性。
由本公开所述的显示基板及其制备方法和显示装置，可以避免使抗腐蚀性较弱的第一金属亚层如铝层出现底切，从而避免使抗腐蚀性较强的第二金属亚层如钛层在其后的工艺中出现坍塌变成移动的导电颗粒，使不同信号线之间发生短路的问题。在一些实施例中，本公开的显示基板制备方法不会增加工艺步骤和成本。
在所述金属层是包括钛层、铝层和钛层的多层结构的情况下，由本公开所述的显示基板及其制备方法和显示装置，可以避免使中间的铝层出现底切，从而避免使上层的钛层在其后的工艺中出现坍塌变成移动的导电颗粒，使不同信号线之间发生短路的问题。
另外，覆盖所述金属层的所述侧表面的导电材料层也属于导电接触区，可以进一步提高所述金属层的导电性。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (19)

  1. 一种显示基板，包括：
    显示区；和
    在所述显示区之外的焊盘区，
    其中所述焊盘区包括至少一个焊盘，所述焊盘包括：
    金属层，所述金属层包括第一金属亚层和层叠在所述第一金属亚层上的第二金属亚层，其中所述第二金属亚层的抗腐蚀性强于所述第一金属亚层的抗腐蚀性；以及
    导电材料层，所述导电材料层覆盖所述金属层的侧表面。
  2. 根据权利要求1所述的显示基板，其中所述显示区包括显示电极，其中所述焊盘的所述导电材料层与所述显示区的所述显示电极同层设置。
  3. 根据权利要求2所述的显示基板，其中所述显示电极包括阳极，其中所述焊盘的所述导电材料层与所述阳极同层设置。
  4. 根据权利要求1所述的显示基板，其中所述显示区包括晶体管，所述晶体管包括源极和漏极，其中所述焊盘的所述金属层与所述显示区的所述源极和漏极同层设置。
  5. 根据权利要求1所述的显示基板，其中所述第一金属亚层包含铝，并且所述第二金属亚层包含钛。
  6. 根据权利要求1所述的显示基板，其中所述金属层还包括第三金属亚层，其中所述第一金属亚层层叠在所述第三金属亚层上，所述第三金属亚层的抗腐蚀性强于所述第一金属亚层的抗腐蚀性。
  7. 根据权利要求6所述的显示基板，其中所述第一金属亚层包含铝，以及所述第二金属亚层和所述第三金属亚层均包含钛。
  8. 根据权利要求1所述的显示基板，其中所述导电材料层是包括第一透明导电氧化物层、金属材料层和第二透明导电氧化物层的多层结构。
  9. 根据权利要求8所述的显示基板，其中所述第一或第二透明导电氧化物层包括下列各项组成的组中的任何一项：氧化铟、氧化锡、氧化锡铟、及其任何两种或更多种的混合物。
  10. 根据权利要求8所述的显示基板，其中所述金属材料层包含银。
  11. 根据权利要求8所述的显示基板，其中所述第一或第二透明导电氧化物层包含氧化锡铟，并且所述金属材料层包含银。
  12. 根据权利要求1所述的显示基板，其中所述焊盘还包括包含金球的异向导电胶，其中所述第二金属亚层与所述包含金球的异向导电胶接触。
  13. 一种显示装置，包括根据权利要求1至12中任何一项所述的显示基板。
  14. 一种用于制备显示基板的方法，所述显示基板包括显示区和在所述显示区之外的焊盘区，所述方法包括以下步骤：
    在焊盘区形成金属层，所述金属层包括第一金属亚层和层叠在所述第一金属亚层上的第二金属亚层，其中所述第二金属亚层的抗腐蚀性强于所述第一金属亚层的抗腐蚀性；
    形成导电材料层，所述导电材料层覆盖所述金属层的侧表面。
  15. 根据权利要求14所述的方法，其中形成导电材料层包括：
    形成预制导电材料层，所述预制导电材料层至少覆盖所述金属层的顶表面和侧表面；
    在所述预制导电材料层上涂布光刻胶；
    用掩模对所述光刻胶进行曝光、显影并暴露所述预制导电材料层的一部分，其中在所述显影后至少保留遮盖所述金属层的侧表面上的预制导电材料层的光刻胶，并且至少去除遮盖所述金属层的一部分顶表面上的预制导电材料层的光刻胶；
    刻蚀所述预制导电材料层的暴露的部分；和
    去除剩余的光刻胶。
  16. 根据权利要求15所述的方法，其中所述方法还包括以下步骤：
    在所述显影后，还保留遮盖所述显示区中的所述预制导电材料层的一部分的光刻胶，从而在去除剩余的光刻胶后，在所述显示区中的所述预制导电材料层的部分形成显示电极。
  17. 根据权利要求16所述的方法，其中所述显示电极包括阳极，以及所述焊盘区的所述导电材料层与所述显示区的所述阳极同时形成。
  18. 根据权利要求14所述的方法，其中所述显示区还包括源极和漏极，以及所述焊盘区的所述金属层和所述显示区的所述源极和漏极同时形成。
  19. 根据权利要求14所述的方法，还包括：在刻蚀所述预制导电材料层的暴露的部分之后，在所述第二金属亚层上形成包含金球的异向导电胶。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112005377B (zh) * 2019-03-26 2023-04-28 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN111682050B (zh) * 2020-06-22 2022-04-01 武汉华星光电半导体显示技术有限公司 触控显示装置及其制造方法
CN111708465B (zh) * 2020-07-08 2023-07-25 武汉华星光电半导体显示技术有限公司 触控显示装置及其制造方法
CN112002251B (zh) * 2020-08-06 2022-05-31 Tcl华星光电技术有限公司 显示面板及其制备方法
CN111916463B (zh) * 2020-08-20 2023-03-24 武汉华星光电技术有限公司 阵列基板、其制备方法及显示面板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101645456A (zh) * 2008-08-06 2010-02-10 奇美电子股份有限公司 电子装置、薄膜晶体管、显示装置及导体接触工艺
CN102496616A (zh) * 2011-11-28 2012-06-13 日月光半导体制造股份有限公司 具有整合被动元件的半导体元件及其制造方法
US20140184937A1 (en) * 2012-12-27 2014-07-03 Lg Display Co., Ltd. Organic light emitting diode display device including touch panel
CN104218058A (zh) * 2013-05-30 2014-12-17 三星显示有限公司 有机发光显示装置
CN105742324A (zh) * 2014-12-29 2016-07-06 乐金显示有限公司 有机发光显示装置及其制造方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2988159B2 (ja) * 1992-11-13 1999-12-06 日本電気株式会社 液晶表示装置
JP2000267595A (ja) * 1999-03-15 2000-09-29 Toshiba Corp 表示装置用アレイ基板の製造方法
US6639265B2 (en) 2000-01-26 2003-10-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the semiconductor device
KR20020083249A (ko) * 2001-04-26 2002-11-02 삼성전자 주식회사 배선의 접촉 구조 및 그의 제조 방법과 이를 포함하는박막 트랜지스터 기판 및 그 제조 방법
JP4036154B2 (ja) 2002-09-12 2008-01-23 セイコーエプソン株式会社 配線構造の製造方法、電気光学装置の製造方法、電気光学装置および電子機器
JP2006047827A (ja) * 2004-08-06 2006-02-16 Mitsubishi Electric Corp 液晶表示装置およびその製造方法
KR101232549B1 (ko) * 2005-12-29 2013-02-12 엘지디스플레이 주식회사 유기 전계 발광 표시 장치 및 이의 제조 방법
BRPI0920935A2 (pt) * 2008-11-26 2019-09-24 Sharp Kk dispositivo de video
JP5624061B2 (ja) * 2009-03-05 2014-11-12 コーニンクレッカ フィリップス エヌ ヴェ 直列接続されたｏｌｅｄ
KR101073552B1 (ko) * 2009-10-09 2011-10-17 삼성모바일디스플레이주식회사 유기 발광 표시 장치 및 그 제조 방법
WO2013011602A1 (ja) * 2011-07-19 2013-01-24 パナソニック株式会社 表示装置、及び表示装置の製造方法
JP2014145857A (ja) 2013-01-28 2014-08-14 Sony Corp 表示装置およびその製造方法、並びに電子機器
EP2966705B1 (en) * 2014-07-11 2018-09-19 LG Display Co., Ltd. Organic light-emitting diode display device and method of fabricating the same
KR102230692B1 (ko) * 2014-07-29 2021-03-19 엘지디스플레이 주식회사 유기 발광 표시 장치 및 유기 발광 표시 장치 제조 방법
US9553156B2 (en) * 2014-07-16 2017-01-24 Lg Display Co., Ltd. Organic light emitting display device and method of manufacturing the same
JPWO2016075791A1 (ja) * 2014-11-13 2017-08-24 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR102377531B1 (ko) 2015-01-23 2022-03-22 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그 제조 방법
KR101879180B1 (ko) 2015-11-16 2018-07-17 엘지디스플레이 주식회사 유기 발광 표시 장치 및 그 제조 방법
CN106338866B (zh) * 2016-10-18 2019-08-02 武汉华星光电技术有限公司 一种液晶面板的焊盘区域结构
KR20180062293A (ko) * 2016-11-30 2018-06-08 엘지디스플레이 주식회사 유기 발광 표시 장치

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101645456A (zh) * 2008-08-06 2010-02-10 奇美电子股份有限公司 电子装置、薄膜晶体管、显示装置及导体接触工艺
CN102496616A (zh) * 2011-11-28 2012-06-13 日月光半导体制造股份有限公司 具有整合被动元件的半导体元件及其制造方法
US20140184937A1 (en) * 2012-12-27 2014-07-03 Lg Display Co., Ltd. Organic light emitting diode display device including touch panel
CN104218058A (zh) * 2013-05-30 2014-12-17 三星显示有限公司 有机发光显示装置
CN105742324A (zh) * 2014-12-29 2016-07-06 乐金显示有限公司 有机发光显示装置及其制造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3457438A4 *

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