WO2018205604A1 - 显示装置、阵列基板及其制造方法 - Google Patents

显示装置、阵列基板及其制造方法 Download PDF

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Publication number
WO2018205604A1
WO2018205604A1 PCT/CN2017/116074 CN2017116074W WO2018205604A1 WO 2018205604 A1 WO2018205604 A1 WO 2018205604A1 CN 2017116074 W CN2017116074 W CN 2017116074W WO 2018205604 A1 WO2018205604 A1 WO 2018205604A1
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Prior art keywords
conductive
pattern
array substrate
reflective metal
layer pattern
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PCT/CN2017/116074
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English (en)
French (fr)
Inventor
白金超
韩笑
桑琦
郭会斌
宋勇志
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/074,185 priority Critical patent/US20210210527A1/en
Publication of WO2018205604A1 publication Critical patent/WO2018205604A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133553—Reflecting elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2203/00—Function characteristic
    • G02F2203/02—Function characteristic reflective

Definitions

  • the present disclosure relates to the field of display technologies, and in particular to a display device, an array substrate, and a method of fabricating an array substrate.
  • Liquid crystal displays generally include two types of transmissive liquid crystal displays and reflective liquid crystal displays.
  • the array substrate of the liquid crystal display generally includes a base substrate and thin film transistors, peripheral circuits, via holes, and the like formed over the substrate. Vias can connect conductive structures located in different layers. However, for the existing array substrate, contact failure at the via hole often occurs.
  • a method of fabricating an array substrate includes the steps of: forming a thin film transistor and a peripheral circuit; forming a passivation layer covering at least the thin film transistor and the peripheral circuit; forming a passivation through And exposing a portion of the first via of the drain of the thin film transistor, and a second via extending through the passivation layer and exposing a portion of the peripheral circuit; forming a first conductive on the passivation layer a layer pattern, the first conductive layer pattern covers the first via hole and the second via hole; forming a pattern of a reflective metal layer and a second conductive layer pattern on the first conductive layer pattern, the second conductive layer A layer covers the second via.
  • forming the first conductive layer pattern, the second conductive layer pattern, and the pattern of the reflective metal layer includes: forming a first conductive film on the passivation layer; and the first conductive film Forming a reflective metal film thereon; patterning the reflective metal film to form a reflective metal layer pattern; forming a second conductive film covering at least the reflective metal layer pattern and the first conductive film; Forming a film and the second conductive film to retain a portion of the first conductive film covered by the reflective metal layer pattern, And a portion of the first conductive film covering the second via and a portion of the second conductive film.
  • the patterning process of the first conductive film and the second conductive film includes: patterning the second conductive film to remove the second layer not covering the second via hole a portion of the conductive film; a patterning process of the first conductive film to remove a portion of the first conductive film that is not covered by the reflective metal layer pattern and that does not cover the second via.
  • the first conductive layer pattern includes a first conductive sub-pattern and a second conductive sub-pattern, and the first conductive sub-pattern is connected to a drain of the thin film transistor via the first via, The second conductive sub-pattern is connected to a common pad of the peripheral circuit via the second via.
  • the first conductive layer pattern and the second conductive layer pattern are made of the same material.
  • both the first conductive layer pattern and the second conductive layer pattern comprise a transparent conductive material.
  • the reflective metal layer pattern and the first conductive sub-pattern overlap each other and cover the first via.
  • the second conductive sub-pattern and the second conductive layer pattern overlap each other and cover the second via.
  • the reflective metal layer forms part of a pixel electrode of the array substrate.
  • an array substrate comprising: a substrate substrate;
  • a thin film transistor disposed on the base substrate; a peripheral circuit disposed on the base substrate; a passivation layer covering at least the thin film transistor and the peripheral circuit; and a first via extending through the passivation And exposing a portion of the drain of the thin film transistor; a second via penetrating the passivation layer and exposing a portion of the peripheral circuit; a first conductive layer pattern disposed on the passivation layer and covering the substrate a first via hole and a second via hole; a second conductive layer pattern disposed on the passivation layer and covering the second via hole; and a reflective metal layer pattern disposed on the first conductive layer pattern And covering the first via.
  • the first conductive pattern and the second conductive pattern are made of the same material.
  • both the first conductive pattern and the second conductive pattern comprise a transparent conductive material.
  • the first conductive pattern includes a first sub-conductive pattern and a second sub-guide An electrical pattern, the first sub-conductive pattern is connected to the drain of the thin film transistor via the first via, and the second sub-conductive pattern is connected to a common pad of the peripheral circuit via the second via.
  • the reflective metal layer pattern and the first conductive sub-pattern overlap each other and cover the first via.
  • the second conductive sub-pattern and the second conductive layer pattern overlap each other and cover the second via, and the reflective metal layer constitutes a portion of the pixel electrode of the array substrate.
  • a further embodiment of the present disclosure also provides a display device that can include the array substrate of any of the preceding embodiments.
  • FIG. 1 is a flow chart of a method of fabricating an array substrate according to an embodiment of the present disclosure.
  • FIG. 2 is a flow chart involved in the process of forming a first conductive layer pattern, a second conductive layer pattern, and a reflective metal layer pattern in the method of fabricating an array substrate according to an embodiment of the present disclosure.
  • 3 to 11 are diagrams for schematically illustrating respective steps in a method of fabricating an array substrate provided according to an embodiment of the present disclosure.
  • relative terms such as “upper” and “lower” are used to describe the relative relationship of one component of the icon to another component, but these terms are used in this specification for convenience only, and these terms are Based on the directions of the examples described in the figures. It will be understood that if the device of the icon is flipped upside down, the component described as “on” will become the component “below”.
  • a structure is "on” another structure, it may mean that a structure is integrally formed on another structure, or that a structure is “directly” disposed on another structure, or that a structure is “indirectly” disposed through another structure. Other structures.
  • the reflective liquid crystal display can reflect the light entering the inside, thereby realizing the display function as a light source required for displaying images, and can save a special backlight, which is beneficial to reduce power consumption.
  • the inventors of the present application have found that the reflective layer in the existing array substrate usually covers the metal exposed by the via hole, such as the drain metal. When the reflective layer pattern is formed by the etching process, the via hole is easily exposed. The metal is etched, making it difficult to achieve a normal electrical connection by the structure of the different layers electrically connected via vias, i.e., poor contact at the vias.
  • the conductive protective layer at the via climbing step may be etched, and the same is utilized.
  • the structure of the different layers of the via connection is difficult to be electrically connected normally, and therefore, the contact failure at the via hole is also caused.
  • an exemplary embodiment of the present disclosure first provides a method of fabricating an array substrate. As shown in FIG. 1 , a method of fabricating an array substrate according to an embodiment of the present disclosure may include the following steps:
  • Step S110 forming a thin film transistor and a peripheral circuit on the base substrate
  • Step S120 forming a passivation layer covering at least the thin film transistor and the peripheral circuit
  • Step S130 forming a first via hole penetrating the passivation layer and exposing a portion of the drain of the thin film transistor, and a second through the passivation layer and exposing a portion of the peripheral circuit Via hole
  • Step S140 forming a pattern of the first conductive layer on the passivation layer, the first conductive layer covering the first via and the second via;
  • Step S150 forming a pattern of a reflective metal layer and a pattern of a second conductive layer on the first conductive layer, the second conductive layer covering the second via.
  • the metal exposed by the first via and the second via can be protected by the first conductive layer to prevent the first via and Etching of the metal exposed by the second via.
  • the second conductive layer is further formed on the first conductive layer, that is, the second conductive layer further covers the second via hole on the basis that the first conductive layer covers the second via hole, so even if the second conductive layer
  • the first conductive layer at the climbing of the hole is etched, and the second conductive layer can also be used to achieve good contact of the second via. Thereby, the contact failure between the first via hole and the second via hole due to the formation of the reflective metal layer can be avoided, which is advantageous for improving the yield.
  • step S110 as shown in FIG. 3, a thin film transistor and a peripheral circuit are formed on the base substrate.
  • a thin film transistor can be formed in the display region of the base substrate 1, and a peripheral circuit can be formed in the non-display area thereof.
  • the thin film transistor may include a gate electrode 2, a gate insulating layer 3, an active layer 4, a source 5 and a drain 6, and the like; the peripheral circuit may include a common pad 7 for connection with a driving circuit board, etc.;
  • the common pad 7 can be formed by one patterning process and located in the same layer, and at the same time, a common electrode can be formed together.
  • the patterning process may be a classical mask process including steps of photoresist coating, exposure, development, etching, photoresist stripping, etc., or a mask process using ground stripping technology, or printing, Other processes such as printing may be performed as long as the gate 2 and the common pad 7 can be formed, and the present invention does not limit the patterning process herein.
  • step S120 as shown in FIG. 4, a passivation layer 8 covering at least the thin film transistor and the peripheral circuit is formed.
  • a passivation layer 8 may be formed on the base substrate 1 on which the thin film transistor and the peripheral circuit are formed, the passivation layer 8 covering the source 5, the drain 6 and the peripheral circuit of the thin film transistor, thereby providing protection effect.
  • the passivation layer 8 may be formed of an insulating material, and the manner in which the passivation layer 8 is formed includes, but is not limited to, deposition, coating, sputtering, and the like.
  • step S130 as shown in FIG. 5, the exposed portion is formed through the passivation layer 8 a first via 9 of a drain of the thin film transistor, and a second via 10 penetrating the passivation layer 8 and exposing a portion of the peripheral circuit.
  • the first via 9 may be a via located in the display area and exposing the drain 6 of the thin film transistor, and the first via 9 may penetrate the passivation layer 8 to expose a portion of the drain 6;
  • the second via 10 may be a via located in the non-display area and exposing a portion of the common pad 7 of the peripheral circuit, and the second via 10 may penetrate the passivation layer 8 and the gate insulating layer 3 to expose the common pad 7. portion.
  • step S140 as shown in FIG. 6 to FIG. 11, a pattern 11 of a first conductive layer is formed on the passivation layer 8, and the first conductive layer 11 covers the first via hole 9 and the second via hole 10 .
  • the first conductive layer 11 can be connected to the drain 6 of the thin film transistor through the first via 9, that is, the first conductive layer 11 can extend along the inner wall of the first via 9 and cover the first via 9 The exposed drain 6; at the same time, the first conductive layer 11 can also be connected to the common pad 7 of the peripheral circuit through the second via 10, that is, the first conductive layer 10 also extends along the inner wall of the second via 10 and covers The common via 7 exposed by the second via 10 is.
  • the first conductive layer 11 may be made of a transparent conductive material, such as indium tin oxide. Of course, the first conductive layer 11 may also be made of other conductive materials, which will not be enumerated here.
  • step S150 as shown in FIG. 11, a pattern 12 of a reflective metal layer and a pattern 13 of a second conductive layer are formed on the pattern 11 of the first conductive layer, the second conductive layer 13 covering the second Via 10.
  • the pattern 12 of the reflective metal layer may directly cover the pattern 11 of the first conductive layer and may be located in the display area to reflect light in the display area.
  • the material of the reflective metal layer includes a high reflectivity metal or alloy material such as aluminum, silver, molybdenum aluminum alloy or aluminum bismuth alloy.
  • the material of the reflective metal layer 12 is not limited to the materials listed above, and other materials may also be used, which will not be enumerated here.
  • the pattern 12 of the reflective metal layer may be the same as the pattern of the pixel electrode, that is, the reflective metal layer 12 may be a part of the pixel electrode, and the reflective metal layer 12 may cover the first via hole 9 and pass through the first conductive layer 11 and the film.
  • the drain 6 of the transistor is electrically connected.
  • the formed second conductive layer may cover the reflective metal layer pattern 12 and the unreflected metal layer pattern 12 A region of the first conductive layer 11 and a second conductive layer may be connected to the common pad 7 through the first conductive layer 11.
  • the second conductive layer can also cover other regions, which is not limited herein.
  • the second conductive layer may be formed of the same transparent conductive material as the first conductive layer, for example, indium tin oxide, which is advantageous for simplifying the manufacturing process.
  • the second conductive layer 13 may also be made of other materials, which is not limited herein.
  • the pattern 11 of the first conductive layer, the pattern 13 of the second conductive layer, and the pattern 12 of the reflective metal layer may be formed by the following steps:
  • Step S161 as shown in FIG. 6, a first conductive film 110 is formed on the passivation layer 8.
  • the first conductive film 110 is formed, including but not limited to deposition, coating, sputtering, and the like; the material of the first conductive film 110 may be a transparent conductive material such as indium tin oxide or other materials.
  • Step S162 as shown in FIG. 7, a reflective metal film 120 is formed on the first conductive film.
  • the reflective metal film 120 may cover the first conductive film 110; the manner of forming the reflective metal film 120 includes, but is not limited to, deposition, coating, sputtering, etc.; the material of the reflective metal film 120 may include the above High reflectivity metal or alloy materials are not described in detail herein.
  • Step S163 as shown in FIG. 8, the reflective metal film 120 is patterned to form a pattern 12 of the reflective metal layer.
  • the patterning process in step S163 may include a mask process classical in the art, which may include steps of photoresist coating, exposure, development, etching, photoresist stripping, etc., of course, may also be utilized.
  • the masking process of the ground stripping technique is not limited herein as long as a specific region of the reflective metal film 120 can be removed to form the pattern 12 of the reflective metal layer.
  • Step S164 as shown in FIG. 9, a second conductive film 130 covering at least the pattern 12 of the reflective metal layer and the first conductive film 110 is formed.
  • the manner of forming the second conductive film 130 may refer to a manner of forming the first conductive film 110, including but not limited to deposition, coating, sputtering, etc., and the material of the second conductive film 130 may be The material of the first conductive film 110 is the same, including but not limited to a transparent conductive material such as indium tin oxide.
  • Step S165 as shown in FIG. 10 and FIG. 11, the first conductive film 110 and the second conductive film 130 are patterned to retain a portion of the first conductive film 110 covered by the reflective metal layer pattern 12. And covering a portion of the first conductive film 110 and the second conductive film 130 of the second via hole 10 to obtain a first conductive layer pattern 11 and a second conductive layer pattern Shape 13.
  • the patterning process of the first conductive film 110 and the second conductive film 130 may include the following steps: as shown in FIG. 10, the second conductive film 130 is patterned to remove Covering a portion of the second conductive film 130 of the second via 10 to obtain a second conductive layer pattern 13; and as shown in FIG. 11, performing photolithography on the first conductive film 110, the removal is not performed A portion of the first conductive film 110 covering the second via hole 10 is covered by the reflective metal layer pattern 12 to obtain a first conductive layer pattern 11.
  • the reflective metal layer pattern 12 may be exposed in the display region; in the non-display region, only the second conductive film 130 is left to cover the second via hole 10 A portion of the second conductive layer pattern 13 is formed. If the first conductive film 110 at the climbing surface of the second via hole 10 is etched or damaged when the reflective metal layer pattern 12 is formed, the second conductive layer pattern 13 covers the second via hole 10 to ensure the second via hole. The contact at 10 was good.
  • the patterning process in the above step S165 may be a classical mask process conventional in the art, which may include steps of photoresist coating, exposure, development, etching, photoresist stripping, etc., of course, may also be stripped off using ground.
  • the masking process of the technology is not limited herein as long as the portion of the second conductive film 130 that does not cover the second via hole 10 can be removed to form the second conductive layer pattern 13, and the first conductive film 110 is removed from the first conductive film 110.
  • the metal layer pattern 12 may cover and cover the portion of the second via hole 10.
  • the first conductive film 110 and the second conductive film 130 are formed of the same material, the same etching solution can be used when the above-mentioned classical mask process is employed, which is advantageous for simplifying the process and improving work efficiency.
  • the above is only an exemplary description of the manner in which the first conductive layer pattern 11 , the second conductive layer pattern 13 , and the reflective metal layer pattern 12 are formed.
  • printing and printing may also be adopted.
  • the other process forms the pattern 11 of the first conductive layer, the pattern 13 of the second conductive layer, and the reflective metal layer pattern 12.
  • the first conductive layer 11 may be formed on the passivation layer 8 by a printing process, and then the reflective metal layer 12 and the second conductive layer 13 may be separately formed on the first conductive layer 11. Therefore, the present disclosure does not constitute a special limitation on the process of forming the first conductive layer pattern 11, the second conductive layer pattern 13, and the reflective metal layer pattern 12.
  • the formed first conductive layer pattern 11 can include a first conductive sub-pattern and a second conductive sub-pattern, and the first conductive sub-pattern is leaked through the first via 9 and the thin film transistor.
  • the pole 6 is connected, and the second conductive sub-pattern is connected to the second via 10
  • the common pads 7 of the peripheral circuits are connected.
  • the formed reflective metal layer pattern 12 may overlap the first conductive sub-pattern and cover the first via 9
  • the second conductive sub-pattern and the second conductive layer pattern 13 may overlap each other and cover the second via 10.
  • a further embodiment of the present disclosure provides an array substrate, which may include a display area and a non-display area.
  • the array substrate of the embodiment may include a substrate substrate 1, a thin film transistor, and a peripheral circuit.
  • a passivation layer 8 a first via 9, a second via 10, a first conductive layer pattern, a second conductive layer pattern, and a reflective metal layer pattern.
  • the base substrate 1 may have a display area and a non-display area, and the display area of the base substrate 1 may correspond to an area of the array substrate for displaying an image, and the non-display area of the base substrate 1 may be used for displaying an image with the array substrate.
  • the area corresponds; the non-display area may be located at the periphery of the display area.
  • a thin film transistor may be disposed in the display region, and the thin film transistor may include a gate 2, a gate insulating layer 3, an active layer 4, a source 5 and a drain 6, etc., a thin film transistor
  • the thin film transistor may include a gate 2, a gate insulating layer 3, an active layer 4, a source 5 and a drain 6, etc., a thin film transistor
  • a peripheral circuit may be disposed in the non-display area, and the peripheral circuit may include a common pad 7 for connecting with the driving circuit board, and may also include other structures, which are not described herein again.
  • the gate 2 and the common pad 7 may be disposed in the same layer and may be formed on the substrate 1 by one patterning process, but it should not be understood that the gate 2 and the common pad 7 can only be in the same layer. Settings, other settings can also be used.
  • the passivation layer 8 may cover the above-described thin film transistor and peripheral circuits, and the passivation layer 8 may be formed of an insulating material to protect the thin film transistor and the peripheral circuit.
  • the first via 9 may be a via for realizing the electrical connection between the drain 6 of the thin film transistor and other components, and may be located in the display region and penetrate the passivation layer 8 to expose the thin film transistor.
  • the first via 9 is not limited to the above exposed drain
  • the via hole of 6 may also be other via holes in the display region.
  • the first via hole may also be a via hole exposing the source of the thin film transistor, and the present disclosure does not constitute a limitation on the first via hole.
  • the second via 10 can implement a via for electrically connecting the common pad 7 of the peripheral circuit to other components, which can be located in the non-display region and penetrates the passivation layer 8 and can further penetrate the gate.
  • the insulating layer 3 is exposed to expose the above common pad 7.
  • the second via 10 is not limited to the above-mentioned via which exposes the common pad 7, and may also be other vias in the non-display area, and the present disclosure does not constitute a special limitation on the second via.
  • the first conductive layer pattern may be formed by referring to the embodiment of the method for manufacturing the array substrate.
  • the first conductive layer pattern may include a portion of the first conductive film 110 that is reserved in the display area and the non-display area.
  • the second conductive pattern may be formed by referring to an embodiment of the method for manufacturing the array substrate, and the second conductive layer pattern may be a portion where the second conductive film 130 is retained in the non-display area, and the second The conductive layer pattern may cover the second via hole 10, that is, the second conductive layer pattern 13 and the first conductive layer layer pattern 11 may coincide with each other in the non-display area.
  • the first conductive layer pattern 11 and the second conductive layer pattern 13 may be formed of the same transparent conductive material, such as indium tin oxide or the like. If the first conductive layer pattern 11 and the second conductive layer pattern 13 are made of the same material, their patterns may be a unitary structure.
  • the reflective metal layer pattern may cover the first conductive layer pattern, and may overlap with the first conductive pattern and may be electrically conductive, so that the reflective metal layer pattern and the first conductive layer pattern may serve as pixel electrodes.
  • the reflective metal layer pattern also reflects light to provide a source of light for imaging the array substrate.
  • a further embodiment of the present disclosure further provides a display device, which may include the array substrate described in any of the above embodiments.
  • the array substrate can be manufactured by using the method for manufacturing the array substrate described in the above embodiments, and the first via hole 9 is protected by the first conductive film pattern to prevent Etching the metal exposed by the first via hole 9 when forming the reflective metal layer pattern; at the same time, consolidating and reinforcing the electrical connection at the second via hole 10 by using the second conductive layer pattern to compensate for the formation of the reflective metal layer pattern
  • the etching of the metal exposed by the second via 10 and the climbing of the second via 10 may occur. Thereby, the contact failure between the first via hole 9 and the second via hole 10 due to the formation of the reflective metal layer pattern can be avoided or reduced, which is advantageous for improving the yield.

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Abstract

提供一种阵列基板的制造方法，包括：（S110）形成薄膜晶体管和外围电路；（S120）形成至少覆盖薄膜晶体管以及外围电路的钝化层（8）；（S130）形成贯穿钝化层且暴露出部分薄膜晶体管的漏极（6）的第一过孔（9），以及贯穿钝化层且暴露出部分外围电路的第二过孔（10）；（S140）在钝化层上形成包括第一导电层的图形（11），第一导电层覆盖第一过孔和第二过孔；（S150）在第一导电层上形成包括反射金属层的图形（12）和包括第二导电层的图形（13），第二导电层覆盖第二过孔。

Description

显示装置、阵列基板及其制造方法
相关申请的交叉引用
本申请要求于2017年5月12日向中国专利局提交的专利申请201710335389.9的优先权利益，并且在此通过引用的方式将该在先申请的内容并入本文。
技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示装置、阵列基板及阵列基板的制造方法。
背景技术
目前，在显示装置领域，薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，简称TFT-LCD)因其具有体积小、功耗低等特点，获得了广泛的应用。液晶显示器一般包括透射式液晶显示器和反射式液晶显示器两种类型。液晶显示器的阵列基板通常包括衬底基板以及形成在衬底基板上方的薄膜晶体管、外围电路和过孔等。过孔可以将位于不同层的导电结构相连接。然而，对于现有的阵列基板，经常发生过孔处的接触不良。
发明内容
根据本公开的一个方面，提供一种阵列基板的制造方法，包括以下步骤：形成薄膜晶体管和外围电路；形成至少覆盖所述薄膜晶体管以及所述外围电路的钝化层；形成贯穿所述钝化层且暴露出部分所述薄膜晶体管的漏极的第一过孔，以及贯穿所述钝化层且暴露出部分所述外围电路的第二过孔；在所述钝化层上形成第一导电层图形，所述第一导电层图形覆盖所述第一过孔和第二过孔；在所述第一导电层图形上形成反射金属层的图形和第二导电层图形，所述第二导电层覆盖所述第二过孔。
在一些实施例中，形成第一导电层图形、所述第二导电层图形和所述反射金属层的图形包括：在所述钝化层上形成第一导电膜；在所述第一导电膜上形成反射金属膜；对所述反射金属膜进行构图工艺，形成反射金属层图形；形成至少覆盖所述反射金属层图形和所述第一导电膜的第二导电膜；对所述第一导电膜和所述第二导电膜进行构图工艺，以保留被所述反射金属层图形覆盖的所述第一导电膜的部分， 以及覆盖所述第二过孔的所述第一导电膜的部分和所述第二导电膜的部分。
在一些实施例中，对所述第一导电膜和所述第二导电膜进行构图工艺包括：对所述第二导电膜进行构图工艺，去除未覆盖所述第二过孔的所述第二导电膜的部分；对所述第一导电膜进行构图工艺，去除未被所述反射金属层图形覆盖且未覆盖所述第二过孔的所述第一导电膜的部分。
在一些实施例中，所述第一导电层图形包括第一导电子图形和第二导电子图形，第一导电子图形经由所述第一过孔与所述薄膜晶体管的漏极连接，所述第二导电子图形经由所述第二过孔与所述外围电路的公共焊盘连接。
在一些实施例中，第一导电层图形和所述第二导电层图形的材质相同。
在一些实施例中，第一导电层图形和第二导电层图形均包括透明导电材料。
在一些实施例中，反射金属层图形和第一导电子图形彼此重叠并覆盖所述第一过孔。
在一些实施例中，所述第二导电子图形和所述第二导电层图形彼此重叠并覆盖所述第二过孔。
在一些实施例中，反射金属层构成阵列基板的像素电极的一部分。
本公开的另一方面提供了一种阵列基板，包括：衬底基板；
薄膜晶体管，设于所述衬底基板上；外围电路，设于所述衬底基板上；钝化层，至少覆盖所述薄膜晶体管和所述外围电路；第一过孔，贯穿所述钝化层并暴露出部分所述薄膜晶体管的漏极；第二过孔，贯穿所述钝化层并暴露出部分所述外围电路；第一导电层图形，设于所述钝化层上并覆盖所述第一过孔和所述第二过孔；第二导电层图形，设于所述钝化层上并覆盖所述第二过孔；反射金属层图形，设置于所述第一导电层图形上并覆盖所述第一过孔。
在一些实施例中，第一导电图形和第二导电图形的材质相同。
在一些实施例中，第一导电图形和第二导电图形均包括透明导电材料。
在一些实施例中，第一导电图形包括第一子导电图形和第二子导 电图形，第一子导电图形经由所述第一过孔与所述薄膜晶体管的漏极连接，所述第二子导电图形经由所述第二过孔与所述外围电路的公共焊盘连接。
在一些实施例中，反射金属层图形和第一导电子图形彼此重叠并覆盖所述第一过孔。
在一些实施例中，第二导电子图形和所述第二导电层图形彼此重叠并覆盖所述第二过孔，反射金属层构成阵列基板的像素电极的一部分。
本公开的另外的实施例还提供了一种种显示装置，其可包括前述实施例中任一实施例所述的阵列基板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图示出了本公开的一些实施例，它们与说明书一起用于解释本公开的原理。下面描述中的附图仅仅是本公开的部分实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的阵列基板的制造方法的流程图。
图2为本公开实施例提供的阵列基板的制造方法中形成第一导电层图形、第二导电层图形和反射金属层图形过程中涉及的流程图。
图3-图11用于示意性地图示根据本公开实施例提供的阵列基板的制造方法中的各个步骤。
具体实施方式
现在，将参考附图更全面地描述示例性实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的示例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例性实施例的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，在实践本公开的技术方案时，可以省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾 夺主而使得本公开的各方面变得模糊。
本说明书中使用相对性的用语，例如“上”、“下”，来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便的目的，这些术语是基于附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则被描述为在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”和“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”和“第二”等用于区分不同的对象，不是对其所指代的对象的数量限制。
反射式液晶显示器可对进入其内部的光线进行反射，以此作为显示图像所需的光源实现显示功能，可以省去专门的背光源，有利于降低功耗。本申请的发明人发现，已有的阵列基板中的反射层通常会覆盖由过孔露出的金属，例如漏极金属等，在通过刻蚀工艺形成反射层图形时，容易使过孔所露出的金属被刻蚀，导致利用过孔电连接的不同层的结构难以实现正常的电连接，即，出现过孔处的接触不良。同时，即便是在过孔所漏出的金属上覆盖导电保护层，但是，在为了形成反射层图形的刻蚀过程中，还可能导致过孔爬坡处的导电保护层被刻蚀，同样使得利用过孔连接的不同层的结构难以正常电连接，因此，同样造成了过孔处的接触不良。
基于上述问题，本公开的示例性实施例首先提供了一种阵列基板的制造方法，如图1所示，根据本公开的实施例的阵列基板的制造方法可以包括以下步骤：
步骤S110、在衬底基板上形成薄膜晶体管和外围电路；
步骤S120、形成至少覆盖所述薄膜晶体管以及所述外围电路的钝化层；
步骤S130、形成贯穿所述钝化层且暴露部分所述薄膜晶体管的漏极的第一过孔，以及贯穿所述钝化层且暴露部分所述外围电路的第二 过孔；
步骤S140、在所述钝化层上形成第一导电层的图形，所述第一导电层覆盖所述第一过孔和第二过孔；
步骤S150、在所述第一导电层上形成反射金属层的图形和第二导电层的图形，所述第二导电层覆盖所述第二过孔。
对于本实施例提供的阵列基板的制造方法，在形成反射金属层时，可通过第一导电层对由第一过孔和第二过孔露出的金属进行保护，防止出现对第一过孔和第二过孔所露出的金属的刻蚀。同时，由于在第一导电层上还形成了第二导电层，即，在第一导电层覆盖第二过孔的基础上，第二导电层进一步覆盖第二过孔，因此，即使第二过孔的爬坡处的第一导电层被刻蚀，也可利用第二导电层来实现第二过孔的接触良好。由此，可避免因形成反射金属层而造成第一过孔和第二过孔处的接触不良，有利于提高良品率。
下面，参照图3～图11，将对本示例性实施例中的阵列基板的制造方法的各步骤进行进一步的说明。
在步骤S110中，如图3所示，在衬底基板上形成薄膜晶体管和外围电路。可以在衬底基板1的显示区形成薄膜晶体管，在其非显示区形成外围电路。
薄膜晶体管可以包括栅极2、栅极绝缘层3、有源层4、源极5和漏极6等；外围电路可以包括用于与驱动电路板连接的公共焊盘7等；栅极2和公共焊盘7可以通过一次构图工艺形成并位于同一层，同时，还可一并形成公共电极。该构图工艺可以是包括光刻胶涂敷、曝光、显影、刻蚀、光刻胶剥离等步骤的经典的掩膜工艺，也可以是采用离地剥离技术的掩膜工艺，还可以是打印、印刷等其它工艺，只要能形成栅极2和公共焊盘7即可，本发明对这里的构图工艺不作限制。
在步骤S120中，如图4所示，形成至少覆盖所述薄膜晶体管以及所述外围电路的钝化层8。
在本实施例中，可在形成有薄膜晶体管和外围电路的衬底基板1上形成钝化层8，该钝化层8覆盖薄膜晶体管的源极5、漏极6和外围电路，从而提供保护作用。钝化层8可由绝缘材质形成，形成钝化层8的方式包括但不限于沉积、涂敷、溅射等。
在步骤S130中，如图5所示，形成贯穿所述钝化层8且暴露部分 所述薄膜晶体管的漏极的第一过孔9，以及贯穿所述钝化层8且暴露部分所述外围电路的第二过孔10。
在本实施例中，第一过孔9可以是位于上述显示区且暴露部分薄膜晶体管的漏极6的过孔，第一过孔9可贯穿上述钝化层8以露出部分漏极6；第二过孔10可以是位于上述非显示区且暴露外围电路的公共焊盘7的一部分的过孔，第二过孔10可贯穿钝化层8和栅极绝缘层3以露出公共焊盘7的一部分。形成上述第一过孔9和第二过孔10的工艺可参考本领域中形成过孔的通常做法，在此不再赘述。以上仅为对第一过孔9和第二过孔10的示例性说明，并不构成对第一过孔9和第二过孔10的限制，第一过孔9和第二过孔10也可以是其它过孔。
在步骤S140中，如图6～图11，在所述钝化层8上形成第一导电层的图形11，所述第一导电层11覆盖所述第一过孔9和第二过孔10。
在本实施例中，第一导电层11可通过第一过孔9与薄膜晶体管的漏极6连接，即第一导电层11可沿第一过孔9的内壁延伸并覆盖第一过孔9露出的漏极6；同时，第一导电层11还可通过第二过孔10与外围电路的公共焊盘7连接，即第一导电层10还沿着第二过孔10的内壁延伸并覆盖第二过孔10露出的公共焊盘7。第一导电层11可以由透明导电材料制成，例如氧化铟锡，当然，第一导电层11也可以采用其它导电材料，在此不再一一列举。
在步骤S150中，如图11所示，在所述第一导电层的图形11上形成反射金属层的图形12和第二导电层的图形13，所述第二导电层13覆盖所述第二过孔10。
在本实施例中，反射金属层的图形12可直接覆盖在第一导电层的图形11上，并可位于上述的显示区，以在显示区内对光线进行反射。反射金属层的材料包括高反射率的金属或合金材料，例如铝、银、钼铝合金或铝钕合金等。当然，反射金属层12的材料并不限定于以上列举的材料，其还可以采用其它材料，在此不再一一列举。反射金属层的图形12可与像素电极的图形相同，也就是说，可将反射金属层12作为像素电极的一部分，反射金属层12可覆盖第一过孔9并经由第一导电层11与薄膜晶体管的漏极6电连接。
如图9所示，在形成第二导电层图形13的过程中，所形成的第二导电层可覆盖反射金属层图形12以及未被反射金属层图形12覆盖的 第一导电层11的区域，且第二导电层可通过第一导电层11与公共焊盘7连接。当然，第二导电层还可以覆盖其它区域，在此不作限制。第二导电层可采用与第一导电层相同的透明导电材料形成，例如氧化铟锡，有利于简化制造工艺，当然，第二导电层13也可以采用其它材料，在此不作限制。
在本公开的实施例中，如图2所示，第一导电层的图形11、第二导电层的图形13和反射金属层的图形12可通过以下步骤形成：
步骤S161、如图6所示，在钝化层8上形成第一导电膜110。
在实施例中，形成第一导电膜110包括但不限于沉积、涂敷、溅射等多种方式；第一导电膜110的材质可为氧化铟锡等透明导电材料或其它材料。
步骤S162、如图7，在所述第一导电膜上形成反射金属膜120。
在本实施例中，反射金属膜120可覆盖第一导电膜110；形成反射金属膜120的方式包括但不限于沉积、涂敷、溅射等；反射金属膜120的材质可包括上文所述的高反射率的金属或合金材料，在此不再详述。
步骤S163、如图8，对所述反射金属膜120进行构图工艺，形成反射金属层的图形12。
在本实施例中，步骤S163中的构图工艺可以包括本领域经典的掩膜工艺，其可以包括光刻胶涂敷、曝光、显影、刻蚀、光刻胶剥离等步骤，当然也可以是利用离地剥离技术的掩膜工艺，在此不做限制，只要能去除反射金属膜120的特定区域，以形成反射金属层的图形12即可。
步骤S164、如图9，形成至少覆盖所述反射金属层的图形12和所述第一导电膜110的第二导电膜130。
在本实施方式中，形成第二导电膜130的方式可参考形成第一导电膜110的方式，包括但不限于沉积、涂敷、溅射等多种方式，第二导电膜130的材质可与与第一导电膜110的材质相同，包括但不限于氧化铟锡等透明导电材料。
步骤S165，如图10和图11，对所述第一导电膜110和所述第二导电膜130进行构图工艺，以保留被所述反射金属层图形12覆盖的第一导电膜110的部分，以及覆盖所述第二过孔10的第一导电膜110和所述第二导电膜130的部分，得到第一导电层图形11和第二导电层图 形13。
在本实施方式中，对所述第一导电膜110和所述第二导电膜130进行构图工艺可以包括以下步骤：如图10所示，对所述第二导电膜130进行构图工艺，去除不覆盖所述第二过孔10的第二导电膜130的部分，得到第二导电层图形13；以及如图11所示，对所述第一导电膜110进行光刻工艺，去除未被所述反射金属层图形12覆盖且未覆盖所述第二过孔10的所述第一导电膜110的部分，得到第一导电层图形11。
在去除未覆盖第二过孔10的第二导电膜130后，在显示区内，至少可露出反射金属层图形12；在非显示区内，仅保留第二导电膜130覆盖第二过孔10的部分，形成第二导电层图形13。若第二过孔10的爬坡处的第一导电膜110在形成反射金属层图形12时被刻蚀或损伤，第二导电层图形13对第二过孔10的覆盖可保证第二过孔10处的接触良好。
上述步骤S165中的构图工艺可以是本领域惯用的经典的掩膜工艺，其可以包括光刻胶涂敷、曝光、显影、刻蚀、光刻胶剥离等步骤，当然也可以是利用离地剥离技术的掩膜工艺，在此不做限制，只要能去除第二导电膜130中未覆盖第二过孔10的部分以形成第二导电层图形13、以及去除第一导电膜110中未被反射金属层图形12覆盖且未覆盖第二过孔10的部分即可。特别地，若第一导电膜110和第二导电膜130采用相同材质形成，则在采用上述经典的掩膜工艺时，可使用同一种刻蚀液，有利于简化工艺，提高工作效率。
需要说明的是，以上仅为形成第一导电层图形11、第二导电层图形13和反射金属层图形12的方式的示例性说明，在本公开的其它实施方式中，还可以采用打印、印刷等其它工艺形成上述的第一导电层的图形11、第二导电层的图形13和反射金属层图形12。举例而言，可通过打印工艺在钝化层8上先形成第一导电层11，再在第一导电层11上分别打印形成反射金属层12和第二导电层13。因此，本公开不构成对形成第一导电层图形11、第二导电层图形13和反射金属层图形12的过程的特殊限制。
从本公开实施例可以理解到的是，所形成的第一导电层图形11可包括第一导电子图形和第二导电子图形，第一导电子图形经由第一过孔9与薄膜晶体管的漏极6连接，第二导电子图形经由第二过孔10与 外围电路的公共焊盘7连接。此外，所形成的反射金属层图形12可与第一导电子图形彼此重叠并覆盖第一过孔9，第二导电子图形和第二导电层图形13可彼此重叠并覆盖第二过孔10。需要说明的是，尽管在附图中以特定顺序描述了本公开实施例中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。在一些实施例中，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
本公开的另外的实施例提供了一种阵列基板，该阵列基板可包括显示区和非显示区，如图11所示，本实施例的阵列基板可以包括衬底基板1、薄膜晶体管、外围电路、钝化层8、第一过孔9、第二过孔10、第一导电层图形、第二导电层图形和反射金属层图形。
衬底基板1可以具有显示区和非显示区，衬底基板1的显示区可与阵列基板用于显示图像的区域对应，衬底基板1的非显示区可与阵列基板非用于显示图像的区域对应；所述非显示区可位于所述显示区的外围。
在本公开的实施例中，薄膜晶体管可设于所述显示区内，该薄膜晶体管可以包括栅极2、栅极绝缘层3、有源层4、源极5和漏极6等，薄膜晶体管的详细构成可参考现有技术中的薄膜晶体管，在此不再赘述。
在本实施方式中，外围电路可设于所述非显示区，所述外围电路可包括用于与驱动电路板连接的公共焊盘7，还可以包括其它结构，在此不再赘述。
需要说明的是，上述栅极2和公共焊盘7可同层设置，可通过一次构图工艺形成在衬底基板1上，但不应理解为上述栅极2和公共焊盘7只能同层设置，还可以采用其它设置方式。
在本实施方式中，钝化层8可覆盖上述薄膜晶体管和外围电路，且钝化层8可以采用绝缘材料形成以便对薄膜晶体管和外围电路进行保护。
在本实施方式中，第一过孔9可以是用于实现薄膜晶体管的漏极6与其他元件的电连接的过孔，其可位于显示区内并贯穿上述钝化层8，以露出薄膜晶体管的漏极6。当然，第一过孔9并不限于上述露出漏极 6的过孔，其也可以是显示区内的其它过孔，例如，第一过孔也可以是露出薄膜晶体管的源极的过孔，本公开不构成对第一过孔的限制。
在本实施方式中，第二过孔10可以实现外围电路的公共焊盘7与其他元件的电连接的过孔，其可位于非显示区内并贯穿钝化层8，并可进一步贯穿栅极绝缘层3，以露出上述公共焊盘7。当然，第二过孔10并不限于上述露出公共焊盘7的过孔，其也可以是非显示区内的其它过孔，本公开不构成对第二过孔的特殊限制。
在本实施方式中，上述第一导电层图形的形成可参考上述阵列基板的制造方法的实施例第一导电层图形可包括上述第一导电膜110在显示区和非显示区被保留的部分。
在本实施方式中，上述第二导电图形的形成可参考上述阵列基板的制造方法的实施例，第二导电层图形可以是第二导电膜130在非显示区被保留的部分，且该第二导电层图形可覆盖第二过孔10，也就是说，第二导电层图形13和第一导电层层图形11可以在非显示区域互相重合。第一导电层层图形11和第二导电层图形13可采用相同的透明导电材质形成，例如氧化铟锡等。若第一导电层图形11和第二导电层图形13材质相同，则它们图形可为一体式结构。图形图形
在本实施方式中，反射金属层图形可覆盖上述第一导电层图形，并可与第一导电图形重合且均可导电，使得反射金属层图形和第一导电层图形可作为像素电极，同时，反射金属层图形还可对光线进行反射，从而为阵列基板的成像提供光源。
本公开的又一实施例还提供一种显示装置，该显示装置可以包括上述任一实施例所述的阵列基板。
对于本公开示例性实施例提供的阵列基板及显示装置，可采用上述实施例所述的阵列基板的制造方法来制造阵列基板，通过第一导电膜图形对第一过孔9进行保护，防止在形成反射金属层图形时对第一过孔9露出的金属的刻蚀；同时，利用第二导电层图形对第二过孔10处的电连接进行巩固和加强，弥补在形成反射金属层图形时可能发生的对第二过孔10露出的金属及第二过孔10的爬坡处的刻蚀。由此，可避免或降低因形成反射金属层图形而造成第一过孔9和第二过孔10处的接触不良，有利于提高良品率。
本领域技术人员在考虑说明书及实践这里公开的实施例后，将容 易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本发明的真正范围和精神由所附的权利要求指出。

Claims (17)

  1. 一种阵列基板的制造方法，包括：
    形成薄膜晶体管和外围电路；
    形成至少覆盖所述薄膜晶体管以及所述外围电路的钝化层；
    形成贯穿所述钝化层且暴露出部分所述薄膜晶体管的漏极的第一过孔，以及贯穿所述钝化层且暴露出部分所述外围电路的第二过孔；
    在所述钝化层上形成第一导电层图形，所述第一导电层图形覆盖所述第一过孔和第二过孔；
    在所述第一导电层图形上形成反射金属层的图形和第二导电层图形，所述第二导电层覆盖所述第二过孔。
  2. 根据权利要求1所述的阵列基板的制造方法，其中形成第一导电层图形、所述第二导电层图形和所述反射金属层的图形包括：
    在所述钝化层上形成第一导电膜；
    在所述第一导电膜上形成反射金属膜；
    对所述反射金属膜进行构图工艺，形成反射金属层图形；
    形成至少覆盖所述反射金属层图形和所述第一导电膜的第二导电膜；
    对所述第一导电膜和所述第二导电膜进行构图工艺，以保留被所述反射金属层图形覆盖的所述第一导电膜的部分，以及覆盖所述第二过孔的所述第一导电膜的部分和所述第二导电膜的部分。
  3. 根据权利要求2所述的阵列基板的制造方法，其中对所述第一导电膜和所述第二导电膜进行构图工艺包括：
    对所述第二导电膜进行构图工艺，去除未覆盖所述第二过孔的所述第二导电膜的部分；
    对所述第一导电膜进行构图工艺，去除未被所述反射金属层图形覆盖且未覆盖所述第二过孔的所述第一导电膜的部分。
  4. 根据权利要求1～3任一项所述的阵列基板的制造方法，其中所述第一导电层图形包括第一导电子图形和第二导电子图形，第一导电子图形经由所述第一过孔与所述薄膜晶体管的漏极连接，所述第二导电子图形经由所述第二过孔与所述外围电路的公共焊盘连接。
  5. 根据权利要求1～3任一项所述的阵列基板的制造方法，其中所 述第一导电层图形和所述第二导电层图形的材质相同。
  6. 根据权利要求5所述的阵列基板的制造方法，其中所述第一导电层图形和所述第二导电层图形均包括透明导电材料。
  7. 根据权利要求4所述的阵列基板的制造方法，其中，所述反射金属层图形和第一导电子图形彼此重叠并覆盖所述第一过孔。
  8. 根据权利要求4所述的阵列基板的制造方法，其中所述第二导电子图形和所述第二导电层图形彼此重叠并覆盖所述第二过孔。
  9. 根据权利要求1-3中任一项所述的阵列基板的制造方法，其中所述反射金属层构成阵列基板的像素电极的一部分。
  10. 一种阵列基板，包括：
    衬底基板；
    薄膜晶体管，设于所述衬底基板上；
    外围电路，设于所述衬底基板上；
    钝化层，至少覆盖所述薄膜晶体管和所述外围电路；
    第一过孔，贯穿所述钝化层并暴露出部分所述薄膜晶体管的漏极；
    第二过孔，贯穿所述钝化层并暴露出部分所述外围电路；
    第一导电层图形，设于所述钝化层上并覆盖所述第一过孔和所述第二过孔；
    第二导电层图形，设于所述钝化层上并覆盖所述第二过孔；
    反射金属层图形，设置于所述第一导电层图形上并覆盖所述第一过孔。
  11. 根据权利要求10所述的阵列基板，其中，所述第一导电图形和所述第二导电图形的材质相同。
  12. 根据权利要求11所述的阵列基板，其中所述第一导电图形和所述第二导电图形均包括透明导电材料。
  13. 根据权利要求10-12任一项所述的阵列基板，其中所述第一导电图形包括第一子导电图形和第二子导电图形，第一子导电图形经由所述第一过孔与所述薄膜晶体管的漏极连接，所述第二子导电图形经由所述第二过孔与所述外围电路的公共焊盘连接。
  14. 根据权利要求13所述的阵列基板，其中，所述反射金属层图形和第一导电子图形彼此重叠并覆盖所述第一过孔。
  15. 根据权利要求13所述的阵列基板，其中所述第二导电子图形 和所述第二导电层图形彼此重叠并覆盖所述第二过孔。
  16. 根据权利要求10-12中任一项所述的阵列基板，其中所述反射金属层构成阵列基板的像素电极的一部分。
  17. 一种显示装置，包括权利要求10-16任一项所述的阵列基板。
PCT/CN2017/116074 2017-05-12 2017-12-14 显示装置、阵列基板及其制造方法 WO2018205604A1 (zh)

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CN108538859A (zh) * 2018-04-24 2018-09-14 深圳市华星光电技术有限公司 阵列基板的制作方法
CN110459505B (zh) 2018-05-07 2022-01-11 京东方科技集团股份有限公司 过孔连接结构及阵列基板的制造方法、阵列基板
CN111554696B (zh) * 2020-05-13 2024-03-29 京东方科技集团股份有限公司 全反射型显示基板及其制作方法、全发射型显示装置
CN112103299B (zh) 2020-09-04 2022-05-03 Tcl华星光电技术有限公司 显示面板的制备方法及显示面板
CN112255849A (zh) 2020-11-10 2021-01-22 合肥京东方光电科技有限公司 显示基板、电子装置
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