WO2016123935A1 - 一种掩膜板及阵列基板的制造方法 - Google Patents

一种掩膜板及阵列基板的制造方法 Download PDF

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Publication number
WO2016123935A1
WO2016123935A1 PCT/CN2015/085322 CN2015085322W WO2016123935A1 WO 2016123935 A1 WO2016123935 A1 WO 2016123935A1 CN 2015085322 W CN2015085322 W CN 2015085322W WO 2016123935 A1 WO2016123935 A1 WO 2016123935A1
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Prior art keywords
region
array substrate
mask
opening
substrate
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PCT/CN2015/085322
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English (en)
French (fr)
Inventor
杨怀伟
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Priority to US14/905,706 priority Critical patent/US9905593B2/en
Publication of WO2016123935A1 publication Critical patent/WO2016123935A1/zh

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/26—Phase shift masks [PSM]; PSM blanks; Preparation thereof
    • G03F1/32—Attenuating PSM [att-PSM], e.g. halftone PSM or PSM having semi-transparent phase shift portion; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/22—Masks or mask blanks for imaging by radiation of 100nm or shorter wavelength, e.g. X-ray masks, extreme ultraviolet [EUV] masks; Preparation thereof
    • G03F1/24—Reflection masks; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2045—Exposure; Apparatus therefor using originals with apertures, e.g. stencil exposure masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a mask and a method of fabricating an array substrate.
  • the gate In the TFT (English: Thin Film Transistor; Chinese: Thin Film Transistor) liquid crystal panel, in order to reduce the frame width of the liquid crystal panel, the gate is usually passed through the GOA (Gate On Array; Chinese: Array substrate row driving) technology.
  • the driving circuit is integrated on the array substrate of the liquid crystal panel to replace the external driving chip, thereby realizing the display function of the liquid crystal panel.
  • the array substrate generally includes a GOA region and a display region.
  • the gate line is connected to the source/drain metal layer by forming a via hole penetrating through the GI (Gate Insulator; Chinese: gate insulating) layer; In the region, it is also necessary to connect the drain of the TFT to the pixel electrode by forming a via.
  • GI Gate Insulator; Chinese: gate insulating
  • a GI mask and a VIA (Chinese: via) mask are used to form via holes in the GOA region and the display region, respectively.
  • VIA Choinese: via
  • embodiments of the present disclosure provide a method for manufacturing a mask and an array substrate.
  • the technical solution is as follows:
  • a mask comprising: a first region corresponding to an array substrate row driving circuit GOA region and a second region corresponding to the array substrate display region;
  • the first region has at least one first opening, and the at least one first opening is used to form a GI via of a gate insulating layer in the array substrate row driving circuit GOA region, and the GI via is used for the GI via Exposing the grid lines;
  • the second region has at least one second opening, the at least one second opening is a halftone mask opening, and the at least one second opening is for forming a VIA via in the array substrate display region, the VIA Vias are used to expose the pattern of the source and drain metal layers.
  • a method of fabricating an array substrate using the above-described mask, the method comprising:
  • a GI via hole of at least one gate insulating layer in the array substrate row driving circuit GOA region by a patterning process, wherein the at least one GI via hole is used to penetrate the gate insulating layer a layer to expose the gate line;
  • the at least one VIA via hole is used to penetrate the protective layer to expose the surface
  • the pattern of the source and drain metal layers is described.
  • the mask panel includes at least one first opening and at least one second opening through which a GI via can be formed in the array substrate row driving circuit GOA region, and the second opening can be in the array
  • the substrate display area forms a VIA via, that is, the first opening forming the GOA area GI via and the second opening forming the display area VIA via are formed on the same mask, and the two vias are the same
  • the formation of the mask reduces the manufacturing cost of the product.
  • FIG. 1 is a schematic structural view of a mask plate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural view of another mask provided by an embodiment of the present disclosure.
  • FIG. 3 is a flow chart of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • FIG. 4 is a flow chart of another method for fabricating an array substrate according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a substrate formed with a gate line pattern according to an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of a substrate formed with a gate insulating layer according to an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of a substrate formed with a GOA region GI via hole according to an embodiment of the present disclosure
  • FIG. 8 is a schematic structural diagram of a substrate formed with a data line pattern according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural view of a substrate formed with a protective layer according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a substrate in which a via layer is formed in a protective layer of a GOA region according to an embodiment of the present disclosure
  • FIG. 11 is a schematic structural diagram of a substrate in which an ITO pattern is formed at a via of a protective layer of a GOA region according to an embodiment of the present disclosure.
  • 51 transparent substrate
  • 52 pattern of gate lines
  • 53 gate insulating layer
  • 54 GI via
  • 55 pattern of source and drain metal layers
  • 56 protective layer
  • 57 via
  • 58 pattern of transparent electrodes.
  • the embodiment of the present disclosure provides a mask.
  • the mask includes: a first region 1 corresponding to the GOA region of the array substrate and a second region 2 corresponding to the display region of the array substrate.
  • the first region 1 has at least one first opening 11 for forming a gate insulating layer GI via hole in the array substrate GOA region, the GI via hole for exposing the gate line; the second region 2 having at least A second opening 21, the at least one second opening 21 is a halftone mask opening, and the at least one second opening is for forming a VIA via in the display area of the array substrate.
  • the mask panel includes at least one first opening and at least one second opening through which a GI via can be formed in the array substrate GOA region, and the second opening can be displayed on the array substrate
  • the region forms a VIA via, that is, the first opening that forms the GI via of the GOA region and the second opening that forms the via of the display region VIA are formed on the same mask, and the two vias use the same mask
  • the formation of the plate reduces the manufacturing cost of the product.
  • the halftone mask opening refers to an opening that is not completely transparent.
  • a filter structure can be implemented by adding a filter structure in the completely transparent opening as needed.
  • a halftone mask specifically, at least one second opening 21 is provided as a halftone mask opening, and when the GI via of the GOA region is formed through the mask, the gate of the display region in the array substrate is not gated
  • the insulation layer has an effect.
  • the display area of the array substrate is an effective display area in the array substrate, that is, a light-transmitting area in the array substrate.
  • the mask further includes: a third region 3 corresponding to an array substrate IC Pad (English: Integrated Circuit Pad; Chinese: Integrated Circuit Interface) region.
  • IC Pad English: Integrated Circuit Pad
  • Chinese Integrated Circuit Interface
  • the third region 3 has at least one third opening 31, the at least one third opening 31 is a halftone mask opening, and the at least one third opening 31 is for forming a VIA via in the IC pad area of the array substrate.
  • the VIA via of the IC Pad region can also be formed.
  • the GI via of the GOA region is used to expose the gate line, and the gate line of the GOA region is connected to the source/drain metal layer, and the VIA via of the display region is used to expose the pattern of the source/drain metal layer, and the TFT of the display region
  • the drain is connected to the pixel electrode, IC Pad
  • the VIA via of the region is also used to expose the pattern of the source/drain metal layer, and therefore, the third opening of the VIA via for forming the IC Pad region is set to a halftone mask for the same reason as the via of the display region VIA.
  • the film is opened, and the third opening for forming the via of the IC Pad region VIA is also formed on the same mask, further reducing the manufacturing cost of the product.
  • the mask further includes: a fourth region 4 corresponding to the signal line region of the array substrate.
  • the fourth region 4 has at least one fourth opening 41 for forming a GI via of the array substrate signal line region.
  • the GI via of the GOA region, the VIA via of the display region, and the VIA via of the IC Pad region can be formed, but also the GI via of the signal line region can be formed.
  • the GI via of the signal line region is used to expose the gate line. Therefore, the fourth opening for forming the signal line region GI via is also formed on the same mask, further reducing the manufacturing cost of the product.
  • At least one first opening on the mask board can not only form a GI via hole of the GOA area of the array substrate, but also can form other via holes of the GOA area, which is not specifically limited in the embodiment of the present disclosure.
  • at least one second opening on the mask can form not only a VIA via of the array substrate display region but also other vias of the display region;
  • at least one third opening on the mask can be formed not only The VIA via hole of the IC Pad region of the array substrate can also form other via holes of the IC Pad region;
  • at least one fourth opening on the mask plate can not only form the GI via hole of the signal line region of the array substrate, but also Other vias forming the signal line region are also not specifically limited in the embodiment of the present disclosure.
  • the embodiment of the present disclosure provides a method for fabricating an array substrate, which uses the mask of the above embodiment. Referring to FIG. 3, the method includes:
  • Step 301 forming a pattern of gate lines on the transparent substrate.
  • Step 302 Form a gate insulating layer on the substrate on which the gate line pattern is formed.
  • Step 303 forming at least one gate insulating layer GI via hole in the GOA region of the array substrate by a patterning process on the surface of the gate insulating layer by using a mask plate of the above embodiment, the at least one GI via hole being used for penetrating the gate insulating layer The gate line is exposed.
  • Step 304 sequentially forming a pattern of an active layer and a source/drain metal layer on a surface of the substrate on which at least one GI via is formed.
  • the pattern of the gate line and the source/drain metal layer is directly connected to at least one GI via location. .
  • the present disclosure also forms a data line for connecting the source, and thus, a pattern of the source/drain metal layer is formed, in other words, a pattern of the source/drain metal layer including the data line is formed.
  • Step 305 forming a protective layer on the substrate on which the pattern of the active layer and the source/drain metal layer is formed.
  • Step 306 forming at least one VIA via hole in the display area of the array substrate by using a masking process on the surface of the protective layer, the at least one VIA via hole for penetrating the protective layer to expose the pattern of the source/drain metal layer .
  • At least one GI via of the GOA region is formed on the gate insulating layer by a first patterning process to penetrate the gate insulating layer of the GOA region, and the gate line at the at least one GI via is exposed And directly forming a pattern of the gate line and the source/drain metal layer by forming a pattern of the active layer and the source/drain metal layer on the gate line at the at least one GI via of the GOA region.
  • two patterning processes are formed to form at least one GI via of the GOA region and at least one VIA via of the display region, respectively, which reduces the manufacturing cost of the product.
  • the embodiment of the present disclosure provides a method for fabricating an array substrate, which uses the mask of the above embodiment. Referring to FIG. 4, the method includes:
  • Step 401 Form a pattern of gate lines on the transparent substrate.
  • a gate metal layer is formed on the transparent substrate, and a pattern of the gate lines is formed on the gate metal layer by a patterning process.
  • the gate metal layer is used to form a pattern of gate lines, and when the gate metal layer is formed on the transparent substrate, it may be formed by deposition, coating or sputtering.
  • the embodiments of the present disclosure do not specifically limit this.
  • the process of forming the gate line pattern by the patterning process may be: coating a photoresist on the surface of the gate metal layer, using a mask for forming a gate line pattern, and coating The substrate of the photoresist is exposed, the exposed substrate is developed using a developing solution, and a pattern corresponding to the mask for forming the gate line pattern is formed on the photoresist-coated substrate, and then The developed substrate is etched using an etching solution, and finally the photoresist is stripped to form a pattern of gate lines.
  • a method for forming a gate line pattern on a transparent substrate may refer to a method for forming a gate line pattern on a transparent substrate in the prior art, which is not described in detail in the embodiments of the present disclosure.
  • Step 402 Form a gate insulating layer on the substrate on which the gate line pattern is formed.
  • the gate insulating layer serves to protect the gate line pattern formed on the transparent substrate, and may be formed by deposition, coating, or sputtering when the gate insulating layer is formed on the substrate on which the gate line pattern is formed.
  • the embodiments of the present disclosure are also not specifically limited.
  • a substrate structure for forming a gate line pattern on a transparent substrate may be as shown in FIG. 5.
  • 51 is for indicating a transparent substrate
  • 52 is for indicating a pattern of gate lines
  • a gate line is formed as shown in FIG. 5.
  • a gate insulating layer 53 is formed on the patterned substrate as shown in FIG.
  • Step 403 forming at least one GI via hole in the GOA region of the array substrate by using a mask plate of the above embodiment on the surface of the gate insulating layer, the at least one GI via hole is used to penetrate the gate insulating layer to expose the gate. line.
  • a photoresist is coated on the surface of the gate insulating layer; the photoresist coated substrate is exposed by using the mask of the above embodiment; and the exposed substrate is developed and etched to form an array substrate. At least one GI via in the GOA region.
  • development can be performed by the developer, and when the substrate after development is etched, etching can be performed by the etching solution.
  • the mask is used When the plate is exposed to the photoresist-coated substrate, the photoresist corresponding to the at least one first opening may be completely photosensitive, and the photoresist corresponding to the at least one second opening is only partially illuminated in the thickness direction.
  • the exposed substrate is developed by using a developing solution, at least one photoresist corresponding to the first opening may be completely dissolved in the developing solution, and the photosensitive portion in the photoresist corresponding to the at least one second opening is dissolved in the developing solution.
  • the unsensitized portion is also located on the substrate, and in general, the thickness of the photosensitive portion is small, and the thickness of the unsensed portion is large. Therefore, when the substrate after development is subsequently etched, it is not at least on the substrate. An influence occurs at a corresponding position of a second opening, ensuring that at least one GI via of the GOA area and at least one VIA via of the display area can adopt the mask Board.
  • the mask since the mask includes not only at least one first opening for forming a GOA region GI via, but also at least one for forming a signal line region GI via The four openings, therefore, on the gate insulating layer, using the mask of the above embodiment, at least one GI via hole of the array substrate signal line region is formed when at least one GI via hole is formed in the array substrate GOA region by a patterning process.
  • a process of forming at least one GI via hole in the GOA region of the array substrate by a patterning process by using a masking process includes: using the same mask plate on the surface of the gate insulating layer, through a patterning process At least one GI via located in the GOA region of the array substrate and at least one GI via located in the signal line region of the array substrate are respectively formed. At least one GI via of the signal line region is formed while forming at least one GI via of the GOA region, which shortens the manufacturing cycle of the array substrate and further reduces the manufacturing cost of the array substrate.
  • the process of forming at least one GI via of the signal line region of the array substrate is the same as the process of forming at least one GI via of the GOA region, and details are not described herein.
  • At least one GI via 54 is formed in the GOA region of the array substrate by a patterning process using a mask, as shown in FIG.
  • Step 404 sequentially forming a pattern of an active layer and a source/drain metal layer on a surface of the substrate on which at least one GI via is formed.
  • a pattern of the gate line and the source/drain metal layer is directly connected at at least one GI via position. .
  • the active layer is further included in the display region of the array substrate, the active layer is located above the gate insulating layer and under the source/drain metal layer, and therefore, an active layer needs to be formed on the surface of the substrate on which at least one GI via is formed. Moreover, since the active layer is not included in the GOA region of the array substrate, when the active layer is formed on the surface of the substrate on which at least one GI via is formed, the active layer may not be formed at at least one GI via, and for the GOA region The formed active layer can be peeled off.
  • a source/drain metal layer is formed on the surface of the substrate on which the active layer is formed, and a pattern of the source/drain metal layer is formed on the source/drain metal layer by a patterning process.
  • the pattern of the gate line and the source/drain metal layer is directly connected at at least one GI via location to avoid connection failure, thereby improving the connection stability of the gate line and the source/drain metal layer.
  • the patterning process for forming the source/drain metal layer pattern on the source/drain metal layer is similar to the patterning process for forming the gate line pattern on the gate metal layer in the above step 401, which is not described in detail in the embodiment of the present disclosure.
  • a method for forming a source/drain metal layer pattern on a substrate on which an active drain metal layer is formed may refer to a method for forming a source/drain metal layer pattern on a substrate on which an active drain metal layer is formed in the prior art.
  • the embodiments of the present disclosure are also not described herein again.
  • the pattern of the source/drain metal layer includes a data line and a source and a drain of the TFT.
  • the position of at least one GI via 54 in FIG. 8 is directly connected to the pattern of the source/drain metal layer.
  • Step 405 forming a protective layer on the substrate on which the pattern of the active layer and the source/drain metal layer is formed.
  • the protective layer is used to protect the source/drain metal layer pattern formed on the substrate, and may be formed by deposition, coating, or sputtering when the protective layer is formed on the substrate on which the active drain metal layer pattern is formed.
  • the embodiments of the present disclosure are also not specifically limited.
  • a protective layer 56 is formed on the substrate on which the active drain metal layer pattern 55 is formed as shown in FIG.
  • Step 406 forming at least one VIA via hole in the display area of the array substrate by using a masking process on the surface of the protective layer, the at least one VIA via hole for penetrating the protective layer to expose the pattern of the source/drain metal layer .
  • a photoresist is coated on the surface of the protective layer; the photoresist coated substrate is exposed by using the mask of the above embodiment; and the exposed substrate is developed, ashed, and etched to form At least one VIA via of the array substrate display area.
  • development can be performed by the developer, and when the substrate after development is etched, etching can be performed by the etching solution.
  • the mask is used a photoresist for exposing a photoresist-coated substrate, wherein at least one photoresist corresponding to the first opening is completely sensitized, and at least one photoresist corresponding to the second opening is only partially in a thickness direction Photosensitive, therefore, when the exposed substrate is developed using a developing solution, at least one photoresist corresponding to the first opening may be completely dissolved in the developing solution, and the photosensitive portion of the photoresist corresponding to the at least one second opening It will dissolve in the developer, and the unexposed portion will also be on the substrate. Therefore, the unsensitized portion of the photoresist corresponding to the at least one second opening can be removed by the ashing process. Thereafter, the substrate is etched by an etching process to form at least one VIA via of the array substrate display region.
  • the at least one second opening is a halftone mask opening. Therefore, after the development, the ashing process is added, and the photoresist corresponding to the at least one second opening can be effectively removed, thereby ensuring at least one VIA via hole forming the display region.
  • the exposed substrate is developed by using a developing solution
  • at least one photoresist corresponding to the first opening is completely dissolved in the developing solution, and therefore, at least one corresponding position of the first opening is etched when the substrate is etched by an etching process
  • the protective layer is also inscribed, so on the surface of the protective layer,
  • the mask plate forms a via hole in a region where the corresponding gate line of the protective layer is directly connected to the pattern of the source/drain metal layer when the at least one VIA via hole is formed in the display region of the array substrate by a patterning process.
  • a pattern of transparent electrodes is formed on the pattern of the source/drain metal layer at the via hole of the region where the protective layer corresponding to the gate line and the source/drain metal layer are directly connected.
  • the source/drain metal layer is used for signal output of the GOA region, after the transparent electrode pattern is formed on the pattern of the source/drain metal layer at the via, the signal of the source/drain metal layer pattern can be tested by the pattern of the transparent electrode. To ensure that the signal output of the GOA area is normal.
  • the transparent electrode may be an ITO (Indium Tin Oxide; Chinese: Indium Tin Oxide) electrode, and of course, other electrodes may be used. .
  • ITO Indium Tin Oxide
  • Chinese Indium Tin Oxide
  • a via hole 57 is formed at a region where the protective layer 56 is directly connected to the pattern of the gate line and the source/drain metal layer.
  • a pattern 58 of transparent electrodes is formed on the source/drain metal layer pattern at the via 57 as shown in FIG.
  • the mask since the mask includes not only at least one second opening for forming the via of the display area VIA, but also at least one third opening for forming the via of the IC Pad region VIA, therefore, the protection At least one VIA via hole of the IC pad region of the array substrate is formed on the layer by using the mask to form at least one VIA via in the display region of the array substrate by a patterning process.
  • the mask is used to form at least one VIA via in the display region of the array substrate by a patterning process, including: using the same mask on the surface of the protective layer, through a patterning process Forming at least one VIA via located in the display area of the array substrate and at least one VIA via located in the IC Pad area of the array substrate integrated circuit interface, respectively.
  • At least one VIA via of the IC Pad region is formed while forming at least one VIA via of the display region, which shortens the manufacturing cycle of the array substrate and further reduces the manufacturing cost of the array substrate.
  • At least one GI via of the GOA region is formed on the gate insulating layer by a first patterning process to penetrate the gate insulating layer of the GOA region, and the gate line at the at least one GI via is exposed And directly forming a pattern of the gate line and the source/drain metal layer by forming a pattern of the active layer and the source/drain metal layer on the gate line at the at least one GI via of the GOA region.
  • two patterning processes are formed to form at least one GI via of the GOA region and at least one VIA via of the display region, respectively, which reduces the manufacturing cost of the product.

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Abstract

一种掩膜板包括：对应阵列基板行驱动电路GOA区域的第一区域（1）和对应阵列基板显示区域的第二区域（2）；第一区域（1）具有至少一个第一开口（11），至少一个第一开口（11）用于在阵列基板行驱动电路GOA区域形成栅绝缘层（53）的GI过孔（54），GI过孔（54）用于暴露出栅线的图案（52）；第二区域（2）具有至少一个第二开口（21），至少一个第二开口（21）为半色调掩膜开口，至少一个第二开口（21）用于在阵列基板显示区域形成VIA过孔，VIA过孔用于暴露出源漏金属层的图案（55）。

Description

一种掩膜板及阵列基板的制造方法
相关申请的交叉引用
本申请主张在2015年2月6日在中国提交的中国专利申请号No.201510064583.9的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，特别涉及一种掩膜板及阵列基板的制造方法。
背景技术
在TFT(英文：Thin Film Transistor；中文：薄膜晶体管)液晶面板中，为了减小液晶面板的边框宽度，通常是通过GOA(英文：Gate On Array；中文：阵列基板行驱动)技术，将栅极驱动电路集成在液晶面板的阵列基板上，来代替外接的驱动芯片，从而实现液晶面板的显示功能。而阵列基板一般包括GOA区域和显示区域，在GOA区域中，需要通过形成贯穿GI(英文：Gate Insulator；中文：栅绝缘)层的过孔，将栅线与源漏金属层进行连接；在显示区域中，同样需要通过形成过孔将TFT的漏极与像素电极进行连接。
现有技术通常是制作两块掩膜板，即，采用GI掩膜板和VIA(中文：过孔)掩膜板分别形成位于GOA区域和显示区域的过孔。但是，制作两块掩膜板会增加产品的制造成本。
发明内容
为了解决现有技术的问题，本公开实施例提供了一种掩膜板及阵列基板的制造方法。所述技术方案如下：
一方面，提供了一种掩膜板，所述掩膜板包括：对应阵列基板行驱动电路GOA区域的第一区域和对应阵列基板显示区域的第二区域；
所述第一区域具有至少一个第一开口，所述至少一个第一开口用于在所述阵列基板行驱动电路GOA区域形成栅绝缘层的GI过孔，所述GI过孔用 于暴露出栅线；
所述第二区域具有至少一个第二开口，所述至少一个第二开口为半色调掩膜开口，所述至少一个第二开口用于在所述阵列基板显示区域形成VIA过孔，所述VIA过孔用于暴露出源漏金属层的图案。
另一方面，提供了一种阵列基板的制造方法，采用上述的掩膜板，所述方法包括：
在透明基板上形成栅线的图案；
在形成有栅线图案的基板上形成栅绝缘层；
在所述栅绝缘层的表面，采用掩膜板，通过构图工艺在阵列基板行驱动电路GOA区域形成至少一个栅绝缘层的GI过孔，所述至少一个GI过孔用于贯穿所述栅绝缘层以暴露出所述栅线；
在形成有至少一个GI过孔的基板表面依次形成有源层和源漏金属层的图案，在所述阵列基板行驱动电路GOA区域，所述栅线与所述源漏金属层的图案在所述至少一个GI过孔位置处直接相连；
在形成有有源层和源漏金属层的图案的基板上形成保护层；
在所述保护层的表面，采用所述掩膜板，通过构图工艺在所述阵列基板显示区域形成至少一个VIA过孔，所述至少一个VIA过孔用于贯穿所述保护层以暴露出所述源漏金属层的图案。
在本公开实施例中，该掩膜板上包括至少一个第一开口和至少一个第二开口，通过第一开口可以在阵列基板行驱动电路GOA区域形成GI过孔，通过第二开口可以在阵列基板显示区域形成VIA过孔，也即是，将形成GOA区域GI过孔的第一开口和形成显示区域VIA过孔的第二开口制作在同一个掩膜板上，两种过孔采用同一块掩膜板形成，降低了产品的制造成本。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中 所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种掩膜板结构示意图；
图2是本公开实施例提供的另一种掩膜板结构示意图；
图3是本公开实施例提供的一种阵列基板制造方法的流程图；
图4是本公开实施例提供的另一种阵列基板制造方法的流程图；
图5是本公开实施例提供的一种形成有栅线图案的基板结构示意图；
图6是本公开实施例提供的一种形成有栅极绝缘层的基板结构示意图；
图7是本公开实施例提供的一种形成有GOA区域GI过孔的基板结构示意图；
图8是本公开实施例提供的一种形成有数据线图案的基板结构示意图；
图9是本公开实施例提供的一种形成有保护层的基板结构示意图；
图10是本公开实施例提供的一种在GOA区域的保护层形成过孔的基板结构示意图；
图11是本公开实施例提供的一种在GOA区域保护层的过孔处形成ITO图案的基板结构示意图。
附图标记：
1：第一区域；2：第二区域；3：第三区域；4：第四区域；
11：第一开口；21：第二开口；31：第三开口；41：第四开口；
51：透明基板；52：栅线的图案；53：栅绝缘层；54：GI过孔；55：源漏金属层的图案；56：保护层；57：过孔；58：透明电极的图案。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
本公开实施例提供了一种掩膜板，参见图1，该掩膜板包括：对应阵列基板GOA区域的第一区域1和对应阵列基板显示区域的第二区域2。
第一区域1具有至少一个第一开口11，至少一个第一开口11用于在阵列基板GOA区域形成栅绝缘层GI过孔，该GI过孔用于暴露出栅线；第二区域2具有至少一个第二开口21，至少一个第二开口21为半色调掩膜开口，至少一个第二开口用于在阵列基板显示区域形成VIA过孔。
在本公开的实施例中，该掩膜板上包括至少一个第一开口和至少一个第二开口，通过第一开口可以在阵列基板GOA区域形成GI过孔，通过第二开口可以在阵列基板显示区域形成VIA过孔，也即是，将形成GOA区域GI过孔的第一开口和形成显示区域VIA过孔的第二开口制作在同一个掩膜板上，两种过孔采用同一块掩膜板形成，降低了产品的制造成本。
需要说明的是，在本公开实施例中，半色调掩模开口是指不完全透光的开口，在实际应用的过程中，可以根据需要通过在完全透光的开口中加装滤光结构实现半色调的掩模，具体地说，将至少一个第二开口21设置为半色调掩膜开口，当通过该掩膜板形成GOA区域的GI过孔时，不会对阵列基板中显示区域的栅绝缘层产生影响。另外，在本公开的实施例中，阵列基板的显示区域为该阵列基板中的有效显示区域，也即是该阵列基板中的透光区域。
在一些实施方式中，参见图2，该掩膜板还包括：对应阵列基板IC Pad(英文：Integrated Circuit Pad；中文：集成电路接口)区域的第三区域3。
第三区域3具有至少一个第三开口31，至少一个第三开口31为半色调掩膜开口，且至少一个第三开口31用于在阵列基板IC Pad区域形成VIA过孔。
在阵列基板中不仅可以形成GOA区域的GI过孔和显示区域的VIA过孔，还可以形成IC Pad区域的VIA过孔。GOA区域的GI过孔用于暴露出栅线，并将GOA区域的栅线与源漏金属层连接，显示区域的VIA过孔用于暴露出源漏金属层的图案，并将显示区域的TFT的漏极与像素电极连接，IC Pad 区域的VIA过孔也用于暴露出源漏金属层的图案，因此，基于与显示区域VIA过孔同样的理由，将用于形成IC Pad区域的VIA过孔的第三开口设置为半色调掩膜开口，并且将用于形成IC Pad区域VIA过孔的第三开口也制作在同一掩膜板上，进一步降低了产品的制造成本。
在一些实施方式中，该掩膜板还包括：对应阵列基板信号线区域的第四区域4。
第四区域4具有至少一个第四开口41，至少一个第四开口41用于形成阵列基板信号线区域的GI过孔。
在阵列基板中不仅可以形成GOA区域的GI过孔、显示区域的VIA过孔和IC Pad区域的VIA过孔，还可以形成信号线区域的GI过孔。而信号线区域的GI过孔用于暴露出栅线，因此，将用于形成信号线区域GI过孔的第四开口也制作在同一掩膜板上，进一步降低了产品的制造成本。
需要说明的是，该掩膜板上的至少一个第一开口不仅可以形成阵列基板GOA区域的GI过孔，还可以形成GOA区域的其他过孔，本公开实施例对此不做具体限定。同理，该掩膜板上的至少一个第二开口不仅可以形成阵列基板显示区域的VIA过孔，还可以形成显示区域的其他过孔；该掩膜板上的至少一个第三开口不仅可以形成阵列基板的IC Pad区域的VIA过孔，还可以形成IC Pad区域的其他过孔；该掩膜板上的至少一个第四开口也不仅可以形成阵列基板的信号线区域的GI过孔，还可以形成信号线区域的其他过孔，本公开实施例同样对此不做具体限定。
上述所有可选技术方案，均可按照任意结合形成本公开的可选实施例，本公开实施例对此不再一一赘述。
本公开实施例提供了一种阵列基板的制造方法，采用上述实施例的掩膜板，参见图3，该方法包括：
步骤301：在透明基板上形成栅线的图案。
步骤302：在形成有栅线图案的基板上形成栅绝缘层。
步骤303：在栅绝缘层的表面，采用上述实施例的掩膜板，通过构图工艺在阵列基板GOA区域形成至少一个栅绝缘层GI过孔，该至少一个GI过孔用于贯穿栅绝缘层以暴露出栅线。
步骤304：在形成有至少一个GI过孔的基板表面依次形成有源层和源漏金属层的图案，在GOA区域，栅线与源漏金属层的图案在至少一个GI过孔位置处直接相连。
本公开在形成源漏金属层的图案时，同时也形成用于连接源极的数据线，因此，形成源漏金属层的图案，换句话说，形成包括数据线的源漏金属层的图案。
步骤305：在形成有有源层和源漏金属层的图案的基板上形成保护层。
步骤306：在保护层的表面，采用同一掩膜板，通过构图工艺在阵列基板显示区域形成至少一个VIA过孔，该至少一个VIA过孔用于贯穿保护层以暴露出源漏金属层的图案。
在本公开实施例中，在栅绝缘层上通过第一次构图工艺形成GOA区域的至少一个GI过孔，以贯穿GOA区域的栅绝缘层，将该至少一个GI过孔处的栅线暴露在外，并通过在GOA区域的至少一个GI过孔处的栅线上形成有源层和源漏金属层的图案，实现栅线与源漏金属层的图案的直接相连。另外，通过采用同一个掩膜板，分两次构图工艺，分别形成GOA区域的至少一个GI过孔和显示区域的至少一个VIA过孔，降低了产品的制作成本。
本公开实施例提供了一种阵列基板的制造方法，采用上述实施例的掩膜板，参见图4，该方法包括：
步骤401：在透明基板上形成栅线的图案。
具体地，在透明基板上形成栅极金属层，在栅极金属层上，通过构图工艺形成栅线的图案。
其中，栅极金属层用于形成栅线的图案，而在透明基板上形成栅极金属层时，可以通过沉积、涂覆或溅射的方式来形成。当然，实际应用中，还可 以通过其他的方式，本公开实施例对此不做具体限定。
另外，在栅极金属层上，通过构图工艺形成栅线图案的过程可以为：在栅极金属层的表面上涂覆光刻胶，采用用于形成栅线图案的掩膜板，对涂覆光刻胶的基板进行曝光，使用显影液，对曝光后的基板进行显影，进而在涂覆光刻胶的基板上形成与用于形成栅线图案的掩膜板相对应的图形，之后，再使用刻蚀液，对显影后的基板进行刻蚀，最后剥离光刻胶，从而形成栅线的图案。
需要说明的是，本公开实施例中，在透明基板上形成栅线图案的方法可以参考现有技术中在透明基板上形成栅线图案的方法，本公开实施例对此不再赘述。
步骤402：在形成有栅线图案的基板上形成栅绝缘层。
栅绝缘层用于对透明基板上形成的栅线图案进行保护，且在形成有栅线图案的基板上形成栅绝缘层时，也可以通过沉积、涂覆或溅射的方式来形成。当然，实际应用中，还可以通过其他的方式，本公开实施例同样对此不做具体限定。
比如，在透明基板上形成栅线图案的基板结构可以如图5所示，在图5中，51用于指示透明基板，52用于指示栅线的图案，在图5所示形成有栅线图案的基板上形成栅绝缘层53，如图6所示。
步骤403：在栅绝缘层的表面，采用上述实施例的掩膜板，通过构图工艺在阵列基板GOA区域形成至少一个GI过孔，该至少一个GI过孔用于贯穿栅绝缘层以暴露出栅线。
具体地，在栅绝缘层的表面上涂覆光刻胶；采用上述实施例的掩膜板，对涂覆光刻胶的基板进行曝光；对曝光后的基板进行显影和刻蚀，形成阵列基板GOA区域的至少一个GI过孔。其中，对曝光后的基板进行显影时，可以通过显影液进行显影，对显影之后的基板进行刻蚀时，可以通过刻蚀液进行刻蚀。
由于上述实施例中掩膜板的第一区域中具有至少一个第一开口，第二区域中具有至少一个第二开口，且至少一个第二开口是半色调掩膜开口，所以，采用该掩膜板对涂覆光刻胶的基板进行曝光时，至少一个第一开口对应的光刻胶可以完全被感光，而至少一个第二开口对应的光刻胶在厚度方向上只有一部分被感光，因此，使用显影液对曝光后的基板进行显影时，至少一个第一开口对应的光刻胶可以完全溶解在显影液中，而至少一个第二开口对应的光刻胶中的感光部分会溶解在显影液中，未感光部分还位于该基板上，并且一般情况下，感光部分的厚度较小，未感光部分的厚度较大，因此，后续对显影之后的基板进行刻蚀时，不会对基板上至少一个第二开口对应位置处产生影响，确保GOA区域的至少一个GI过孔和显示区域的至少一个VIA过孔均可以采用该掩膜板。
在一些实施方式中，如附图2所示，由于掩膜板上不仅包括用于形成GOA区域GI过孔的至少一个第一开口，还包括用于形成信号线区域GI过孔的至少一个第四开口，因此，在栅绝缘层上，采用上述实施例的掩膜板，通过构图工艺在阵列基板GOA区域形成至少一个GI过孔时，还形成阵列基板信号线区域的至少一个GI过孔。也即是，在栅绝缘层的表面，采用掩膜板，通过构图工艺在阵列基板GOA区域形成至少一个GI过孔的工序包括：在栅绝缘层的表面，采用同一掩膜板，通过构图工艺分别形成位于阵列基板GOA区域的至少一个GI过孔以及位于阵列基板信号线区域的至少一个GI过孔。在形成GOA区域的至少一个GI过孔的同时，还形成信号线区域的至少一个GI过孔，缩短了阵列基板的制造周期，进而也降低了阵列基板的制造成本。
需要说明的是，形成阵列基板信号线区域的至少一个GI过孔的工艺与上述形成GOA区域的至少一个GI过孔的工艺相同，本公开实施例对此不再赘述。
基于上述步骤的例子，在图6所示的栅绝缘层上，采用掩膜板，通过构图工艺在阵列基板GOA区域形成至少一个GI过孔54，如图7所示。
步骤404：在形成有至少一个GI过孔的基板表面依次形成有源层和源漏金属层的图案，在GOA区域，栅线与源漏金属层的图案在至少一个GI过孔位置处直接相连。
由于阵列基板显示区域中还包括有源层，该有源层位于栅绝缘层之上，且位于源漏金属层之下，因此，在形成有至少一个GI过孔的基板表面需要形成有源层。又由于阵列基板GOA区域中不包括有源层，因此，在形成有至少一个GI过孔的基板表面形成有源层时，在至少一个GI过孔处可以不形成有源层，而对于GOA区域形成的有源层，可以进行剥离。之后，在形成有源层的基板表面形成源漏金属层，在源漏金属层上，通过构图工艺，形成源漏金属层的图案。在GOA区域，栅线与源漏金属层的图案在至少一个GI过孔位置处直接相连，避免出现连接不良的现象，从而提高栅线与源漏金属层的连接稳定性。
其中，在源漏金属层上形成源漏金属层图案的构图工艺与上述步骤401中，在栅极金属层上形成栅线图案的构图工艺相似，本公开实施例对此不再赘述。另外，本公开实施例中，在形成有源漏金属层的基板上形成源漏金属层图案的方法可以参考现有技术中在形成有源漏金属层的基板上形成源漏金属层图案的方法，本公开实施例同样对此不再赘述。
其中，源漏金属层的图案包括数据线与TFT的源极以及漏极。
基于上述步骤的例子，如图8所示，在形成有至少一个GI过孔54的基板表面依次形成有源层和源漏金属层的图案55之后，图8中的至少一个GI过孔54位置处的栅线与源漏金属层的图案直接相连。
步骤405：在形成有有源层和源漏金属层的图案的基板上形成保护层。
保护层用于对基板上形成的源漏金属层图案进行保护，且在形成有源漏金属层图案的基板上形成保护层时，也可以通过沉积、涂覆或溅射的方式来形成。当然，实际应用中，还可以通过其他的方式，本公开实施例同样对此不做具体限定。
基于上述步骤的例子，在图8所示形成有源漏金属层图案55的基板上形成保护层56，如图9所示。
步骤406：在保护层的表面，采用同一掩膜板，通过构图工艺在阵列基板显示区域形成至少一个VIA过孔，该至少一个VIA过孔用于贯穿保护层以暴露出源漏金属层的图案。
具体地，在保护层的表面上涂覆光刻胶；采用上述实施例的掩膜板，对涂覆光刻胶的基板进行曝光；对曝光后的基板进行显影、灰化和刻蚀，形成阵列基板显示区域的至少一个VIA过孔。其中，对曝光后的基板进行显影时，可以通过显影液进行显影，对显影之后的基板进行刻蚀时，可以通过刻蚀液进行刻蚀。
由于上述实施例中掩膜板的第一区域中具有至少一个第一开口，第二区域中具有至少一个第二开口，且至少一个第二开口是半色调掩膜开口，所以，采用该掩膜板，对涂覆光刻胶的基板进行曝光时，该基板中，至少一个第一开口对应的光刻胶可以完全被感光，而至少一个第二开口对应的光刻胶在厚度方向上只有一部分被感光，因此，使用显影液对曝光后的基板进行显影时，至少一个第一开口对应的光刻胶可以完全溶解在显影液中，而至少一个第二开口对应的光刻胶中的感光部分会溶解在显影液中，未感光部分还位于该基板上。因此，通过灰化工艺，可以将至少一个第二开口对应的光刻胶中未感光部分去除。之后，再通过刻蚀工艺，对基板进行刻蚀，从而可以形成阵列基板显示区域的至少一个VIA过孔。
至少一个第二开口是半色调掩膜开口，因此，在显影之后，增加灰化工艺，可以有效去除至少一个第二开口对应的光刻胶，进而可以确保形成显示区域的至少一个VIA过孔。
使用显影液对曝光后的基板进行显影时，至少一个第一开口对应的光刻胶完全溶解在显影液中，因此，通过刻蚀工艺，对基板进行刻蚀时，至少一个第一开口对应位置的保护层也会被刻穿，所以，在保护层的表面，采用该 掩膜板，通过构图工艺在阵列基板显示区域形成至少一个VIA过孔时，还在保护层的对应栅线与源漏金属层的图案直接相连的区域形成过孔。之后，再在保护层对应栅线与源漏金属层的图案直接相连区域的过孔处，源漏金属层的图案上形成透明电极的图案。
由于源漏金属层用于GOA区域的信号输出，因此，在该过孔处的源漏金属层的图案上形成透明电极图案之后，可以通过透明电极的图案对源漏金属层图案的信号进行测试，以确保GOA区域的信号输出正常。
需要说明的是，在本公开实施例中，透明电极可以为ITO(英文：Indium Tin Oxide；中文：氧化铟锡)电极，当然，还可以为其他电极，本公开实施例对此不做具体限定。
基于上述步骤的例子，如图10所示，形成有保护层56的基板上，在保护层56对应栅线与源漏金属层的图案直接相连区域处形成过孔57。在该过孔57处的源漏金属层图案上形成透明电极的图案58，如图11所示。
在一些实施方式中，由于掩膜板上不仅包括用于形成显示区域VIA过孔的至少一个第二开口，还包括用于形成IC Pad区域VIA过孔的至少一个第三开口，因此，在保护层上，采用该掩膜板，通过构图工艺在阵列基板显示区域形成至少一个VIA过孔时，还形成阵列基板IC Pad区域的至少一个VIA过孔。也即是，在保护层的表面，采用该掩膜板，通过构图工艺在阵列基板显示区域形成至少一个VIA过孔的工序包括：在保护层的表面，采用该同一掩膜板，通过构图工艺分别形成位于阵列基板显示区域的至少一个VIA过孔以及位于阵列基板集成电路接口IC Pad区域的至少一个VIA过孔。在形成显示区域的至少一个VIA过孔的同时，还形成IC Pad区域的至少一个VIA过孔，缩短了阵列基板的制造周期，进而也降低了阵列基板的制造成本。
需要说明的是，形成阵列基板IC Pad区域的至少一个VIA过孔的工艺与上述形成显示区域的至少一个VIA过孔的工艺相同，本公开实施例对此不再赘述。
在本公开实施例中，在栅绝缘层上通过第一次构图工艺形成GOA区域的至少一个GI过孔，以贯穿GOA区域的栅绝缘层，将该至少一个GI过孔处的栅线暴露在外，并通过在GOA区域的至少一个GI过孔处的栅线上形成有源层和源漏金属层的图案，实现栅线与源漏金属层的图案的直接相连。另外，通过采用同一个掩膜板，分两次构图工艺，分别形成GOA区域的至少一个GI过孔和显示区域的至少一个VIA过孔，降低了产品的制作成本。
以上所述仅为本公开的较佳实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (9)

  1. 一种掩膜板，其包括：对应阵列基板行驱动电路GOA区域的第一区域和对应阵列基板显示区域的第二区域；
    所述第一区域具有至少一个第一开口，所述至少一个第一开口用于在所述阵列基板行驱动电路GOA区域形成栅绝缘层的GI过孔，所述GI过孔用于暴露出栅线；
    所述第二区域具有至少一个第二开口，所述至少一个第二开口为半色调掩膜开口，所述至少一个第二开口用于在所述阵列基板显示区域形成VIA过孔，所述VIA过孔用于暴露出源漏金属层的图案。
  2. 如权利要求1所述的掩膜板，其中，所述掩膜板还包括：对应阵列基板集成电路接口IC Pad区域的第三区域；
    所述第三区域具有至少一个第三开口，所述至少一个第三开口为半色调掩膜开口，且所述至少一个第三开口用于在所述阵列基板集成电路接口IC Pad区域形成VIA过孔。
  3. 如权利要求1或2所述的掩膜板，其中，所述掩膜板还包括：对应阵列基板信号线区域的第四区域；
    所述第四区域具有至少一个第四开口，所述至少一个第四开口用于在所述阵列基板信号线区域形成GI过孔。
  4. 一种阵列基板的制造方法，其采用权利要求1-3中的任意一项所述的掩膜板，其包括以下步骤：
    在透明基板上形成栅线图案；
    在形成有栅线图案的基板上形成栅绝缘层；
    在所述栅绝缘层的表面，采用所述掩膜板，通过构图工艺在阵列基板行驱动电路GOA区域形成至少一个栅绝缘层的GI过孔，所述至少一个GI过孔用于贯穿所述栅绝缘层以暴露出所述栅线；
    在形成有至少一个GI过孔的基板表面依次形成有源层和源漏金属层的图案，在所述阵列基板行驱动电路GOA区域，所述栅线与所述源漏金属层的图案在所述至少一个GI过孔位置处直接相连；
    在形成有有源层和源漏金属层的图案的基板上形成保护层；
    在所述保护层的表面，采用所述掩膜板，通过构图工艺在所述阵列基板显示区域形成至少一个VIA过孔，所述至少一个VIA过孔用于贯穿所述保护层以暴露出所述源漏金属层的图案。
  5. 如权利要求4所述的阵列基板的制造方法，其中，在所述栅绝缘层的表面，采用所述掩膜板，通过构图工艺在阵列基板行驱动电路GOA区域形成至少一个栅绝缘层的GI过孔的步骤包括：
    在所述栅绝缘层上涂覆光刻胶；
    采用所述掩膜板，对涂覆光刻胶的基板进行曝光；
    对曝光后的基板进行显影和刻蚀，从而形成位于阵列基板行驱动电路GOA区域的至少一个GI过孔。
  6. 如权利要求4所述的阵列基板的制造方法，其中，在所述栅绝缘层的表面，采用所述掩膜板，通过构图工艺在阵列基板行驱动电路GOA区域形成至少一个栅绝缘层的GI过孔的步骤还包括：
    在所述栅绝缘层的表面，采用所述掩膜板，通过构图工艺分别形成位于阵列基板行驱动电路GOA区域的至少一个GI过孔以及位于阵列基板信号线区域的至少一个GI过孔。
  7. 如权利要求4所述的阵列基板的制造方法，其中，在所述保护层的表面，采用所述掩膜板，通过构图工艺在所述阵列基板显示区域形成至少一个VIA过孔的步骤包括：
    在所述保护层上涂覆光刻胶；
    采用所述掩膜板，对涂覆光刻胶的基板进行曝光；
    对曝光后的基板进行显影、灰化和刻蚀，从而形成位于所述阵列基板显 示区域的至少一个VIA过孔。
  8. 如权利要求4-7中的任意一项所述的阵列基板的制造方法，其中，在所述保护层的表面，采用所述掩膜板，通过构图工艺在所述阵列基板显示区域形成至少一个VIA过孔的步骤还包括：
    在所述保护层的表面，采用所述掩膜板，通过构图工艺分别形成位于所述阵列基板显示区域的至少一个VIA过孔以及位于阵列基板集成电路接口IC Pad区域的至少一个VIA过孔。
  9. 如权利要求4所述的阵列基板的制造方法，其中，
    在所述保护层的表面，采用所述掩膜板，通过构图工艺在所述阵列基板显示区域形成至少一个VIA过孔时，还在所述保护层的与所述栅线与所述源漏金属层的图案直接相连的区域对应的地方形成过孔；
    在所述保护层的表面，采用所述掩膜板，通过构图工艺在所述阵列基板显示区域形成至少一个VIA过孔之后，还在所述保护层的与所述栅线与所述源漏金属层的图案直接相连的区域对应的地方形成的过孔处，在所述源漏金属层的图案表面形成透明电极的图案。
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