WO2021170042A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2021170042A1
WO2021170042A1 PCT/CN2021/077923 CN2021077923W WO2021170042A1 WO 2021170042 A1 WO2021170042 A1 WO 2021170042A1 CN 2021077923 W CN2021077923 W CN 2021077923W WO 2021170042 A1 WO2021170042 A1 WO 2021170042A1
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WIPO (PCT)
Prior art keywords
layer
display substrate
source
display
base substrate
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PCT/CN2021/077923
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English (en)
French (fr)
Inventor
孟会杰
宋二龙
周宏军
刘聪
魏锋
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/433,217 priority Critical patent/US11810924B2/en
Publication of WO2021170042A1 publication Critical patent/WO2021170042A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • the present disclosure relates to the field of display technology, in particular to a display substrate, a manufacturing method thereof, and a display device.
  • the electrical test (ET) lighting is used to detect whether the display screen of the display substrate is normal, but how to ensure the flexible printed circuit (FPC) and the display substrate wiring area when performing the ET lighting test.
  • FPC flexible printed circuit
  • the technical problem to be solved by the present disclosure is to provide a display substrate, a manufacturing method thereof, and a display device.
  • a display substrate including an electrical inspection area, wherein:
  • At least one test electrode and an insulating structure surrounding the test electrode are provided in the electrical detection area.
  • the distance is not greater than the distance between the surface of the test electrode that is far from the base substrate and the base substrate,
  • the display substrate further includes a display area, and the electrical detection area is located at the periphery of the display area;
  • the test electrode is used to make physical contact with the pins of the flexible circuit board of the display substrate, so as to perform an electrical test on the display substrate.
  • the distance between the surface of the insulating structure far from the base substrate of the display substrate and the base substrate is smaller than the distance between the surface of the test electrode far away from the base substrate and the base substrate. The distance between the base substrates.
  • the display substrate includes an active layer, a gate insulating layer, a gate metal layer, an interlayer insulating layer, a first source-drain metal layer, a passivation layer, and a first flat layer that are sequentially arranged along a direction away from the base substrate.
  • Layer, a second source and drain metal layer, a second flat layer, the insulating film layer of the display substrate includes the gate insulating layer, the interlayer insulating layer, the passivation layer, the first flat layer and the For the second flat layer, the number of film layers included in the insulating structure is less than the total number of insulating film layers of the display substrate.
  • the orthographic projection of the first source/drain metal layer on the base substrate falls into the orthographic projection of the second source/drain metal layer on the base substrate within.
  • a plurality of the test electrodes are arranged in the electrical detection area, and adjacent test electrodes of the plurality of test electrodes are arranged separately from each other.
  • the insulating structure includes the passivation layer and the first flat layer; or, the insulating structure includes the passivation layer and the second flat layer.
  • the display substrate includes an active layer, a gate insulating layer, a gate metal layer, an interlayer insulating layer, a first source-drain metal layer, a passivation layer, and a first flat layer that are sequentially arranged along a direction away from the base substrate.
  • Layer, a second source and drain metal layer, a second flat layer, the insulating film layer of the display substrate includes the gate insulating layer, the interlayer insulating layer, the passivation layer, the first flat layer and the For the second flat layer, the film thickness of at least one insulating film layer included in the insulating structure is smaller than the film thickness of the same insulating film layer in other regions of the display substrate.
  • the test electrode includes a pattern of a first source-drain metal layer and a pattern of a second source-drain metal layer that are stacked.
  • a passivation layer is provided between the pattern of the first source-drain metal layer and the pattern of the second source-drain metal layer, and the pattern of the first source-drain metal layer and the second source-drain metal layer The pattern of the metal layer is connected by a via hole penetrating the passivation layer.
  • the second flat layer is only provided in the display area.
  • the embodiment of the present disclosure also provides a display device including the display substrate as described above.
  • the embodiments of the present disclosure also provide a manufacturing method of a display substrate, the display substrate including an electrical detection area, and the manufacturing method includes:
  • At least one test electrode and an insulating structure surrounding the test electrode are formed in the electrical detection area, and the distance between the surface of the insulating structure and the base substrate of the display substrate is different from that of the base substrate. It is greater than the distance between the surface of the test electrode that is far from the base substrate and the base substrate.
  • the display substrate includes an active layer, a gate insulating layer, a gate metal layer, an interlayer insulating layer, a first source-drain metal layer, a passivation layer, and a first flat layer that are sequentially arranged along a direction away from the base substrate.
  • Layer, a second source and drain metal layer, a second flat layer, the insulating film layer of the display substrate includes the gate insulating layer, the interlayer insulating layer, the passivation layer, the first flat layer and the The second flat layer, forming the insulating structure includes:
  • the first flat layer of the electrical detection area is removed.
  • the display substrate includes an active layer, a gate insulating layer, a gate metal layer, an interlayer insulating layer, a first source-drain metal layer, a passivation layer, and a first flat layer that are sequentially arranged along a direction away from the base substrate.
  • Layer, a second source and drain metal layer, a second flat layer, the insulating film layer of the display substrate includes the gate insulating layer, the interlayer insulating layer, the passivation layer, the first flat layer and the The second flat layer, forming the insulating structure includes:
  • the second flat layer of the electrical detection area is removed.
  • FIG. 1 is a schematic plan view showing the electrical detection area in the substrate in the related art
  • Fig. 2 is a schematic cross-sectional view in the AA direction of Fig. 1;
  • Figure 3 is a schematic diagram of the flexible circuit board crimped to the electrical inspection area
  • FIG. 4 is a schematic plan view showing an electrical detection area in a substrate according to an embodiment of the present disclosure
  • FIG. 5 is a schematic cross-sectional view in the AA direction of FIG. 4;
  • FIG. 6 is a schematic diagram of a flexible circuit board crimped to an electrical detection area according to an embodiment of the disclosure
  • FIG. 7 is a schematic cross-sectional view of another embodiment of the disclosure showing an electrical detection area in a substrate
  • FIG. 8 is a schematic diagram of a flexible circuit board crimped to an electrical detection area according to another embodiment of the present disclosure.
  • the active-matrix organic light-emitting diode (AMOLED) flexible display uses ET to detect whether the display substrate can display the picture normally. During lighting inspection, the pads of the ET flexible printed circuit (FPC) are crimped on the test electrodes (pads) of the electrical inspection area of the display substrate.
  • FPC ET flexible printed circuit
  • the test electrode 21 in the electrical detection area is formed by stacking a double-layer source/drain metal layer (a first source/drain metal layer 211 and a second source/drain metal layer 212).
  • a double-layer source/drain metal layer a first source/drain metal layer 211 and a second source/drain metal layer 212.
  • an insulating structure is provided around the test electrode 21.
  • the insulating structure includes a passivation layer 23, a first flat layer 24, and a second flat layer 25.
  • the insulating structure is greater than the surface height of the test electrode 21, that is, the distance between the side surface of the insulating structure away from the base substrate of the display substrate and the base substrate is greater than that of the side surface of the test electrode 21 away from the base substrate and the base substrate the distance between.
  • the outermost part of the insulating structure is the second flat layer 25, and the distance between the surface of the second flat layer 25 away from the base substrate and the base substrate is greater than that of the test electrode 21 on the side away from the base substrate.
  • the thickness of the insulating structure formed with the passivation layer 23 is relatively large, so that the pins 26 of the flexible circuit board cannot contact the test electrode 21, or there is a problem of poor crimping with the test electrode 21, which causes the display substrate to fail to light up.
  • the embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device, which can ensure that the display substrate can be normally lit during electrical lighting detection.
  • the embodiment of the present disclosure provides a display substrate including a display area and an electrical detection area located at the periphery of the display area, in which at least one test electrode and an insulating structure surrounding the test electrode are provided,
  • the distance between the side surface of the insulating structure away from the base substrate of the display substrate and the base substrate is not greater than the distance between the side surface of the test electrode away from the base substrate and the base substrate. The distance between.
  • the distance between the surface of the insulating structure away from the base substrate of the display substrate and the base substrate is not greater than the distance between the surface of the test electrode away from the base substrate and the base substrate.
  • the distance between the side surface of the insulating structure away from the base substrate of the display substrate and the base substrate may be equal to or less than the distance between the side surface of the test electrode away from the base substrate and the base substrate.
  • the display substrate includes an active layer, a gate insulating layer, a gate metal layer, an interlayer insulating layer, a first source and drain metal layer, a passivation layer, a first flat layer, and a second layer which are sequentially arranged along a direction away from the base substrate.
  • the insulating film layer of the display substrate includes the gate insulating layer, the interlayer insulating layer, the passivation layer, the first flat layer, and the second flat layer.
  • the insulating structure surrounding the test electrode can also be composed of these insulating film layers.
  • the distance between the side surface of the insulating structure away from the base substrate of the display substrate and the base substrate can be achieved in a variety of ways, not greater than the distance between the test electrode and the substrate.
  • the distance between one side surface of the substrate and the base substrate such as removing all or part of a certain insulating film layer constituting the insulating structure, or removing all or part of multiple insulating film layers constituting the insulating structure, so that the insulating structure is far away
  • the distance between one side surface of the base substrate of the display substrate and the base substrate is not greater than the distance between the side surface of the test electrode away from the base substrate and the base substrate.
  • the left half of FIG. 5 is the display area of the display substrate.
  • the display substrate includes an active layer 8, a gate insulating layer 9, and a gate metal layer on the base substrate 7. 10.
  • Interlayer insulating layer 13 first source/drain metal layer 11, passivation layer 3, first flat layer 4, second source/drain metal layer 12, and second flat layer 5.
  • the right half of FIG. 5 is the display substrate
  • the electrical detection area, as shown in Figures 4 to 5, the electrical detection area of the display substrate of this embodiment removes the second flat layer 5, and the outermost insulating film layer of the insulating structure away from the base substrate is the first flat layer 4. In this way, the surface height of the insulating structure can be made smaller than the surface height of the test electrode.
  • the test electrode 1 is formed by stacking the first source/drain metal layer 11 and the second source/drain metal layer 12, the first source/drain metal layer 11 and the second source/drain metal layer A passivation layer 3 is spaced between 12, and the first source-drain metal layer 11 and the second source-drain metal layer 12 are connected by a via hole penetrating the passivation layer 3.
  • the second flat layer 5 in the electrical detection area can be removed by a special patterning process; or when the pattern of the second flat layer 5 in the display area is formed, The same patterning process removes the second flat layer 5 in the electrical inspection area at the same time, so that the number of patterning processes for manufacturing the display substrate can be reduced, and the production cost of the display substrate can be reduced.
  • the left half of FIG. 7 is the display area of the display substrate.
  • the display substrate includes an active layer 8, a gate insulating layer 9, and a gate metal layer 10 on the base substrate 7.
  • the right half of FIG. 7 shows the electrical inspection of the display substrate
  • the electrical detection area of the display substrate of this embodiment removes the first flat layer 4, and the outermost insulating film layer of the insulating structure away from the base substrate is the second flat layer 5, which can make the insulating structure
  • the surface height of the test electrode is smaller than the surface height of the test electrode.
  • the second flat layer 5 and the passivation layer 3 are composed of The thickness of the insulating structure of the flexible circuit board is small, the contact between the pin 6 of the flexible circuit board and the test electrode 1 is not affected by the insulating structure, and the pin 6 of the flexible circuit board can fully contact the test electrode 1, so that the display substrate can be normal ET lights up.
  • the first source-drain metal layer 11 and the second source-drain metal layer 12 are laminated to form the test electrode 1.
  • the first source-drain metal layer 11 and the second source-drain metal layer A passivation layer 3 is spaced between 12, and the first source-drain metal layer 11 and the second source-drain metal layer 12 are connected by a via hole penetrating the passivation layer 3.
  • the first flat layer 4 in the electrical detection area may be removed by a special patterning process; or when the pattern of the first flat layer 4 in the display area is formed, The same patterning process removes the first flat layer 4 in the electrical inspection area at the same time, so that the number of patterning processes for manufacturing the display substrate can be reduced, and the production cost of the display substrate can be reduced.
  • the insulating film layer of the display substrate includes a gate insulating layer, an interlayer insulating layer, a passivation layer, a first flat layer and a second flat layer, and the insulating structure includes at least one layer of insulation
  • the film thickness of the film layer is smaller than the film thickness of the same insulating film layer in other regions of the display substrate.
  • the number of insulating film layers included in the insulating structure of the electrical detection area may be the same as the total number of insulating film layers included in the display substrate, but the thickness of a part of the insulating film layers is smaller than the thickness of the same insulating film layer in other areas of the display substrate, or where The thickness of all the insulating film layers is less than the thickness of the same insulating film layer in other areas of the display substrate, so that the distance between the surface of the insulating structure and the base substrate of the base substrate away from the display substrate is different. It is greater than the distance between the surface of the test electrode that is far from the base substrate and the base substrate.
  • the insulating structure is composed of an insulating film layer.
  • the thickness of the first flat layer in the electrical detection area is less than the thickness of the first flat layer in other areas of the display substrate, or the thickness of the second flat layer in the electrical detection area is less than the thickness of the second flat layer in other areas of the display substrate
  • the thickness of the passivation layer in the electrical detection area is smaller than the thickness of the passivation layer in other areas of the display substrate, and so on.
  • the pattern of the first flat layer in other areas can be formed while the thickness of the first flat layer in the electrical detection area is reduced. Thickness; when the thickness of the second flat layer in the electrical detection area is less than the thickness of the second flat layer in other areas of the display substrate, the second flat layer in the other area can be formed while the second flat layer in the electrical detection area is thinned.
  • the thickness of the layer when the thickness of the passivation layer in the electrical detection area is less than the thickness of the passivation layer in other areas of the display substrate, the passivation layer in other areas can be formed while the passivation layer in the electrical detection area is thinned. Thickness, and so on.
  • the first flat layer in the electrical detection area When the thickness of the first flat layer in the electrical detection area is less than the thickness of the first flat layer in other areas of the display substrate, it is also possible to thin the first flat layer in the electrical detection area after the pattern of the first flat layer in other areas is formed. Thickness; when the thickness of the second flat layer in the electrical detection area is less than the thickness of the second flat layer in other areas of the display substrate, the second flat layer in the electrical detection area can be thinned after the pattern of the second flat layer in other areas is formed. Thickness, and so on.
  • the test electrode in order to make the resistance of the test electrode lower, is formed by stacking the first source/drain metal layer and the second source/drain metal layer.
  • the embodiment of the present disclosure also provides a display device including the display substrate as described above.
  • the display device includes but is not limited to: radio frequency unit, network module, audio output unit, input unit, sensor, display unit, user input unit, interface unit, memory, processor, power supply and other components.
  • the structure of the above display device does not constitute a limitation on the display device, and the display device may include more or less of the above components, or combine some components, or arrange different components.
  • the display device includes, but is not limited to, a display, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, and the like.
  • the display device may be any product or component with a display function such as a TV, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board, and a backplane.
  • the embodiments of the present disclosure also provide a method for manufacturing a display substrate, the display substrate including a display area and an electrical detection area located at the periphery of the display area, and the manufacturing method includes:
  • At least one test electrode and an insulating structure surrounding the test electrode are formed in the electrical detection area, and the distance between the surface of the insulating structure and the base substrate of the base substrate away from the display substrate is not greater than The distance between the side surface of the test electrode away from the base substrate and the base substrate.
  • the distance between the surface of the insulating structure away from the base substrate of the display substrate and the base substrate is not greater than the distance between the surface of the test electrode away from the base substrate and the base substrate.
  • the distance between the side surface of the insulating structure away from the base substrate of the display substrate and the base substrate may be equal to or less than the distance between the side surface of the test electrode away from the base substrate and the The distance between the base substrates, so that the surface height of the insulating structure will not exceed the surface height of the test electrode.
  • the display substrate includes an active layer, a gate insulating layer, a gate metal layer, an interlayer insulating layer, a first source and drain metal layer, a passivation layer, a first flat layer, and a second layer which are sequentially arranged along a direction away from the base substrate.
  • the insulating film layer of the display substrate includes the gate insulating layer, the interlayer insulating layer, the passivation layer, the first flat layer, and the second flat layer.
  • the insulating structure surrounding the test electrode can also be composed of these insulating film layers.
  • the distance between the side surface of the insulating structure away from the base substrate of the display substrate and the base substrate can be achieved in a variety of ways, not greater than the distance between the test electrode and the substrate.
  • the distance between one side surface of the substrate and the base substrate such as removing all or part of a certain insulating film layer constituting the insulating structure, or removing all or part of multiple insulating film layers constituting the insulating structure, so that the insulating structure is far away
  • the distance between one side surface of the base substrate of the display substrate and the base substrate is not greater than the distance between the side surface of the test electrode away from the base substrate and the base substrate.
  • the number of insulating film layers included in the insulating structure is less than the total number of insulating film layers of the display substrate.
  • the left half of FIG. 5 is the display area of the display substrate.
  • the display substrate includes an active layer 8, a gate insulating layer 9, and a gate metal layer on the base substrate 7. 10.
  • Interlayer insulating layer 13 first source/drain metal layer 11, passivation layer 3, first flat layer 4, second source/drain metal layer 12, and second flat layer 5.
  • the right half of FIG. 5 is the display substrate.
  • the electrical detection area, as shown in FIGS. 4 to 5, the electrical detection area of the display substrate of this embodiment removes the second flat layer 5, and the outermost insulating film layer of the insulating structure away from the base substrate is the first flat layer 4. In this way, the surface height of the insulating structure can be made smaller than the surface height of the test electrode.
  • the first source-drain metal layer 11 and the second source-drain metal layer 12 are laminated to form the test electrode 1.
  • the first source-drain metal layer 11 and the second source-drain metal layer A passivation layer 3 is spaced between 12, and the first source-drain metal layer 11 and the second source-drain metal layer 12 are connected by a via hole penetrating the passivation layer 3.
  • the second flat layer 5 in the electrical detection area can be removed by a special patterning process; or when the pattern of the second flat layer 5 in the display area is formed, The same patterning process removes the second flat layer 5 in the electrical inspection area at the same time, so that the number of patterning processes for manufacturing the display substrate can be reduced, and the production cost of the display substrate can be reduced.
  • forming the insulating structure includes:
  • the first flat layer of the electrical detection area is removed.
  • the left half of FIG. 7 is the display area of the display substrate.
  • the display substrate includes an active layer 8, a gate insulating layer 9, and a gate metal layer 10 on the base substrate 7.
  • the right half of FIG. 7 shows the electrical inspection of the display substrate
  • the electrical detection area of the display substrate of this embodiment removes the first flat layer 4, and the outermost insulating film layer of the insulating structure away from the base substrate is the second flat layer 5, which can make the insulating structure
  • the surface height of the test electrode is smaller than the surface height of the test electrode.
  • the second flat layer 5 and the passivation layer 3 are composed of The thickness of the insulating structure of the flexible circuit board is small, the contact between the pin 6 of the flexible circuit board and the test electrode 1 is not affected by the insulating structure, and the pin 6 of the flexible circuit board can fully contact the test electrode 1, so that the display substrate can be normal ET lights up.
  • the first source-drain metal layer 11 and the second source-drain metal layer 12 are laminated to form the test electrode 1.
  • the first source-drain metal layer 11 and the second source-drain metal layer A passivation layer 3 is spaced between 12, and the first source-drain metal layer 11 and the second source-drain metal layer 12 are connected by a via hole penetrating the passivation layer 3.
  • the first flat layer 4 in the electrical detection area may be removed by a special patterning process; or when the pattern of the first flat layer 4 in the display area is formed, The same patterning process removes the first flat layer 4 in the electrical inspection area at the same time, so that the number of patterning processes for manufacturing the display substrate can be reduced, and the production cost of the display substrate can be reduced.
  • forming the insulating structure includes:
  • the second flat layer of the electrical detection area is removed.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract

一种显示基板及其制作方法、显示装置，该显示基板包括电学检测区域，在该电学检测区域中设置有至少一个测试电极（1）、以及围绕该测试电极（1）的绝缘结构，该绝缘结构远离该显示基板的衬底基板（7）的一侧表面与该衬底基板（7）之间的距离不大于该测试电极（1）远离该衬底基板（7）的一侧表面与该衬底基板（7）之间的距离。

Description

显示基板及其制作方法、显示装置
相关申请的交叉引用
本公开主张在2020年2月28日在中国提交的中国专利申请No.202010130700.8的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，特别是指一种显示基板及其制作方法、显示装置。
背景技术
相关技术中，通过电学测试(Electric Test，ET)点灯检测显示基板的显示画面是否正常，但在进行该ET点灯测试时，如何保证柔性电路板(Flexible Printed Circuit，FPC)与显示基板走线区域的测试电极的有效电连接，以确保测试的正常进行，相关技术中并未给出适当的解决方案。
发明内容
本公开要解决的技术问题是提供一种显示基板及其制作方法、显示装置。
一方面，提供一种显示基板，包括电学检测区域，其中：
在所述电学检测区域中设置有至少一个测试电极、以及围绕所述测试电极的绝缘结构，所述绝缘结构远离所述显示基板的衬底基板的一侧表面与所述衬底基板之间的距离不大于所述测试电极远离所述衬底基板的一侧表面与所述衬底基板之间的距离，
其中，所述显示基板还包括显示区域，所述电学检测区域位于所述显示区域周边；
所述测试电极用于与所述显示基板的柔性电路板的引脚进行物理接触，以对所述显示基板进行电学测试。
可选地，所述绝缘结构远离所述显示基板的衬底基板的一侧表面与所述衬底基板之间的距离小于所述测试电极远离所述衬底基板的一侧表面与所述 衬底基板之间的距离。
可选地，所述显示基板包括沿远离衬底基板的方向依次设置的有源层、栅绝缘层、栅金属层、层间绝缘层、第一源漏金属层、钝化层、第一平坦层、第二源漏金属层、第二平坦层，所述显示基板的绝缘膜层包括所述栅绝缘层、所述层间绝缘层、所述钝化层、所述第一平坦层和所述第二平坦层，所述绝缘结构包括的膜层的数量小于所述显示基板的绝缘膜层的总数量。
可选地，在所述电学检测区域中，所述第一源漏金属层在所述衬底基板上的正投影落入所述第二源漏金属层在所述衬底基板上的正投影之内。
可选地，在所述电学检测区域中设置有多个所述测试电极，所述多个测试电极中的相邻测试电极之间彼此分开设置。
可选地，所述绝缘结构包括所述钝化层和所述第一平坦层；或，所述绝缘结构包括所述钝化层和第二平坦层。
可选地，所述显示基板包括沿远离衬底基板的方向依次设置的有源层、栅绝缘层、栅金属层、层间绝缘层、第一源漏金属层、钝化层、第一平坦层、第二源漏金属层、第二平坦层，所述显示基板的绝缘膜层包括所述栅绝缘层、所述层间绝缘层、所述钝化层、所述第一平坦层和所述第二平坦层，所述绝缘结构包括的至少一层绝缘膜层的膜厚小于所述显示基板其他区域相同绝缘膜层的膜厚。
可选地，所述测试电极包括层叠设置的第一源漏金属层的图形和第二源漏金属层的图形。
可选地，所述第一源漏金属层的图形和所述第二源漏金属层的图形之间设置有钝化层，所述第一源漏金属层的图形和所述第二源漏金属层的图形通过贯穿所述钝化层的过孔连接。
可选地，所述第二平坦层仅设置在所述显示区域中。
本公开实施例还提供了一种显示装置，包括如上所述的显示基板。
本公开实施例还提供了一种显示基板的制作方法，所述显示基板包括电学检测区域，所述制作方法包括：
在所述电学检测区域中形成至少一个测试电极和围绕所述测试电极的绝 缘结构，所述绝缘结构远离所述显示基板的衬底基板的一侧表面与所述衬底基板之间的距离不大于所述测试电极远离所述衬底基板的一侧表面与所述衬底基板之间的距离。
可选地，所述显示基板包括沿远离衬底基板的方向依次设置的有源层、栅绝缘层、栅金属层、层间绝缘层、第一源漏金属层、钝化层、第一平坦层、第二源漏金属层、第二平坦层，所述显示基板的绝缘膜层包括所述栅绝缘层、所述层间绝缘层、所述钝化层、所述第一平坦层和所述第二平坦层，形成所述绝缘结构包括：
在形成所述显示基板的第一平坦层的图形之后，去除所述电学检测区域的第一平坦层。
可选地，所述显示基板包括沿远离衬底基板的方向依次设置的有源层、栅绝缘层、栅金属层、层间绝缘层、第一源漏金属层、钝化层、第一平坦层、第二源漏金属层、第二平坦层，所述显示基板的绝缘膜层包括所述栅绝缘层、所述层间绝缘层、所述钝化层、所述第一平坦层和所述第二平坦层，形成所述绝缘结构包括：
在形成所述显示基板的第二平坦层的图形之后，去除所述电学检测区域的第二平坦层。
附图说明
图1为相关技术显示基板中电学检测区域的平面示意图；
图2为图1的AA方向上的截面示意图；
图3为柔性电路板压接到电学检测区域的示意图；
图4为本公开一实施例显示基板中电学检测区域的平面示意图；
图5为图4的AA方向上的截面示意图；
图6为本公开实施例柔性电路板压接到电学检测区域的示意图；
图7为本公开另一实施例显示基板中电学检测区域的截面示意图；
图8为本公开另一实施例柔性电路板压接到电学检测区域的示意图。
具体实施方式
为使本公开的实施例要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
有源矩阵有机发光二极体(Active-matrix organic light-emitting diode，AMOLED)柔性显示屏通过ET点灯检测显示基板是否能够正常显示画面。在进行点灯检测时，将ET柔性电路板(Flexible Printed Circuit，FPC)的引脚(pad)压接在显示基板电学检测区域的测试电极(pad)上。
如图1-3所示，为了降低测试电极21的电阻，电学检测区域的测试电极21由双层源漏金属层(第一源漏金属层211和第二源漏金属层212)层叠形成，在电学检测区域，围绕测试电极21设置有绝缘结构，绝缘结构包括钝化层23、第一平坦层24和第二平坦层25，在第一平坦层24和第二平坦层25层叠后，绝缘结构的表面高度大于测试电极21的表面高度，即绝缘结构远离显示基板的衬底基板的一侧表面与衬底基板之间的距离大于测试电极21远离衬底基板的一侧表面与衬底基板之间的距离。如图2所示，绝缘结构的最外侧为第二平坦层25，第二平坦层25远离衬底基板一侧的表面与衬底基板之间的距离大于测试电极21远离衬底基板一侧的表面与衬底基板之间的距离，如图3所示，在进行ET点灯时，将柔性电路板的引脚26压接在电学检测区域时，由于第二平坦层25、第一平坦层24和钝化层23组成的绝缘结构的厚度较大，导致柔性电路板的引脚26无法接触到测试电极21，或者与测试电极21之间出现压接不良的问题，导致显示基板无法点亮。
本公开的实施例提供一种显示基板及其制作方法、显示装置，能够保证显示基板在进行电学点灯检测时可以正常点亮。
本公开的实施例提供一种显示基板，包括显示区域和位于所述显示区域周边的电学检测区域，在所述电学检测区域中设置有至少一个测试电极、以及围绕所述测试电极的绝缘结构，所述绝缘结构远离所述显示基板的衬底基板的一侧表面与所述衬底基板之间的距离不大于所述测试电极远离所述衬底基板的一侧表面与所述衬底基板之间的距离。
本实施例中，绝缘结构远离显示基板的衬底基板的一侧表面与衬底基板 之间的距离不大于测试电极远离衬底基板的一侧表面与衬底基板之间的距离，这样在进行ET点灯，将柔性电路板的引脚压接在电学检测区域时，可以使得引脚与电学检测区域的测试电极之间的接触不受绝缘结构的影响，引脚可以与测试电极充分接触，使得显示基板可以正常ET点亮。
其中，所述绝缘结构远离所述显示基板的衬底基板的一侧表面与所述衬底基板之间的距离可以等于或小于所述测试电极远离所述衬底基板的一侧表面与所述衬底基板之间的距离，这样，绝缘结构的表面高度不会超出测试电极的表面高度，在进行ET点灯，将柔性电路板的引脚压接在电学检测区域时，可以使得引脚与电学检测区域的测试电极之间的接触不受绝缘结构的影响，引脚可以与测试电极充分接触，使得显示基板可以正常ET点亮。
所述显示基板包括沿远离衬底基板的方向依次设置的有源层、栅绝缘层、栅金属层、层间绝缘层、第一源漏金属层、钝化层、第一平坦层、第二源漏金属层、第二平坦层，所述显示基板的绝缘膜层包括所述栅绝缘层、所述层间绝缘层、所述钝化层、所述第一平坦层和所述第二平坦层，围绕测试电极的绝缘结构也可由这些绝缘膜层组成，可以通过多种方式实现绝缘结构远离显示基板的衬底基板的一侧表面与衬底基板之间的距离不大于测试电极远离衬底基板的一侧表面与衬底基板之间的距离，比如去除组成绝缘结构的某一个绝缘膜层的全部或者一部分，或者去除组成绝缘结构的多个绝缘膜层的全部或者一部分，使得绝缘结构远离显示基板的衬底基板的一侧表面与衬底基板之间的距离不大于测试电极远离衬底基板的一侧表面与衬底基板之间的距离。
本公开示例性实施例中，所述绝缘结构包括的绝缘膜层的数量可以小于所述显示基板的绝缘膜层的总数量。
一具体实施例中，如图4-图5所示，图5左半部分为显示基板的显示区域，显示基板包括位于衬底基板7上的有源层8、栅绝缘层9、栅金属层10、层间绝缘层13、第一源漏金属层11、钝化层3、第一平坦层4、第二源漏金属层12和第二平坦层5，图5右半部分为显示基板的电学检测区域，如图4-图5所示，本实施例的显示基板的电学检测区域去除第二平坦层5，绝缘结 构远离衬底基板的最外侧的绝缘膜层为第一平坦层4，这样可以使得绝缘结构的表面高度小于测试电极的表面高度，如图6所示，在进行ET点灯时，将柔性电路板的引脚6压接在电学检测区域时，由于第一平坦层4和钝化层3组成的绝缘结构的厚度较小，柔性电路板的引脚6与测试电极1之间的接触不受绝缘结构的影响，柔性电路板的引脚6可以与测试电极1充分接触，使得显示基板可以正常ET点亮。
本实施例中，为了使得测试电极的电阻较低，由第一源漏金属层11和第二源漏金属层12层叠组成测试电极1，第一源漏金属层11和第二源漏金属层12之间间隔有钝化层3，第一源漏金属层11和第二源漏金属层12通过贯穿钝化层3的过孔连接。
其中，可以在形成显示区域的第二平坦层5的图形后，通过专门的构图工艺去除电学检测区域的第二平坦层5；也可以在形成显示区域的第二平坦层5的图形时，通过同一次构图工艺同时去除电学检测区域的第二平坦层5，这样可以减少制作显示基板的构图工艺的次数，降低显示基板的生产成本。
另一具体实施例中，如图7所示，图7左半部分为显示基板的显示区域，显示基板包括位于衬底基板7上的有源层8、栅绝缘层9、栅金属层10、层间绝缘层13、第一源漏金属层11、钝化层3、第一平坦层4、第二源漏金属层12和第二平坦层5，图7右半部分为显示基板的电学检测区域，如图7所示，本实施例的显示基板的电学检测区域去除第一平坦层4，绝缘结构远离衬底基板的最外侧的绝缘膜层为第二平坦层5，这样可以使得绝缘结构的表面高度小于测试电极的表面高度，如图8所示，在进行ET点灯时，将柔性电路板的引脚6压接在电学检测区域时，由于第二平坦层5和钝化层3组成的绝缘结构的厚度较小，柔性电路板的引脚6与测试电极1之间的接触不受绝缘结构的影响，柔性电路板的引脚6可以与测试电极1充分接触，使得显示基板可以正常ET点亮。
本实施例中，为了使得测试电极的电阻较低，由第一源漏金属层11和第二源漏金属层12层叠组成测试电极1，第一源漏金属层11和第二源漏金属层12之间间隔有钝化层3，第一源漏金属层11和第二源漏金属层12通过贯 穿钝化层3的过孔连接。
其中，可以在形成显示区域的第一平坦层4的图形后，通过专门的构图工艺去除电学检测区域的第一平坦层4；也可以在形成显示区域的第一平坦层4的图形时，通过同一次构图工艺同时去除电学检测区域的第一平坦层4，这样可以减少制作显示基板的构图工艺的次数，降低显示基板的生产成本。
本公开另一实施例中，所述显示基板的绝缘膜层包括栅绝缘层、层间绝缘层、钝化层、第一平坦层和第二平坦层，所述绝缘结构包括的至少一层绝缘膜层的膜厚小于所述显示基板其他区域相同绝缘膜层的膜厚。
电学检测区域的绝缘结构包括的绝缘膜层的数量可以与显示基板包括的绝缘膜层的总数量一致，但其中一部分绝缘膜层的厚度小于显示基板其他区域相同绝缘膜层的厚度，或者，其中全部绝缘膜层的厚度均小于显示基板其他区域相同绝缘膜层的厚度，这样可以使得所述绝缘结构远离所述显示基板的衬底基板的一侧表面与所述衬底基板之间的距离不大于所述测试电极远离所述衬底基板的一侧表面与所述衬底基板之间的距离。可选地，所述绝缘结构由绝缘膜层构成。
比如，一具体示例中，电学检测区域的第一平坦层的厚度小于显示基板其他区域第一平坦层的厚度，或者，电学检测区域的第二平坦层的厚度小于显示基板其他区域第二平坦层的厚度，或者，电学检测区域的钝化层的厚度小于显示基板其他区域钝化层的厚度，等等。
在电学检测区域的第一平坦层的厚度小于显示基板其他区域第一平坦层的厚度时，可以在形成其他区域的第一平坦层的图形的同时，减薄电学检测区域的第一平坦层的厚度；在电学检测区域的第二平坦层的厚度小于显示基板其他区域第二平坦层的厚度时，可以在形成其他区域的第二平坦层的图形的同时，减薄电学检测区域的第二平坦层的厚度；在电学检测区域的钝化层的厚度小于显示基板其他区域钝化层的厚度时，可以在形成其他区域的钝化层的图形的同时，减薄电学检测区域的钝化层的厚度，以此类推。
在电学检测区域的第一平坦层的厚度小于显示基板其他区域第一平坦层的厚度时，还可以在形成其他区域的第一平坦层的图形之后，减薄电学检测 区域的第一平坦层的厚度；在电学检测区域的第二平坦层的厚度小于显示基板其他区域第二平坦层的厚度时，还可以在形成其他区域的第二平坦层的图形之后，减薄电学检测区域的第二平坦层的厚度；在电学检测区域的钝化层的厚度小于显示基板其他区域钝化层的厚度时，还可以在形成其他区域的钝化层的图形之后，减薄电学检测区域的钝化层的厚度，以此类推。
本实施例中，为了使得测试电极的电阻较低，由第一源漏金属层和第二源漏金属层层叠组成测试电极。
本公开实施例还提供了一种显示装置，包括如上所述的显示基板。该显示装置包括但不限于：射频单元、网络模块、音频输出单元、输入单元、传感器、显示单元、用户输入单元、接口单元、存储器、处理器、以及电源等部件。本领域技术人员可以理解，上述显示装置的结构并不构成对显示装置的限定，显示装置可以包括上述更多或更少的部件，或者组合某些部件，或者不同的部件布置。在本公开实施例中，显示装置包括但不限于显示器、手机、平板电脑、电视机、可穿戴电子设备、导航显示设备等。
所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板。
本公开实施例还提供了一种显示基板的制作方法，所述显示基板包括显示区域和位于所述显示区域周边的电学检测区域，所述制作方法包括：
在所述电学检测区域形成至少一个测试电极和围绕所述测试电极的绝缘结构，所述绝缘结构远离所述显示基板的衬底基板的一侧表面与所述衬底基板之间的距离不大于所述测试电极远离所述衬底基板的一侧表面与所述衬底基板之间的距离。
本实施例中，绝缘结构远离显示基板的衬底基板的一侧表面与衬底基板之间的距离不大于测试电极远离衬底基板的一侧表面与衬底基板之间的距离，这样在进行ET点灯，将柔性电路板的引脚压接在电学检测区域时，可以使得引脚与电学检测区域的测试电极之间的接触不受绝缘结构的影响，引脚可以与测试电极充分接触，使得显示基板可以正常ET点亮。
其中，所述绝缘结构远离所述显示基板的衬底基板的一侧表面与所述衬底基板之间的距离可以等于或小于所述测试电极远离所述衬底基板的一侧表面与所述衬底基板之间的距离，这样，绝缘结构的表面高度不会超出测试电极的表面高度，在进行ET点灯，将柔性电路板的引脚压接在电学检测区域时，可以使得引脚与电学检测区域的测试电极之间的接触不受绝缘结构的影响，引脚可以与测试电极充分接触，使得显示基板可以正常ET点亮。
所述显示基板包括沿远离衬底基板的方向依次设置的有源层、栅绝缘层、栅金属层、层间绝缘层、第一源漏金属层、钝化层、第一平坦层、第二源漏金属层、第二平坦层，所述显示基板的绝缘膜层包括所述栅绝缘层、所述层间绝缘层、所述钝化层、所述第一平坦层和所述第二平坦层，围绕测试电极的绝缘结构也可由这些绝缘膜层组成，可以通过多种方式实现绝缘结构远离显示基板的衬底基板的一侧表面与衬底基板之间的距离不大于测试电极远离衬底基板的一侧表面与衬底基板之间的距离，比如去除组成绝缘结构的某一个绝缘膜层的全部或者一部分，或者去除组成绝缘结构的多个绝缘膜层的全部或者一部分，使得绝缘结构远离显示基板的衬底基板的一侧表面与衬底基板之间的距离不大于测试电极远离衬底基板的一侧表面与衬底基板之间的距离。
本公开示例性实施例中，所述绝缘结构包括的绝缘膜层的数量小于所述显示基板的绝缘膜层的总数量。
一具体实施例中，如图4-图5所示，图5左半部分为显示基板的显示区域，显示基板包括位于衬底基板7上的有源层8、栅绝缘层9、栅金属层10、层间绝缘层13、第一源漏金属层11、钝化层3、第一平坦层4、第二源漏金属层12和第二平坦层5，图5右半部分为显示基板的电学检测区域，如图4-图5所示，本实施例的显示基板的电学检测区域去除第二平坦层5，绝缘结构远离衬底基板的最外侧的绝缘膜层为第一平坦层4，这样可以使得绝缘结构的表面高度小于测试电极的表面高度，如图6所示，在进行ET点灯时，将柔性电路板的引脚6压接在电学检测区域时，由于第一平坦层4和钝化层3组成的绝缘结构的厚度较小，柔性电路板的引脚6与测试电极1之间的接 触不受绝缘结构的影响，柔性电路板的引脚6可以与测试电极1充分接触，使得显示基板可以正常ET点亮。
本实施例中，为了使得测试电极的电阻较低，由第一源漏金属层11和第二源漏金属层12层叠组成测试电极1，第一源漏金属层11和第二源漏金属层12之间间隔有钝化层3，第一源漏金属层11和第二源漏金属层12通过贯穿钝化层3的过孔连接。
其中，可以在形成显示区域的第二平坦层5的图形后，通过专门的构图工艺去除电学检测区域的第二平坦层5；也可以在形成显示区域的第二平坦层5的图形时，通过同一次构图工艺同时去除电学检测区域的第二平坦层5，这样可以减少制作显示基板的构图工艺的次数，降低显示基板的生产成本。
一具体示例中，形成所述绝缘结构包括：
在形成所述显示基板的第一平坦层的图形之后，去除所述电学检测区域的第一平坦层。
另一具体实施例中，如图7所示，图7左半部分为显示基板的显示区域，显示基板包括位于衬底基板7上的有源层8、栅绝缘层9、栅金属层10、层间绝缘层13、第一源漏金属层11、钝化层3、第一平坦层4、第二源漏金属层12和第二平坦层5，图7右半部分为显示基板的电学检测区域，如图7所示，本实施例的显示基板的电学检测区域去除第一平坦层4，绝缘结构远离衬底基板的最外侧的绝缘膜层为第二平坦层5，这样可以使得绝缘结构的表面高度小于测试电极的表面高度，如图8所示，在进行ET点灯时，将柔性电路板的引脚6压接在电学检测区域时，由于第二平坦层5和钝化层3组成的绝缘结构的厚度较小，柔性电路板的引脚6与测试电极1之间的接触不受绝缘结构的影响，柔性电路板的引脚6可以与测试电极1充分接触，使得显示基板可以正常ET点亮。
本实施例中，为了使得测试电极的电阻较低，由第一源漏金属层11和第二源漏金属层12层叠组成测试电极1，第一源漏金属层11和第二源漏金属层12之间间隔有钝化层3，第一源漏金属层11和第二源漏金属层12通过贯穿钝化层3的过孔连接。
其中，可以在形成显示区域的第一平坦层4的图形后，通过专门的构图工艺去除电学检测区域的第一平坦层4；也可以在形成显示区域的第一平坦层4的图形时，通过同一次构图工艺同时去除电学检测区域的第一平坦层4，这样可以减少制作显示基板的构图工艺的次数，降低显示基板的生产成本。
一具体示例中，形成所述绝缘结构包括：
在形成所述显示基板的第二平坦层的图形之后，去除所述电学检测区域的第二平坦层。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护 范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种显示基板，包括电学检测区域，其中：
    在所述电学检测区域中设置有至少一个测试电极、以及围绕所述测试电极的绝缘结构，所述绝缘结构远离所述显示基板的衬底基板的一侧表面与所述衬底基板之间的距离不大于所述测试电极远离所述衬底基板的一侧表面与所述衬底基板之间的距离，
    其中，所述显示基板还包括显示区域，所述电学检测区域位于所述显示区域周边；
    所述测试电极用于与所述显示基板的柔性电路板的引脚进行物理接触，以对所述显示基板进行电学测试。
  2. 根据权利要求1所述的显示基板，其中，所述绝缘结构远离所述显示基板的衬底基板的一侧表面与所述衬底基板之间的距离小于所述测试电极远离所述衬底基板的一侧表面与所述衬底基板之间的距离。
  3. 根据权利要求1或2所述的显示基板，其中，所述显示基板包括沿远离衬底基板的方向依次设置的有源层、栅绝缘层、栅金属层、层间绝缘层、第一源漏金属层、钝化层、第一平坦层、第二源漏金属层、第二平坦层，所述显示基板的绝缘膜层包括所述栅绝缘层、所述层间绝缘层、所述钝化层、所述第一平坦层和所述第二平坦层，所述绝缘结构包括的膜层的数量小于所述显示基板的绝缘膜层的总数量。
  4. 根据权利要求3所述的显示基板，其中，在所述电学检测区域中，所述第一源漏金属层在所述衬底基板上的正投影落入所述第二源漏金属层在所述衬底基板上的正投影之内。
  5. 根据权利要求1或2所述的显示基板，其中，在所述电学检测区域中设置有多个所述测试电极，所述多个测试电极中的相邻测试电极之间彼此分开设置。
  6. 根据权利要求3所述的显示基板，其中，所述绝缘结构包括所述钝化层和所述第一平坦层；或，所述绝缘结构包括所述钝化层和第二平坦层。
  7. 根据权利要求1或2所述的显示基板，其中，所述显示基板包括沿远离衬底基板的方向依次设置的有源层、栅绝缘层、栅金属层、层间绝缘层、第一源漏金属层、钝化层、第一平坦层、第二源漏金属层、第二平坦层，所述显示基板的绝缘膜层包括所述栅绝缘层、所述层间绝缘层、所述钝化层、所述第一平坦层和所述第二平坦层，所述绝缘结构包括的至少一层绝缘膜层的膜厚小于所述显示基板其他区域相同绝缘膜层的膜厚。
  8. 根据权利要求1或2所述的显示基板，其中，所述测试电极包括层叠设置的第一源漏金属层的图形和第二源漏金属层的图形。
  9. 根据权利要求8所述的显示基板，其中，所述第一源漏金属层的图形和所述第二源漏金属层的图形之间设置有钝化层，所述第一源漏金属层的图形和所述第二源漏金属层的图形通过贯穿所述钝化层的过孔连接。
  10. 根据权利要求7所述的显示基板，其中，所述第二平坦层仅设置在所述显示区域中。
  11. 一种显示装置，包括如权利要求1-10中任一项所述的显示基板。
  12. 一种显示基板的制作方法，所述显示基板包括电学检测区域，所述制作方法包括：
    在所述电学检测区域中形成至少一个测试电极和围绕所述测试电极的绝缘结构，所述绝缘结构远离所述显示基板的衬底基板的一侧表面与所述衬底基板之间的距离不大于所述测试电极远离所述衬底基板的一侧表面与所述衬底基板之间的距离。
  13. 根据权利要求12所述的显示基板的制作方法，其中，所述显示基板包括沿远离衬底基板的方向依次设置的有源层、栅绝缘层、栅金属层、层间绝缘层、第一源漏金属层、钝化层、第一平坦层、第二源漏金属层、第二平坦层，所述显示基板的绝缘膜层包括所述栅绝缘层、所述层间绝缘层、所述钝化层、所述第一平坦层和所述第二平坦层，形成所述绝缘结构包括：
    在形成所述显示基板的第一平坦层的图形之后，去除所述电学检测区域的第一平坦层。
  14. 根据权利要求12所述的显示基板的制作方法，其中，所述显示基板 包括沿远离衬底基板的方向依次设置的有源层、栅绝缘层、栅金属层、层间绝缘层、第一源漏金属层、钝化层、第一平坦层、第二源漏金属层、第二平坦层，所述显示基板的绝缘膜层包括所述栅绝缘层、所述层间绝缘层、所述钝化层、所述第一平坦层和所述第二平坦层，形成所述绝缘结构包括：
    在形成所述显示基板的第二平坦层的图形之后，去除所述电学检测区域的第二平坦层。
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