WO2017016153A1 - 电连接结构、阵列基板和显示装置 - Google Patents

电连接结构、阵列基板和显示装置 Download PDF

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Publication number
WO2017016153A1
WO2017016153A1 PCT/CN2015/098268 CN2015098268W WO2017016153A1 WO 2017016153 A1 WO2017016153 A1 WO 2017016153A1 CN 2015098268 W CN2015098268 W CN 2015098268W WO 2017016153 A1 WO2017016153 A1 WO 2017016153A1
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Prior art keywords
electrical connection
conductive
layer
array substrate
connection member
Prior art date
Application number
PCT/CN2015/098268
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English (en)
French (fr)
Inventor
刘利萍
尹文祥
艾雨
韩君奇
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/127,139 priority Critical patent/US10199397B2/en
Priority to EP15891031.5A priority patent/EP3333624B8/en
Publication of WO2017016153A1 publication Critical patent/WO2017016153A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/15—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on an electrochromic effect
    • G02F1/153—Constructional details
    • G02F1/155—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/05—Flexible printed circuits [FPCs]

Definitions

  • At least one embodiment of the present disclosure is directed to an electrical connection structure, an array substrate, and a display device.
  • the liquid crystal display device is a mainstream display product including an array substrate and an opposite substrate (for example, a color filter substrate) opposed to each other, and a liquid crystal layer disposed between the array substrate and the opposite substrate.
  • the array substrate has a display area, and a driving device such as a driver IC is disposed outside the display area of the array substrate, and the driving device may be disposed on the array substrate or may be disposed outside the array substrate and through, for example, a flexible printed circuit.
  • the board is connected to the array substrate.
  • a plurality of signal lines (for example, horizontally intersecting gate lines and data lines) are disposed on the array substrate, and the signal lines extend from the display area of the array substrate and are generally electrically connected to the flexible printed circuit board outside the display area. To achieve signal transmission between the array substrate and the driving device.
  • At least one embodiment of the present disclosure provides an electrical connection structure, an array substrate, and a display device to reduce conductive structures and other devices due to undercutting at vias in an insulating layer while ensuring lower resistance The risk of signal transmission between disconnections.
  • At least one embodiment of the present disclosure provides an electrical connection structure including a first electrical connection member including a conductive structure, an insulating layer covering the conductive structure, and disposed on the insulating layer Conductive connection layer; at least one first via and at least one second via are disposed in the insulating layer, and each of the first via and each of the second via exposes the conductive a partial surface of the structure; an opening size of each of the first via holes is larger than an opening size of each of the second via holes in a direction in which the insulating layer is located; the conductive connection layer covers the at least one a via and the at least one second via are electrically connected to the conductive structure through the at least one first via and the at least one second via.
  • At least one embodiment of the present disclosure also provides an array substrate including the above electrical connection Structure.
  • At least one embodiment of the present disclosure also provides a display device including the above array substrate.
  • 1a is a schematic view showing the connection of an array substrate and a driving device
  • 1b is a cross-sectional view showing a portion of a signal line outside the display area of the array substrate
  • FIG. 2a is a schematic cross-sectional view of an electrical connection structure provided by an embodiment of the present disclosure
  • FIG. 2b is a top plan view of a first electrical connection member in an electrical connection structure according to an embodiment of the present disclosure
  • FIG. 3 is a partial cross-sectional view of an array substrate according to an embodiment of the present disclosure.
  • FIG. 1a is a schematic diagram of a connection between an array substrate and a driving device. As shown in FIG. 1a, the array substrate 1 is connected to the driving device 4 through the flexible printed circuit board 3, and a plurality of signal lines 2 extending from the display area of the array substrate 1 (shown by a broken line in FIG. 1a) and flexible printing The circuit board 3 is electrically connected.
  • Figure 1b is a cross-sectional view showing a portion of a signal line outside the display area of the array substrate.
  • each of the signal lines 2 is provided with a non-metal layer 5 (for example, formed of an insulating material), the non-metal layer 5 is for preventing the signal line 2 from being oxidized, and the non-metal layer 5 is provided with an exposed signal.
  • a non-metal layer 5 for example, formed of an insulating material
  • the non-metal layer 5 is for preventing the signal line 2 from being oxidized
  • the non-metal layer 5 is provided with an exposed signal.
  • a via 5a of a portion of the surface of the line 2 a conductive connection layer 6 (for example, formed of a transparent metal oxide material) is disposed on the non-metal layer 5, and the conductive connection layer 6 covers the via 5a in the non-metal layer 5 to prevent signals
  • the surface of the line 2 exposed by the via hole 5a is oxidized, and the conductive connection layer 6 is electrically connected to the driving device (not shown in FIG. 1b) and electrically connected to the signal line 2 through the via hole 5a, thereby driving the driving device and the signal line 2 electrically connected together.
  • the conductive connection layer 6 is generally disposed in the same layer as the transparent electrode in the array substrate, which is usually made of a transparent metal oxide (for example, indium tin oxide), because of the transparent metal oxide.
  • the material has a large resistivity, so the size of the via 5a in the non-metal layer 5 is made larger to maximize the contact area between the conductive connection layer 6 and the signal line 2, thereby minimizing the conductive connection layer 6.
  • the resistance is usually made of a transparent metal oxide (for example, indium tin oxide), because of the transparent metal oxide.
  • the via hole 5a is The undercut phenomenon is liable to occur, that is, the conductive connection layer 6 is easily broken at the step of the via hole 5a, and the position where the signal line 2 is in contact with the conductive connection layer 6 is also easily applied to the step of the via hole 5a due to the force.
  • the breakage causes the signal transmitted between the flexible printed circuit board and the array substrate to be broken, that is, an open circuit is formed, thereby causing a phenomenon such as a bright line or an abnormal lighting.
  • At least one embodiment of the present disclosure provides an electrical connection structure 01, as shown in Figures 2a and 2b, the electrical connection structure 01 comprising a first electrical connection member 10, the first electrical connection member 10 comprising a conductive structure 11, covering An insulating layer 12 of the conductive structure 11 and a conductive connecting layer 13 disposed on the insulating layer 12; at least one first via hole 12a and at least one second via hole 12b are disposed in the insulating layer 12, and each of the first via holes 12a And each of the second via holes 12b respectively exposes a part of the surface of the conductive structure 11; in the direction of the surface of the insulating layer 12, the opening size W1 of each of the first via holes 12a is larger than the opening size W2 of each of the second via holes 12b Covered by the conductive connection layer 13 disposed on the insulating layer 12
  • the at least one first via 12a and the at least one second via 12b, and the conductive connection layer 13 are electrically connected to the conductive structure 11 through the at least one first via 12
  • the conductive structure 11 may be a conductive structure of any shape (for example, a line shape or a plate shape, etc.).
  • embodiments of the present disclosure do not limit the arrangement of the first via holes and the second via holes, and the first via holes and the second via holes may be arranged in combination in any manner.
  • the insulating layer 12 on the conductive structure 11 may protect a portion of the surface of the conductive structure 11; the conductive connection layer 13 may protect the first via 12a and the second through the insulating layer 12 of the conductive structure 11.
  • the surface of the hole 12b is exposed; by providing the first via hole 12a having a larger opening size, the contact area between the conductive connection layer 13 and the conductive structure 11 is made larger, so that the conductive connection layer 13 can be ensured to have a small electrical resistance.
  • the contact area of the conductive connection layer 6 and the conductive structure 11 at the position of the second via hole having a small opening size is small, and the distance difference formed during thermal expansion and contraction is small, so that The undercut is not prone to occur at the second via. Therefore, in the case of ensuring the electrical connection effect, the first via having a larger opening size and the opening size are smaller in the embodiment of the present disclosure than in the case of using a plurality of vias having a larger opening size and the same size. In the manner of the second via combination, the second via having a smaller opening size can share the risk of undercut caused by thermal expansion and contraction between different layers of materials, and the insulating layer 12 on the conductive structure 11 is lowered.
  • the risk of undercutting occurs at the vias, which in turn reduces the risk of disconnection of the transmitted signal.
  • the second via hole 12b having a small opening size since the total number of via holes in the insulating layer 12 is increased, the effect can be reduced as compared with the manner in which a conductive via is exposed on the conductive structure.
  • the risk of signal transmission between the conductive structure and other devices (such as the driving device) caused by undercutting occurs at the via holes in the insulating layer 12.
  • the embodiment of the present disclosure is applicable to an electrical connection in which the conductive structure 11 can be protected by the insulating layer 12 and the conductive connection layer 13 and the resistance of the conductive connection layer 13 decreases as the contact area with the conductive structure 11 increases.
  • the material of the conductive structure 11 may include a metal
  • the material of the conductive connection layer 13 may include a conductive metal oxide material.
  • the size ratio of each of the second via holes 12b to each of the first via holes 12a may be 1:100 to 1:2. This can ensure that the conductive connecting layer 13 has a small electrical resistance, and the risk of signal transmission disconnection between the conductive structure 11 and other devices due to undercut at the via holes in the insulating layer can be minimized.
  • the number ratio of the first via hole 12a to the second via hole 12b may be 1:100 to 1:1.
  • the number of the first via holes 12a having a larger opening size is smaller than the second via holes 12b having a smaller opening size, so that the positions of the first via holes 12a and the second via holes 12b are facilitated, and
  • the signal transmitted between the conductive structure 11 and other devices is less likely to be broken by the undercut phenomenon than the number of the first vias is greater than the number of the first vias. .
  • each of the first via holes 12a on the surface of the insulating layer 12 may be any shape, for example, may be polygonal, circular or elliptical.
  • each of the second via holes 12b on the surface of the insulating layer 12 may also be any shape, for example, may be polygonal, circular or elliptical.
  • the disclosure includes, but is not limited to, the following.
  • the electrical connection structure 01 provided by at least one embodiment of the present disclosure may further include a second electrical connection member 20, the second electrical connection member 20 including a conductive joint 21, which is electrically connected
  • the conductive connection layer 13 of the first electrical connection member 10 is electrically connected to the second electrical connection member 20 and the conductive structure 11 of the first electrical connection member 10.
  • the conductive joint 21 of the second electrical connection member 20 may be electrically connected to the conductive connection layer 13 of the first electrical connection member 10 in any manner.
  • the conductive bonding portion 21 can be electrically connected to the conductive connection layer 13 through the first via hole 12a and/or the second via hole 12b, so as to avoid the conductive connection layer from being made of a material having a large resistivity such as a metal oxide. Impact.
  • the conductive bonding portion 21 may also be electrically connected to a portion of the conductive connection layer 13 that is outside the first via hole 12a and the second via hole 12b.
  • FIGS. 2a and 2b show only one conductive structure 11. In the case of a plurality of electrically conductive structures, the electrically conductive connection layers electrically connected to the electrically conductive structures are spaced apart from each other to prevent the electrically conductive structures from being electrically connected together.
  • the conductive bond 21 can be electrically connected to the conductive connection layer 13 by a conductive paste 30, as shown in Figure 2a. This can make the conductive bonding portion 21 sufficiently in contact with the conductive connection layer 13; and, in the case where the conductive bonding portion 21 extends into the first via hole or the second via hole and the conductive paste 30 is located in the corresponding via hole, even if The undercut occurs at the via hole, and the conductive paste 30 can also perform a certain electrical connection, thereby further reducing the signal transmission disconnection between the conductive structure and other devices due to undercut at the via hole in the insulating layer. risks of.
  • the conductive adhesive 30 may be dropped into the via hole in a manner commonly used in the art, and the embodiments of the present disclosure are not described herein.
  • the second electrical connection member 20 can be a flexible printed circuit board or a driving device such as a driver IC.
  • the conductive bonding portion 21 of the second electrical connection member 20 may be, for example, an electrode lead.
  • At least one embodiment of the present disclosure also provides an array substrate 02 comprising the electrical connection structure 01 provided by any of the above embodiments.
  • FIG. 3 is a partial cross-sectional view of an array substrate according to an embodiment of the present disclosure.
  • the array substrate 02 has a display area, and the first via 12a and the second via 12b in the insulating layer 12 are disposed outside the display area (ie, disposed in the peripheral area). Since the signal lines on the array substrate, such as the gate lines and the data lines, extend from the display area and are electrically connected to the flexible printed circuit board or the driving device at the peripheral area, the thermal expansion and contraction of the different layers of materials is easily caused in the peripheral area.
  • the undercut phenomenon occurs inconsistently, and therefore, the first via hole and the second via hole of different opening sizes are disposed in the insulating layer 12 of the peripheral region to reduce the undercut at the via hole between the different layer materials as a whole. The risk of the phenomenon.
  • a metal layer (for example, a gate metal layer 71' where the gate 71 of the thin film transistor 70 is located, or a source/drain metal layer 73' where the source 73 and the drain 74 are located) is disposed in the display region of the array substrate 02, in at least one implementation.
  • the conductive structure 11 of the electrical connection structure 01 may be disposed in the same layer as the metal layer located in the display area.
  • the material forming the gate electrode 71 in the peripheral region may be left in the process of forming the gate electrode 71 in the display region to form the conductive structure 11, in which case the conductive structure 11 is, for example, a gate line or a gate contact pad;
  • the material forming the source 73 and the drain 74 in the peripheral region may be left in forming the source 73 and the drain 74 in the display region to form the conductive structure 11, in which case the conductive structure 11 is, for example Contact the pad for the data or data line.
  • the electrically conductive structure is, for example, a common electrode line or a common electrode contact pad.
  • One or more transparent electrode layers are usually disposed in the display area of the array substrate 02.
  • the array substrate used in the liquid crystal display device may be provided with a pixel electrode 75, or a pixel electrode 75 and a common electrode 76.
  • the one or more transparent electrode layers may be pixel electrodes. The layer where 75 is located or the layer where the pixel electrode 75 is located and the layer where the common electrode 76 is located.
  • the electrically conductive connection layer 13 of the electrical connection structure can include portions disposed in the same layer as at least one of the one of the transparent electrode layers or the plurality of transparent electrode layers.
  • the material forming the pixel electrode 75 in the peripheral region is left to form the conductive connection layer 13 when the pixel electrode 75 in the display region is formed; or, for example, may be separately retained in the process of forming the pixel electrode 75 and the common electrode 76 in the display region
  • the material forming the pixel electrode 75 and the material forming the common electrode 76 in the peripheral region are formed to form the conductive connection layer 13.
  • the embodiment of the present disclosure does not limit the structure of the thin film transistor 70 in the array substrate 02 and the positional relationship of the pixel electrode 75 and the common electrode 76. That is, in the thin film transistor 70, the gate 71 may be located below or above the active layer 72, and the source 73 and the drain 74 may be located below or above the active layer 72; the pixel electrode 75 and the common electrode 76 may The same layer setting or the different layer setting (the pixel electrode 75 may be located below or above the common electrode 76).
  • the array substrate provided by the embodiment of the present disclosure may also be another type of array substrate such as an OLED (Organic Light-Emitting Diode) array substrate, as long as it includes the electrical connection structure provided by any of the above embodiments.
  • OLED Organic Light-Emitting Diode
  • At least one embodiment of the present disclosure also provides a display device comprising the array substrate provided by any of the above embodiments.
  • the display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种电连接结构、阵列基板和显示装置，所述电连接结构(01)包括第一电连接构件(10)，其包括：导电结构(11)；覆盖所述导电结构(11)且设置有分别暴露出所述导电结构(11)部分表面的第一过孔(12a)和第二过孔(12b)的绝缘层(12)，第一过孔(12a)的开口尺寸(W1)大于第二过孔(12b)的开口尺寸(W2)；以及覆盖所述第一过孔(12a)和所述第二过孔(12b)且通过所述第一过孔(12a)和所述第二过孔(12b)与所述导电结构(11)电连接的导电连接层(13)。该电连接结构(01)可以减少绝缘层(12)中的过孔处发生的咬边现象。

Description

电连接结构、阵列基板和显示装置 技术领域
本公开的至少一个实施例涉及一种电连接结构、阵列基板和显示装置。
背景技术
随着显示技术的飞速发展，显示装置已经逐渐遍及人们的生活。
液晶显示装置是一种主流的显示产品，其包括相互对置的阵列基板和对置基板(例如彩膜基板)，以及设置于阵列基板和对置基板之间的液晶层。阵列基板具有显示区，在阵列基板的显示区外设置有驱动器件，例如驱动IC(Integrated Circuit)，该驱动器件可以设置在阵列基板上，也可以设置在阵列基板之外并且通过例如柔性印刷电路板与阵列基板连接。阵列基板上设置有各种信号线(例如横纵交叉的栅线和数据线)，这些信号线从阵列基板的显示区中延伸出来并且通常与显示区外的柔性印刷电路板电连接在一起，以实现阵列基板与驱动器件之间的信号传输。
发明内容
本公开的至少一个实施例提供了一种电连接结构、阵列基板和显示装置，以在保证较低电阻的前提下降低因绝缘层中的过孔处发生咬边现象导致的导电结构与其它器件之间的信号传输断开的风险。
本公开的至少一个实施例提供了一种电连接结构，其包括第一电连接构件，所述第一电连接构件包括导电结构、覆盖所述导电结构的绝缘层以及设置在所述绝缘层上的导电连接层；所述绝缘层中间隔设置有至少一个第一过孔和至少一个第二过孔，每个所述第一过孔和每个所述第二过孔分别暴露出所述导电结构的部分表面；沿所述绝缘层所在面方向上，每个所述第一过孔的开口尺寸大于每个所述第二过孔的开口尺寸；所述导电连接层覆盖所述至少一个第一过孔和所述至少一个第二过孔并且通过所述至少一个第一过孔和所述至少一个第二过孔与所述导电结构电连接。
本公开的至少一个实施例还提供了一种阵列基板，其包括上述电连接结 构。
本公开的至少一个实施例还提供了一种显示装置，其包括上述阵列基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1a为一种阵列基板与驱动器件的连接示意图；
图1b为一种信号线在阵列基板的显示区外的部分的剖视示意图；
图2a本公开的实施例提供的一种电连接结构的剖视示意图；
图2b为本公开的实施例提供的一种电连接结构中第一电连接构件的俯视示意图；
图3为本公开的实施例提供的一种阵列基板的局部剖视示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地 改变。
图1a为一种阵列基板与驱动器件的连接示意图。如图1a所示，阵列基板1通过柔性印刷电路板3与驱动器件4连接，从阵列基板1的显示区(如图1a中的虚线所示)中延伸出来的多条信号线2与柔性印刷电路板3电连接。
图1b为一种信号线在阵列基板的显示区外的部分的剖视示意图。如图1b所示，每条信号线2上设置有非金属层5(例如采用绝缘材料形成)，非金属层5用于防止该信号线2被氧化，非金属层5中设置有暴露出信号线2的部分表面的过孔5a；在非金属层5上设置有导电连接层6(例如采用透明金属氧化物材料形成)，导电连接层6覆盖非金属层5中的过孔5a以防止信号线2的被过孔5a暴露出的表面氧化，导电连接层6与驱动器件(图1b中未示出)电连接并且通过过孔5a与信号线2电连接，由此将驱动器件与信号线2电连接在一起。
在研究中，本申请的发明人注意到，导电连接层6一般与阵列基板中的透明电极同层设置，其通常采用透明金属氧化物(例如氧化铟锡)等材料制作，由于透明金属氧化物材料的电阻率较大，因此非金属层5中的过孔5a的尺寸制作得较大，以尽量增大导电连接层6与信号线2之间的接触面积，从而尽量减小导电连接层6的电阻。由于在显示装置的制作过程中有较多的高温工艺，并且由于信号线2、位于信号线2上的非金属层5和导电连接层6的材料的热胀冷缩程度不一致，过孔5a处容易发生咬边(under cut)现象，即：导电连接层6在过孔5a的台阶处容易断裂，并且信号线2与导电连接层6接触的位置因受力也容易在过孔5a的台阶处断裂，这使得在柔性印刷电路板与阵列基板之间传输的信号断开，即形成开路，从而导致亮线、点灯异常等现象发生。
本公开的至少一个实施例提供了一种电连接结构01，如图2a和图2b所示，该电连接结构01包括第一电连接构件10，第一电连接构件10包括导电结构11、覆盖导电结构11的绝缘层12以及设置在绝缘层12上的导电连接层13；绝缘层12中间隔设置有至少一个第一过孔12a和至少一个第二过孔12b，每个第一过孔12a和每个第二过孔12b分别暴露出导电结构11的部分表面；沿绝缘层12所在面方向上，每个第一过孔12a的开口尺寸W1大于每个第二过孔12b的开口尺寸W2；设置在绝缘层12上的导电连接层13覆盖 上述至少一个第一过孔12a和上述至少一个第二过孔12b，并且导电连接层13通过上述至少一个第一过孔12a和上述至少一个第二过孔12b与导电结构11电连接。
需要说明的是，导电结构11可以是任意形状(例如线状或板状等)的导电结构。此外，本公开的实施例不限定第一过孔与第二过孔的排布方式，第一过孔和第二过孔可以以任意方式组合排列。
在本公开的实施例中，导电结构11上的绝缘层12可以保护导电结构11的部分表面；导电连接层13可以保护导电结构11的被绝缘层12中的第一过孔12a和第二过孔12b暴露出的表面；通过设置开口尺寸较大的第一过孔12a，使得导电连接层13与导电结构11之间的接触面积较大，从而可以保证导电连接层13具有较小的电阻。在本公开的实施例中，导电连接层6与导电结构11在开口尺寸较小的第二过孔所在位置处的接触面积较小，在热胀冷缩时形成的距离差较小，使得第二过孔处不容易发生咬边现象。因此，确保电连接效果的情况下，与采用多个开口尺寸较大且尺寸相同的过孔的方式相比，在本公开实施例提供的开口尺寸较大的第一过孔与开口尺寸较小的第二过孔组合的方式中，开口尺寸较小的第二过孔可以分担因不同层物质之间热胀冷缩引起的咬边现象的风险，降低导电结构11上的绝缘层12中的过孔处发生咬边现象的风险，进而降低传输信号断开的风险。此外，通过设置开口尺寸较小的第二过孔12b，由于增加了绝缘层12中过孔的总体数量，与导电结构上设置一个暴露出其表面的过孔的方式相比，也可以降低因绝缘层12中的过孔处发生咬边现象导致的导电结构与其它器件(例如驱动器件)之间的信号传输断开的风险。
也就是说，本公开实施例适用于导电结构11可以通过绝缘层12和导电连接层13进行保护并且导电连接层13的电阻随其与导电结构11的接触面积的增大而减小的电连接结构01。例如，导电结构11的材料可以包括金属，并且导电连接层13的材料可以包括导电金属氧化物材料。
在至少一个实施例中，每个第二过孔12b与每个第一过孔12a的尺寸比可以为1:100～1:2。这样既可以保证导电连接层13具有较小的电阻，又可以尽量降低因绝缘层中过孔处发生咬边现象而导致的导电结构11与其它器件之间的信号传输断开的风险。
在至少一个实施例中，上述第一过孔12a与上述第二过孔12b的数量比可以为1:100～1:1。在该实施例中，开口尺寸较大的第一过孔12a的数量少于开口尺寸较小的第二过孔12b，这样便于安排第一过孔12a和第二过孔12b的位置，而且在过孔总数一定的情况下，与第一过孔的数量多于第二过孔的数量的方式相比，导电结构11与其它器件之间传输的信号因咬边现象而断开的风险更低。
在本公开的实施例中，每个第一过孔12a在绝缘层12所在面上的形状可以为任意形状，例如可以为多边形、圆形或椭圆形。
在本公开的实施例中，每个第二过孔12b在绝缘层12所在面上的形状也可以为任意形状，例如可以为多边形、圆形或椭圆形。
图2b仅以第一过孔12a的形状为四边形、第二过孔12b的形状为圆形为例进行说明。本公开包括、但不限于此。
如图2a所示，本公开的至少一个实施例提供的电连接结构01还可以包括第二电连接构件20，该第二电连接构件20包括导电结合部21，该导电结合部21被电连接到第一电连接构件10的导电连接层13，以将第二电连接构件20与第一电连接构件10的导电结构11电连接。
在本公开的实施例中，第二电连接构件20的导电结合部21可以通过任意方式与第一电连接构件10的导电连接层13电连接。例如，导电结合部21可以与导电连接层13通过第一过孔12a和/或第二过孔12b电连接，这样可以尽量避免导电连接层因采用金属氧化物等电阻率较大的材料带来的影响。当然，导电结合部21也可以与导电连接层13的位于第一过孔12a和第二过孔12b之外的部分电连接。需要说明的是，图2a和图2b仅示出了一个导电结构11。在多个导电结构的情形中，与这些导电结构分别电连接的导电连接层彼此间隔开，以避免这些导电结构电连接在一起。
在至少一个实施例中，可以通过导电胶30使导电结合部21与导电连接层13电连接在一起，如图2a所示。这样可以使导电结合部21与导电连接层13充分接触；而且，在导电结合部21延伸至第一过孔或第二过孔中并且导电胶30位于该相应的过孔中的情况下，即使该过孔处发生咬边现象，导电胶30也可以起到一定的电连接作用，从而进一步降低因绝缘层中的过孔处发生咬边现象导致的导电结构与其它器件之间信号传输断开的风险。
需要说明的是，可以采用本领域常用的方式将导电胶30滴入过孔中，本公开实施例不做赘述。
例如，第二电连接构件20可以为柔性印刷电路板或者驱动器件，例如驱动IC。
第二电连接构件20为柔性印刷电路板或者驱动器件时，第二电连接构件20的导电结合部21例如可以为电极引脚。
本公开的至少一个实施例还提供了一种阵列基板02，其包括上述任一项实施例提供的电连接结构01。
图3为本公开的实施例提供的一种阵列基板的局部剖视示意图。如图3所述，阵列基板02具有显示区，绝缘层12中的第一过孔12a和第二过孔12b设置于显示区之外(即设置于周边区内)。由于阵列基板上的例如栅线和数据线等信号线从显示区延伸出来之后在周边区处与柔性印刷电路板或驱动器件等进行电连接，在周边区内容易因不同层物质的热胀冷缩程度不一致发生咬边现象，因此，在周边区的绝缘层12中设置不同开口尺寸的第一过孔和第二过孔，以在总体上降低不同层物质之间在过孔处发生咬边现象的风险。
阵列基板02的显示区中设置有金属层(例如薄膜晶体管70的栅极71所在的栅金属层71’、或者源极73和漏极74所在的源漏金属层73’)，在至少一个实施例中，电连接结构01的导电结构11可以与位于显示区的该金属层同层设置。例如，可以在形成显示区中的栅极71的过程中保留周边区中的形成栅极71的材料以形成导电结构11，在这种情况下，导电结构11例如为栅线或栅接触垫；或者，例如，可以在形成显示区中的源极73和漏极74时保留周边区中的形成源极73和漏极74的材料以形成导电结构11，在这种情况下，导电结构11例如为数据线或数据线接触垫。或者，导电结构例如为公共电极线或公共电极接触垫。
阵列基板02的显示区中通常设置有一层或多层透明电极层。以用于液晶显示装置的阵列基板为例，阵列基板中可以设置有像素电极75，或者像素电极75和公共电极76，在这种情况下，上述一层或多层透明电极层可以为像素电极75所在的层或者像素电极75所在的层以及公共电极76所在的层。
在至少一个实施例中，电连接结构的导电连接层13可以包括与上述一层透明电极层或多层透明电极层中的至少一层同层设置的部分。例如，可以在 形成显示区中的像素电极75时保留周边区中的形成像素电极75的材料以形成导电连接层13；或者，例如，可以在形成显示区中的像素电极75和公共电极76的过程中分别保留周边区中的形成像素电极75的材料和形成公共电极76的材料，以形成导电连接层13。
需要说明的是，本公开的实施例不限定阵列基板02中薄膜晶体管70的结构，以及像素电极75和公共电极76的位置关系。也就是说，薄膜晶体管70中，栅极71可以位于有源层72的下方或上方，并且源极73和漏极74可以位于有源层72的下方或上方；像素电极75和公共电极76可以同层设置或异层设置(像素电极75可以位于公共电极76下方或上方)。本公开的实施例提供的阵列基板也可以为OLED(Organic Light-Emitting Diode，有机发光二极管)阵列基板等其它类型的阵列基板，只要其包括上述任一实施例提供的电连接结构即可。
本公开的至少一个实施例还提供了一种显示装置，其包括上述任一项实施例提供的阵列基板。
例如，该显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。
本申请要求于2015年7月28日递交的中国专利申请第201520566486.5号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (13)

  1. 一种电连接结构，包括第一电连接构件，其中，所述第一电连接构件包括：
    导电结构；
    覆盖所述导电结构的绝缘层，其中，所述绝缘层中间隔设置有至少一个第一过孔和至少一个第二过孔，每个所述第一过孔和每个所述第二过孔分别暴露出所述导电结构的部分表面；沿所述绝缘层所在面方向上，每个所述第一过孔的开口尺寸大于每个所述第二过孔的开口尺寸；以及
    设置在所述绝缘层上且覆盖所述至少一个第一过孔和所述至少一个第二过孔的导电连接层，所述导电连接层通过所述至少一个第一过孔和所述至少一个第二过孔与所述导电结构电连接。
  2. 根据权利要求1所述的电连接结构，其中，所述导电结构的材料包括金属，并且所述导电连接层的材料包括导电金属氧化物材料。
  3. 根据权利要求1或2所述的电连接结构，其中，所述第一过孔与所述第二过孔的数量比为1:100～1:1。
  4. 根据权利要求1至3中任一项所述的电连接结构，其中，每个所述第二过孔与每个所述第一过孔的尺寸比为1:100～1:2。
  5. 根据权利要求1至4中任一项所述的电连接结构，其中，
    每个所述第一过孔和/或每个所述第二过孔在所述绝缘层所在面上的形状包括多边形、圆形或椭圆形。
  6. 根据权利要求1至5中任一项所述的电连接结构，还包括第二电连接构件，其中，
    所述第二电连接构件包括导电结合部，
    所述第二电连接构件的所述导电结合部被电连接到所述第一电连接构件的所述导电连接层，以将所述第二电连接构件与所述第一电连接构件的所述导电结构电连接。
  7. 根据权利要求6所述的电连接结构，其中，所述第二电连接构件为柔性印刷电路板或者驱动器件。
  8. 根据权利要求6或7所述的电连接结构，其中，所述第二电连接构件 的所述导电结合部通过导电胶电连接到所述第一电连接构件的所述导电连接层。
  9. 一种阵列基板，包括根据权利要求1-8任一项所述的电连接结构。
  10. 根据权利要求9所述的阵列基板，其中，所述阵列基板具有显示区，所述第一过孔和所述第二过孔设置于所述显示区之外。
  11. 根据权利要求9所述的阵列基板，其中，
    所述阵列基板具有显示区，所述显示区中设置有金属层，所述电连接结构的所述导电结构与所述金属层同层设置。
  12. 根据权利要求9所述的阵列基板，其中，
    所述阵列基板具有显示区，所述显示区中设置有一层或多层透明电极层，所述电连接结构的所述导电连接层包括与所述一层透明电极层或所述多层透明电极层中的至少一层同层设置的部分。
  13. 一种显示装置，包括根据权利要求9-12任一项所述的阵列基板。
PCT/CN2015/098268 2015-07-28 2015-12-22 电连接结构、阵列基板和显示装置 WO2017016153A1 (zh)

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