WO2017133089A1 - 阵列基板、覆晶薄膜、显示面板及显示装置 - Google Patents

阵列基板、覆晶薄膜、显示面板及显示装置 Download PDF

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Publication number
WO2017133089A1
WO2017133089A1 PCT/CN2016/080646 CN2016080646W WO2017133089A1 WO 2017133089 A1 WO2017133089 A1 WO 2017133089A1 CN 2016080646 W CN2016080646 W CN 2016080646W WO 2017133089 A1 WO2017133089 A1 WO 2017133089A1
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Prior art keywords
array substrate
pads
pad
flip chip
display area
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PCT/CN2016/080646
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English (en)
French (fr)
Inventor
李红
陈立强
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京东方科技集团股份有限公司
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Priority to US15/538,712 priority Critical patent/US10784187B2/en
Publication of WO2017133089A1 publication Critical patent/WO2017133089A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • G—PHYSICS
    • G04—HOROLOGY
    • G04B—MECHANICALLY-DRIVEN CLOCKS OR WATCHES; MECHANICAL PARTS OF CLOCKS OR WATCHES IN GENERAL; TIME PIECES USING THE POSITION OF THE SUN, MOON OR STARS
    • G04B19/00—Indicating the time by visual means
    • G04B19/04—Hands; Discs with a single mark or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/0905—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/091—Disposition
    • H01L2224/0912—Layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes

Definitions

  • Embodiments of the present invention relate to an array substrate, a flip chip, a display panel, and a display device.
  • Flat panel displays are currently the most popular displays, which are widely used in electronic products such as computer screens and mobile phones because of their slim profile, power saving and no radiation.
  • An embodiment of the present invention provides an array substrate having a display area and a binding area located around the display area, the array substrate includes a plurality of first pads located in the binding area, and the first soldering The length direction of the disk faces the display area.
  • Another embodiment of the present invention provides a flip chip having a central region and a bonding region at a periphery of the central region, the flip chip comprising a plurality of second pads located in the bonding region, The length direction of the second pad faces the central area.
  • a further embodiment of the present invention provides a display panel including an array substrate and a flip chip, the array substrate including a plurality of first pads, the flip chip comprising a plurality of second pads, the array substrate and The flip chip is bonded to the second pad by the first pad, wherein a length direction of the first pad faces a display area of the array substrate; The two pads are disposed in a one-to-one correspondence with the plurality of the first pads.
  • Yet another embodiment of the present invention provides a display device including the above display panel.
  • FIG. 1 is a schematic structural view of an array substrate according to a first embodiment of the present invention
  • FIG. 2 is a first embodiment of the array substrate according to the first embodiment of the present invention after deformation and a flip chip Schematic diagram of the positional relationship;
  • FIG. 3 is a schematic view showing the positional relationship between the deformed film and the flip chip after the second embodiment of the array substrate according to the first embodiment of the present invention
  • FIG. 4 is a schematic view showing a positional relationship between a deformed film and a flip chip after the third case of the array substrate according to the first embodiment of the present invention
  • FIG. 5 is a schematic view showing a positional relationship between a deformed film and a flip chip after the fourth case of the array substrate according to the first embodiment of the present invention
  • FIG. 6 is a schematic view showing a positional relationship between a deformed film and a flip chip after the fifth case of the array substrate according to the first embodiment of the present invention
  • FIG. 7 is a schematic view showing a single-sided external lead of a flip chip of a first embodiment of the present invention.
  • FIG. 8 is a schematic view showing a double-sided external lead of a flip chip of the first embodiment of the present invention.
  • Fig. 9 is a schematic view of a display panel of a first embodiment of the present invention.
  • the display device mainly includes a color filter substrate, an array substrate, and a chip on film (COF); wherein the array substrate has a display area for displaying and a binding area at the periphery of the display area (Bonding) Area), the end of the lead in the display area (ie, the pad) is located in the binding area; the flip chip is provided with a lead and a chip on one side, and one end of the lead on the flip chip is connected to the chip, and the other end also has a pad For binding to the pad of the binding area on the display array substrate, the signal provided by the chip is transmitted to the lead on the array substrate through the lead wire to display the display area.
  • COF chip on film
  • the inventors have found that at least the following problems exist in the related art: when the array substrate is a flexible array substrate, that is, the substrate of the array substrate is often made of a flexible material, such as an organic material such as PI or PET, other film layers are formed thereon, and When the via is formed by etching, the flexible substrate is deformed. When the pads on the flip chip are bonded to the pads on the array substrate, the alignment is misaligned and misaligned, so that the two are not bound. A short circuit between a solid or adjacent pad.
  • Embodiments of the present invention provide an array substrate and flip chip which are compatible with expansion and contraction changes of an array substrate. Film, display panel and display device.
  • the present embodiment provides a display panel 100 including an array substrate 10 and a flip chip 20.
  • the array substrate 10 has a display area Q1 for display and a binding area Q2 located around the display area Q1.
  • a plurality of first pads 1 are disposed in the bonding region Q2 of the array substrate 10, and the plurality of first pads 1 are arranged around the display region Q1.
  • the length direction of the first pad 1 faces the display area Q1.
  • each of the first pads 1 has a rectangular surface having a long side and a short side.
  • the length direction of the first pad 1 toward the display region Q1 means that an extension of the long side of the rectangular surface of the first pad 1 passes through the display region Q1.
  • each of the first pads 1 has a strip shape extending in the length direction of the first pad 1.
  • the corresponding flip chip 20 includes a second pad 2 arranged in the same manner as the first pad 1, that is, the second pad 2 is arranged in a ring shape, and the length direction of the second pad 2 is arranged in a ring shape. Central area Q1.
  • the plurality of second pads 2 on the flip chip 20 can overlap one-to-one with the plurality of first pads 1 on the array substrate 10.
  • the first pad 1 on the array substrate 10 and the second pad 2 on the flip chip 20 are arranged in an annular manner around the display area Q1, and the length direction thereof faces the display area Q1, which can effectively improve
  • the outward expansion or the inward contraction deformation of the array substrate during the preparation process causes a problem that the first pad 1 and the second pad 2 are poorly bonded.
  • FIGS. 2 to 6 a plurality of first pads 1 schematically represent an array substrate 10, and a plurality of second pads 2 schematically represent a flip chip 20, so that FIGS. 2 to 6 schematically show the display. Panel 100.
  • the array substrate is uniformly deformed when a uniform outward expansion occurs, that is, the first pad 1 on the array substrate is opposite to the second pad on the flip chip. 2 outwardly misaligned part of the structure, but it is not difficult to see that since the first pad 1 and the second pad 2 have a ring design and the length direction thereof faces the display area, the array substrate is uniformly deformed, therefore, each first Most of the structure of the pad 1 is also bonded to its corresponding second pad 2 so as not to affect the robustness of the bonding of the first pad 1 to the second pad 2.
  • the array substrate is uniformly deformed when uniform inward shrinkage occurs, that is, the first pad 1 on the array substrate is opposite to the second pad on the flip chip. 2 Inwardly offsetting part of the structure, but it is not difficult to see that since the first pad 1 and the second pad 2 have a ring design and the length direction thereof faces the display area, the array substrate is uniformly deformed, and therefore, each first Most of the structure of the pad 1 is also bonded to its corresponding second pad 2 so as not to affect the robustness of the bonding of the first pad 1 to the second pad 2.
  • the array substrate is unevenly deformed.
  • the array substrate is outwardly expanded in the X direction (row direction)
  • the upper first pad 1 and the second pad 2 are misaligned, but most of the structures are bonded together, and the first pad 1 and the second pad 2 at other positions are misaligned even if they are misaligned.
  • the position is also very small, so it does not affect the firmness of the bonding of the first pad 1 and the second pad 2.
  • the array substrate is unevenly deformed.
  • the array substrate is inwardly contracted in the X direction (row direction), it is not difficult to see from the figure that although in the X direction.
  • the upper first pad 1 and the second pad 2 are misaligned, but most of the structures are bonded together, and the first pad 1 and the second pad 2 at other positions are misaligned even if they are misaligned.
  • the position is also very small, so it does not affect the firmness of the bonding of the first pad 1 and the second pad 2.
  • the array substrate is deformed to different degrees, for example, when the array substrate is outwardly expanded in the X direction (row direction) and inwardly in the Y direction (column direction). It is not difficult to see from the figure that although the first pad 1 and the second pad 2 are misaligned in the X and Y directions, most of the structures are bound together, and the other positions are first. Even if the pad 1 and the second pad 2 are misaligned, the position of the misalignment is extremely small, so that the bonding of the first pad 1 and the second pad 2 is not affected.
  • the position of the broken line in FIGS. 2-6 indicates not only the arrangement position of the second pad 2 but also the position of the display area Q1 and the first pad 1 when the array substrate is not deformed.
  • the display area Q1 of the display device is circular.
  • the shape of the display area Q1 may be a rectangle or various regular polygons; or any shape may be used.
  • the present embodiment is particularly suitable for use in a flexible display in which the substrate of the array substrate is made of a flexible material, and thus the array substrate is flexible.
  • the technical solution of the embodiment of the present invention is also applicable to a general non-flexible display device.
  • the first pad 1 on the array substrate and the second pad 2 on the flip chip are uniformly arranged to surround the display area Q1. For example, the distance between each adjacent two first pads 1 is equal; the distance between each adjacent two second pads 2 is equal. This way of setting up helps in the array When the substrate is deformed, the first pad 1 and the second pad 2 can be well bound even if they are misaligned.
  • the flip chip 20 is further provided with a driver (Drive IC), and a plurality of leads 3, wherein one end of each lead 3 is connected to a second pad 2, and the other end is connected to a tube of the driver 4. foot.
  • the flip chip 20 may include a driver 4 or two drivers 4. As shown in FIG. 7, when the flip chip includes a driver 4, the lead 3 is connected by a single-sided external lead 3. As shown in FIG. 8, when the flip chip includes two drivers, that is, two opposite first drivers 41 and second drivers 42, a part of the leads 3 are connected to the first driver 41, and the other portion of the leads 3 are connected. Connected to the second driver 42, the access mode of the lead wires 3 is externally connected.
  • the embodiment provides a display device including the display panel in the first embodiment.
  • the display device may be any product or component having a display function, such as a liquid crystal display device, an OLED display device, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal display device, an OLED display device, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device in this embodiment has a good yield.

Abstract

提供一种阵列基板(10)、覆晶薄膜(20)、显示面板(100)及显示装置(200)。阵列基板(10)具有显示区(Q1)和位于显示区(Q1)周边的绑定区(Q2)。阵列基板(10)包括位于绑定区(Q2)的多个第一焊盘(1)，第一焊盘(1)的长度方向朝向显示区(Q1)。这样，阵列基板(10)、覆晶薄膜(20)之间的绑定被改善。

Description

阵列基板、覆晶薄膜、显示面板及显示装置 技术领域
本发明实施例涉及一种阵列基板、覆晶薄膜、显示面板及显示装置。
背景技术
平板显示器为目前主要流行的显示器，其因为具有外形轻薄、省电以及无辐射等特点而被广泛地应用于电脑屏幕、移动电话等电子产品上。
发明内容
本发明一实施例提供一种阵列基板，具有显示区和位于所述显示区周边的绑定区，所述阵列基板包括位于所述绑定区的多个第一焊盘，所述第一焊盘的长度方向朝向所述显示区。
本发明另一实施例提供一种覆晶薄膜，具有中心区和位于所述中心区周边的绑定区，所述覆晶薄膜包括位于所述绑定区的多个第二焊盘，所述第二焊盘的长度方向朝向所述中心区。
本发明又一实施例提供一种显示面板，包括阵列基板和覆晶薄膜，所述阵列基板包括多个第一焊盘，所述覆晶薄膜包括多个第二焊盘，所述阵列基板和所述覆晶薄膜通过所述第一焊盘与所述第二焊盘绑定在一起，其中，且所述第一焊盘的长度方向朝向所述阵列基板的显示区；多个所述第二焊盘与多个所述第一焊盘一一对应重叠设置。
本发明又一实施例提供一种显示装置，其包括上述的显示面板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，并非对本公开的限制。
图1为本发明的第一实施例的阵列基板的结构示意图；
图2为本发明的第一实施例的阵列基板第一种情况变形后与覆晶薄膜的 位置关系的示意图；
图3为本发明的第一实施例的阵列基板第二种情况变形后与覆晶薄膜的位置关系的示意图；
图4为本发明的第一实施例的阵列基板第三种情况变形后与覆晶薄膜的位置关系的示意图；
图5为本发明的第一实施例的阵列基板第四种情况变形后与覆晶薄膜的位置关系的示意图；
图6为本发明的第一实施例的阵列基板第五种情况变形后与覆晶薄膜的位置关系的示意图；
图7为本发明的第一实施例的覆晶薄膜的单侧外接引线的示意图；
图8为本发明的第一实施例的覆晶薄膜的双侧外接引线的示意图；
图9为本发明的第一实施例的显示面板的示意图。
具体实施方式
在相关技术中，显示装置主要包括彩膜基板、阵列基板、覆晶薄膜(COF，Chip On Film)；其中，阵列基板具有用于进行显示的显示区和位于显示区外围的绑定区(Bonding区)，显示区中引线的端头(也即焊盘)位于绑定区中；覆晶薄膜一面设有引线和芯片，覆晶薄膜上的引线一端与芯片连接，另一端上同样具有焊盘，用于与显阵列基板上绑定区的焊盘进行绑定，将芯片所提供的信号通过引线传输给阵列基板上的引线，以使显示区进行显示。
发明人发现相关技术中至少存在如下问题：当阵列基板为柔性阵列基板时，即阵列基板的基底常采用柔性材料，例如PI、PET等有机材料制成时，在其上形成其他膜层，以及刻蚀形成过孔时，会导致柔性基底变形，此时将覆晶薄膜上的焊盘与阵列基板上的焊盘进行绑定时，容易造成对位不准以及错位，致使两者绑定不牢固或者相邻焊盘之间发生短路的现象。
下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本发明实施例提供一种兼容阵列基板膨胀和收缩变化的阵列基板、覆晶 薄膜、显示面板及显示装置。
第一实施例：
结合图1-8所示，本实施例提供一种显示面板100，包括阵列基板10、覆晶薄膜20。阵列基板10具有用于显示的显示区Q1，以及位于显示区Q1周边的绑定区Q2。在阵列基板10的绑定区Q2设置有多个第一焊盘1，这多个第一焊盘1环绕显示区Q1排布。第一焊盘1的长度方向朝向显示区Q1。例如，在本实施例中，每个第一焊盘1具有一矩形表面，该矩形表面具有一长边和一短边。第一焊盘1的长度方向朝向显示区Q1是指该第一焊盘1的矩形表面的长边的延长线穿过所述显示区Q1。在另一实施例中，每个第一焊盘1具有条形形状，该条形形状的延伸方向为该第一焊盘1的长度方向。相应的覆晶薄膜20上包括与第一焊盘1排布方式相同的第二焊盘2，也即第二焊盘2呈环形排布，且第二焊盘2的长度方向朝向环形排布的中心区Q1。在一个示例中，覆晶薄膜20上的多个第二焊盘2能够与阵列基板10上的多个第一焊盘1一一对应重叠。
本实施例中阵列基板10上的第一焊盘1和覆晶薄膜20上的第二焊盘2采用围绕显示区Q1环形排布方式，且其长度方向朝向显示区Q1，可以有效的改善由于阵列基板在制备过程中出现的向外扩张或者向内收缩的变形，导致的第一焊盘1和第二焊盘2绑定不良的问题。
在图2至图6中，多个第一焊盘1示意性表示阵列基板10，多个第二焊盘2示意性表示覆晶薄膜20，从而图2至图6示意性的示出了显示面板100。
以下结合图2至图6说明本公开实施例中第一焊盘1和第二焊盘2之间的绑定情况。
第一种情况，如图2所示，阵列基板发生均匀的变形，当发生均匀的向外扩张时，也就是说阵列基板上的第一焊盘1相对于覆晶薄膜上的第二焊盘2向外错位出去部分结构，但是不难看出的是，由于第一焊盘1和第二焊盘2呈环形设计且其长度方向朝向显示区，阵列基板是均匀变形的，因此，各个第一焊盘1大部分结构还是与其对应的第二焊盘2绑定的，从而不会影响第一焊盘1与第二焊盘2绑定的牢固性。
第二种情况，如图3所示，阵列基板发生均匀的变形，当发生均匀的向内收缩时，也就是说阵列基板上的第一焊盘1相对于覆晶薄膜上的第二焊盘 2向内错位出去部分结构，但是不难看出的是，由于第一焊盘1和第二焊盘2呈环形设计且其长度方向朝向显示区，阵列基板是均匀变形的，因此，各个第一焊盘1大部分结构还是与其对应的第二焊盘2绑定的，从而不会影响第一焊盘1与第二焊盘2绑定的牢固性。
第三种情况，如图4所示，阵列基板发生不均匀的变形，当阵列基板发生沿X方向(行方向)上的向外扩张时，从图中不难看出的是，虽然在X方向上第一焊盘1与第二焊盘2会发生错位，但是仍然大部分结构是绑定在一起的，而且其他位置的第一焊盘1和第二焊盘2即使发生了错位，但是错位的位置也是非常的小，故不会影响第一焊盘1和第二焊盘2绑定的牢固性。
第四种情况，如图5所示，阵列基板发生不均匀的变形，当阵列基板发生沿X方向(行方向)上的向内收缩时，从图中不难看出的是，虽然在X方向上第一焊盘1与第二焊盘2会发生错位，但是仍然大部分结构是绑定在一起的，而且其他位置的第一焊盘1和第二焊盘2即使发生了错位，但是错位的位置也是非常的小，故不会影响第一焊盘1和第二焊盘2绑定的牢固性。
第五种情况，如图6所示，阵列基板发生不同程度的变形，例如当阵列基板发生沿X方向(行方向)上的向外扩张，以及沿Y方向(列方向)上向内收缩时，从图中不难看出的是，虽然在X和Y方向上第一焊盘1与第二焊盘2会发生错位，但是仍然大部分结构是绑定在一起的，而且其他位置的第一焊盘1和第二焊盘2即使发生了错位，但是错位的位置也是非常的小，故不会影响第一焊盘1和第二焊盘2绑定的牢固性。
在此需要说明的是，在图2-6中的虚线位置不仅表示第二焊盘2的排布位置，而且代表了阵列基板在未变形时显示区Q1以及第一焊盘1的位置。
以上例子示意显示装置的显示区Q1为圆形进行说明的，同理显示区Q1的形状也可以为矩形或者各种正多边形；也可以是任意形状。
而且本实施例特别适用与柔性显示中，即阵列基板的基底采用柔性材料制备，因此阵列基板是柔性的。当然，本发明实施例的技术方案也适用于一般的非柔性显示装置。
阵列基板上的第一焊盘1和覆晶薄膜上的第二焊盘2均是均匀的排布环绕在显示区Q1的。例如，每相邻两个第一焊盘1之间的距离是相等的；每相邻两个第二焊盘2之间的距离是相等的。这样的设置方式，有助于在阵列 基板发生变形时，使得第一焊盘1与第二焊盘2即使发生错位也可以很好的绑定在一起。
参见图7和8，覆晶薄膜20上还设置有驱动器(Drive IC)，以及多条引线3，其中每一条引线3的一端连接一个第二焊盘2，另一端则连接驱动器4的一个管脚。覆晶薄膜20上可以包括一个驱动器4，也可以包括两个驱动器4，如图7所示，当覆晶薄膜上包括一个驱动器4时，引线3的接入方式则为单侧外接引线3。如图8所示，当覆晶薄膜上包括两个驱动器时，即两相对设置的第一驱动器41和第二驱动器42，此时一部分所述引线3与第一驱动器41连接，另一部分引线3与所述第二驱动器42连接，引线3的接入方式为两侧外接。
在上述实施例中，无论阵列基板发生向外扩还是向内缩的形变，都可以保证足够的绑定位置，以使第一焊盘与第二焊盘仍然可以很好的绑定在一起。
第二实施例
本实施例提供一种显示装置，其包括第一实施例中的显示面板。
其中，显示装置可以为液晶显示装置、OLED显示装置、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本实施例中的显示装置具有较好良率。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。
本申请要求于2016年2月6日递交的中国专利申请第201610083954.2号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (14)

  1. 一种阵列基板，具有显示区和位于所述显示区周边的绑定区，所述阵列基板包括位于所述绑定区的多个第一焊盘，所述第一焊盘的长度方向朝向所述显示区。
  2. 根据权利要求1所述的阵列基板，其中，多个所述第一焊盘围绕着阵列基板的显示区排布。
  3. 根据权利要求2所述的阵列基板，其中，多个所述第一焊盘围绕着阵列基板的显示区均匀排布。
  4. 根据权利要求1至3中任一项所述的阵列基板，其中，所述阵列基板是柔性的。
  5. 根据权利要求1至4中任一项所述的阵列基板，其中，所述阵列基板的显示区为圆形、矩形、正多边形中任意一种。
  6. 一种覆晶薄膜，具有中心区和位于所述中心区周边的绑定区，所述覆晶薄膜包括位于所述绑定区的多个第二焊盘，所述第二焊盘的长度方向朝向所述中心区。
  7. 根据权利要求6所述的覆晶薄膜，其中，多个所述第二焊盘围绕着覆晶薄膜的中心区排布。
  8. 根据权利要求7所述的覆晶薄膜，其中，多个所述第二焊盘呈环形均匀排布。
  9. 根据权利要求6至8中任一项所述的覆晶薄膜，其中，还包括相对设置的第一驱动器和第二驱动器，以及多条引线；每个第二焊盘连接一条所述引线；其中一部分所述引线与第一驱动器连接，另一部分引线与所述第二驱动器连接。
  10. 根据权利要求6至8中任一项所述的覆晶薄膜，其中，还包括驱动器和多条引线；其中，每个第二焊盘连接一条所述引线，各个所述引线均与所述驱动器连接。
  11. 一种显示面板，包括阵列基板和覆晶薄膜，所述阵列基板包括多个第一焊盘，所述覆晶薄膜包括多个第二焊盘，所述阵列基板和所述覆晶薄膜通过所述第一焊盘与所述第二焊盘绑定在一起，其中，且所述第一焊盘的长 度方向朝向所述阵列基板的显示区；多个所述第二焊盘与多个所述第一焊盘一一对应重叠设置。
  12. 根据权利要求11所述的显示面板，其中，多个所述第一焊盘围绕着所述阵列基板的显示区排布。
  13. 根据权利要求12所述的显示面板，其中，多个所述第一焊盘围绕着所述阵列基板的显示区排布。
  14. 一种显示装置，包括权利要求11至13中任一项所述的显示面板。
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