WO2017140055A1 - 基板、覆晶薄膜及电子设备 - Google Patents

基板、覆晶薄膜及电子设备 Download PDF

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Publication number
WO2017140055A1
WO2017140055A1 PCT/CN2016/082420 CN2016082420W WO2017140055A1 WO 2017140055 A1 WO2017140055 A1 WO 2017140055A1 CN 2016082420 W CN2016082420 W CN 2016082420W WO 2017140055 A1 WO2017140055 A1 WO 2017140055A1
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Prior art keywords
pads
substrate
pad
flip chip
shape
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PCT/CN2016/082420
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English (en)
French (fr)
Inventor
李红
陈立强
周伟峰
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京东方科技集团股份有限公司
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Priority to US15/504,628 priority Critical patent/US10622386B2/en
Publication of WO2017140055A1 publication Critical patent/WO2017140055A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04102—Flexible digitiser, i.e. constructional details for allowing the whole digitising part of a device to be flexed or rolled like a sheet of paper
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/0905—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/091—Disposition
    • H01L2224/0912—Layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch, thickness; Using different connections on the pads

Definitions

  • the invention belongs to the technical field of display, and in particular relates to a substrate, a flip chip and an electronic device.
  • Flat panel displays are currently the most popular displays, which are widely used in electronic products such as computer screens and mobile phones because of their slim profile, power saving and no radiation.
  • the display device mainly includes a color film substrate, an array substrate, and a chip on film (COF, Chip On Film).
  • the array substrate has a display area for display and a bonding area at the periphery of the display area; the ends (ie, pads) of the leads in the display area are located in the connection area.
  • the flip chip is provided with leads and chips on one side. One end of the lead on the flip chip is connected to the chip, and the other end has a pad for bonding with the pad of the bonding area on the array substrate, and transmitting the signal provided by the chip to the lead on the array substrate through the lead. Make the display area display.
  • the substrate is a flexible substrate (that is, when the substrate of the substrate is often made of a flexible material such as an organic material such as PI or PET), other film layers are formed thereon, and When the via is etched, the flexible substrate is deformed. At this time, when the pads on the flip chip are bonded to the pads on the substrate, misalignment and misalignment are likely to occur, resulting in a weak bond or a short circuit between adjacent pads.
  • the technical solution adopted by the embodiment of the present invention is a substrate including a plurality of first pads arranged side by side along the first direction; each of the first pads has a first oppositely disposed along the first direction a side edge and a second side edge, and a third side and a fourth side edge disposed opposite each other along a second direction perpendicular to the first direction; a first side of each of the first pads and The second side is non-parallel.
  • the directly adjacent first side and second side of the adjacent two first pads are disposed in parallel with each other.
  • each of the first pads is a shape that gradually widens in the second direction.
  • each of the first pads is a shape that gradually narrows in the second direction.
  • the third side and the fourth side of each of the first pads are disposed in parallel with each other.
  • the third side of each of the first pads is located on a straight line, and the fourth side of each of the first pads is located on another straight line.
  • the substrate of the substrate is a flexible substrate.
  • the substrate is an array substrate.
  • the substrate is a touch substrate.
  • Embodiments of the present invention provide a flip chip including a plurality of second pads arranged side by side along a third direction, each of the second pads having a first oppositely disposed along the third direction a side edge and a second side edge, and a third side and a fourth side edge disposed opposite to a fourth direction perpendicular to the third direction, a first side and a first side of each of the second pad The two sides are not parallel.
  • the directly adjacent first side and second side of the adjacent two second pads are disposed in parallel with each other.
  • each of the second pads is a shape that gradually widens in the fourth direction.
  • each of the second pads is a shape that gradually narrows in the fourth direction.
  • the third side and the fourth side of each of the second pads are disposed in parallel with each other.
  • the third sides of the plurality of second pads are all on a straight line, and the fourth sides of the plurality of second pads are all located on another straight line.
  • Embodiments of the present invention provide an electronic device including the substrate as described above and a flip chip as described above; the substrate is bonded to the second pad of the flip chip by the first pad Together, the shape and distribution of the plurality of first pads are the same as the shape and distribution of the plurality of second pads, respectively.
  • the first direction and the third direction are the same; the second direction is the same as the fourth direction.
  • the substrate is an array substrate or a touch substrate.
  • the first side and the second side of each of the first pads on the substrate of the embodiment of the present invention are relatively inclined, non-parallel, which advantageously avoids a short circuit occurring during bonding.
  • the shape of each of the first pads is a shape that gradually widens or narrows in a direction from a third side to a fourth side thereof.
  • the shape of the first pad is a shape that gradually widens in a direction from the third side to the fourth side thereof, and the second pad is the same as the first pad.
  • the length of the substrate in the Y direction is correspondingly shortened, and the first pad on the flip chip is moved upward in the Y direction;
  • the shape is a shape that gradually widens in a direction from the third side to the fourth side thereof, so that the first pad and the second pad of the flip chip can still be well bonded.
  • the length of the substrate in the Y direction is equivalent to being elongated, and the first pad on the flip chip is moved downward in the Y direction;
  • the shape of the disk is gradually widened in a direction from the third side to the fourth side thereof, so that the first pad and the second pad of the flip chip can still be well bonded.
  • FIG. 1 is a schematic diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic view of a flip chip according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of arrangement of first pads of an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram showing an epitaxial extension of an array substrate according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of an in-line shrinkage of an array substrate according to an embodiment of the present invention.
  • REFERENCE SIGNS 1-first pad; 2-second pad; Q1-display area; Q2-bonding area.
  • an array substrate is used as an example of a "substrate” in the embodiment of the present invention, and a display device is utilized as an example of “electronic device.”
  • a display device is utilized as an example of “electronic device.”
  • substrates such as array substrates and touch substrates in electronic devices such as display devices may employ the same pad configuration.
  • Embodiments of the present invention provide a display device including an array substrate (shown in FIG. 1 ) and a flip chip (shown in FIG. 2 ); wherein the array substrate has a display area Q1 for display to be located in the display area Q1 The surrounding bonding zone Q2.
  • a plurality of first pads 1 are disposed in the bonding region Q2, and the plurality of first pads 1 are arranged side by side in the first direction.
  • Each of the first pads 1 includes a first side and a second side oppositely disposed along the first direction, and a third side disposed opposite to a second direction perpendicular to the first direction And the fourth side. The first side and the second side of each of the first pads 1 are non-parallel.
  • the shape of the second pad 2 on the flip chip is matched to the shape on the first pad 1 on the array substrate. That is, the flip chip includes a plurality of second pads 2 arranged side by side along the third direction, each of the second pads 2 having a first side disposed oppositely along the third direction a side and a second side, and a third side and a fourth side disposed opposite to a fourth direction perpendicular to the third direction, a first side and a first side of each of the second pads 2 The two sides are not parallel.
  • first side, the second side, the third side, and the fourth side of each first pad 1 refer to the left side and the right side of the figure, respectively. Upper side and lower side.
  • the first side and the second side of each of the first pads 1 in this embodiment are relatively inclined and non-parallel. That is, the shape of each of the first pads 1 is a shape that gradually widens or narrows in a direction from the third side to the fourth side thereof (ie, in a direction away from the display area 01). .
  • the shape of each of the first pads 1 is gradually widened in a direction from the third side to the fourth side.
  • each of the first pads 1 is a shape that gradually widens in a direction from the third side to the fourth side thereof (that is, from the top to the bottom in the Y direction).
  • the second pad 2 has the same shape as the first pad 1.
  • the deformation of the array substrate in the Y direction occurs at this time.
  • the first pad 1 on the array substrate and the second pad 2 on the flip chip are bonded together, the first pad 1 on the deformed array substrate is opposite to the flip chip by the foregoing
  • the position of the second pad 2 is moved upward in the Y direction. It is not difficult to see that the wider position of the first pad 1 is just combined with the narrower position on the second pad 2, so that the two are still well bonded.
  • the second side of each first pad 1 and the first side of the adjacent first pad 1 are parallel to each other. Therefore, when the above-described deformation occurs between the respective first pads 1 on the array substrate, short-circuiting does not occur.
  • the second side of each of the second pads 2 and the first side of the adjacent second pads 2 are disposed to be parallel to each other, and the second pad 2 is corresponding to the first one.
  • the pads 1 are bonded together and no shorting occurs between the respective second pads 2.
  • the spacing between adjacent first pads 1 is bound to be enlarged.
  • the second pad 2 does not short-circuit between the first pad 1 adjacent thereto.
  • the pitch between adjacent first pads 1 is inevitably reduced (excluding the zero spacing between adjacent first pads 1), at this time, Since the shapes of the first pad 1 and the second pad 2 are the same, that is, the second side of the first pad 1 and the first side of the second pad 2 are parallel to each other, therefore, the second soldering The disk 2 does not short-circuit with its adjacent first pad 1.
  • the third side and the fourth side of each of the first pads 1 on the array substrate are disposed in parallel with each other.
  • the third side and the fourth side of each of the second pads 2 on the respective flip chip are disposed in parallel with each other.
  • the shape defined between the two adjacent first pads 1 is The parallelogram defines a parallelogram shape between the two adjacent second pads 2. This type of setting is more convenient to prepare.
  • the third side and the fourth side of each of the first pads 1 may also be disposed non-parallel; the third side and the fourth side of each of the second pads 2 on the flip chip may also be non-parallel Parallel settings.
  • the third side of each of the first pads 1 on the array substrate is located on a straight line, and the fourth side of each of the first pads 1 is located on another straight line.
  • the third side of each of the second pads 2 on the corresponding flip chip is located on a straight line, and the fourth side of each of the first pads 1 is located on another line.
  • the first pad 1 and the second pad 2 are arranged neatly.
  • the first pad 1 is disposed on the bonding substrate 02 on the array substrate, that is, disposed in the frame region, thereby facilitating implementation. A narrow border of the display device.
  • each of the first pads 1 may be specifically disposed according to the shape of the array substrate, and the arrangement manner of the second pads 2 may be changed correspondingly.
  • the substrate of the array substrate adopts a flexible substrate, that is, the array substrate and the flip chip of the embodiment are suitable for use in a flexible display because the flexible substrate is more susceptible to deformation.
  • the display device of the embodiment may be any product or component having a display function, such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • An embodiment of the present invention further provides an electronic device including the substrate as described above and a flip chip as described above; the substrate passing through the first pad and the second pad of the flip chip Bonded together; the shape and distribution of the plurality of first pads are the same as the shape and distribution of the plurality of second pads, respectively.
  • the first direction and the third direction are the same; the second direction is the same as the fourth direction.
  • the substrate is an array substrate or a touch substrate.

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Abstract

一种可用于柔性显示面板中的基板、覆晶薄膜及电子设备。所述基板包括多个沿着第一方向并排设置的第一焊盘（1）；每个所述第一焊盘（1）均具有沿着所述第一方向相对设置的第一侧边和第二侧边，以及沿着与所述第一方向垂直的第二方向相对设置的第三侧边和第四侧边；每个所述第一焊盘（1）的第一侧边和第二侧边非平行设置。

Description

基板、覆晶薄膜及电子设备 技术领域
本发明属于显示技术领域，具体涉及一种基板、覆晶薄膜及电子设备。
背景技术
平板显示器为目前主要流行的显示器，其因为具有外形轻薄、省电以及无辐射等特点而被广泛地应用于电脑屏幕、移动电话等电子产品上。
显示装置主要包括彩膜基板、阵列基板、覆晶薄膜(COF，Chip On Film)。阵列基板具有用于进行显示的显示区和位于显示区外围的结合区(bonding区)；显示区中引线的端头(也即焊盘)位于连接区中。覆晶薄膜一面设有引线和芯片。覆晶薄膜上的引线一端与芯片连接，另一端上同样具有焊盘，用于与阵列基板上结合区的焊盘进行结合，将芯片所提供的信号通过引线传输给阵列基板上的引线，以使显示区进行显示。
发明内容
发明人发现：当基板(阵列基板或触控基板)为柔性基板时(即，基板的基底常采用柔性材料，例如PI、PET等有机材料制成时)，在其上形成其他膜层、以及刻蚀过孔时，会导致柔性基底变形。此时将覆晶薄膜上的焊盘与基板上的焊盘进行结合(bond)时，容易造成对位不准以及错位，致使两者结合不牢固或者相邻焊盘之间发生短路的现象。
针对现有的诸如显示装置的电子设备存在的上述缺陷，提供了一种兼容膨胀和收缩变化的基板、覆晶薄膜及电子设备。
本发明实施例采用的技术方案是一种基板，包括多个沿着第一方向并排设置的第一焊盘；每个所述第一焊盘均具有沿着所述第一方向相对设置的第一侧边和第二侧边，以及沿着与所述第一方向垂直的第二方向相对设置的第三侧边和第四侧边；每个所述第一焊盘的第一侧边和第二侧边非平行设置。
可选的是，相邻的两个第一焊盘的直接相邻的第一侧边和第二侧边相互平行设置。
可选的是，每个所述第一焊盘的形状为沿所述第二方向逐渐变宽的形状。
可选的是，每个所述第一焊盘的形状为沿所述第二方向逐渐变窄的形状。
可选的是，每个所述第一焊盘的第三侧边和第四侧边相互平行设置。
可选的是，各个所述第一焊盘的第三侧边位于一直线上，各个所述第一焊盘的第四侧边位于另一直线上。
可选的是，所述基板的基底为柔性基底。
可选的是，所述基板是阵列基板。
可选的是，所述基板是触控基板。
本发明实施例提供了一种覆晶薄膜，包括多个沿着第三方向并排设置的第二焊盘，每个所述第二焊盘均具有沿着所述第三方向相对设置的第一侧边和第二侧边，以及沿着与所述第三方向垂直的第四方向相对设置的第三侧边和第四侧边，每个所述第二焊盘的第一侧边和第二侧边非平行设置。
可选的是，相邻的两个第二焊盘的直接相邻的第一侧边和第二侧边相互平行设置。
可选的是，每个所述第二焊盘的形状为沿所述第四方向逐渐变宽的形状。
可选的是，每个所述第二焊盘的形状为沿所述第四方向逐渐变窄的形状。
可选的是，每个所述第二焊盘的第三侧边和第四侧边相互平行设置。
可选的是，所述多个第二焊盘的第三侧边均位于一直线上，所述多个第二焊盘的第四侧边均位于另一直线上。
本发明实施例提供了一种电子设备，包括如上所述的基板和如上所述的覆晶薄膜；所述基板通过所述第一焊盘与所述覆晶薄膜的所述第二焊盘结合在一起；所述多个第一焊盘的形状和分布分别与所述多个第二焊盘的形状和分布相同。
可选的是，所述第一方向和所述第三方向相同；所述第二方向和所述第四方向相同。
可选的是，所述基板是阵列基板或触控基板。
本发明实施例的基板上的各个第一焊盘的第一侧边与第二侧边是相对倾斜，非平行设置的，有利地避免了结合过程中发生的短路。
在一些实施例中，每个第一焊盘的形状是沿从其第三侧边到第四侧边的方向逐渐变宽或者变窄的形状。
在本申请实施例中，假若第一焊盘的形状为沿从其第三侧边到其第四侧边的方向逐渐变宽的形状，并且第二焊盘与第一焊盘相同。基板在沿X方向上发生向外延展的变形时，基板的Y方向长度相当于变短，相对于覆晶薄膜上的第一焊盘发生了沿Y方向向上的移动；由于第一焊盘的形状为沿从其第三侧边到其第四侧边的方向逐渐变宽的形状，故第一焊盘与覆晶薄膜的第二焊盘仍然可以很好的结合在一起。同理，基板在发生沿X方向向内收缩时，基板的Y方向长度相当于被拉长，相对于覆晶薄膜上的第一焊盘发生了沿Y方向向下的移动；由于第二焊盘的形状为沿从其第三侧边到其第四侧边的方向逐渐变宽的形状，故第一焊盘与覆晶薄膜的第二焊盘仍然可以很好的结合在一起。
附图说明
图1为本发明实施例提供的阵列基板的示意图；
图2为本发明实施例提供的覆晶薄膜的示意图；
图3为本发明实施例提供的阵列基板的第一焊盘的排列示意图；
图4为本发明实施例提供的阵列基板向外延展的示意图；以及
图5为本发明实施例提供的阵列基板向内收缩的示意图。
附图标记：1-第一焊盘；2-第二焊盘；Q1-显示区；Q2-结合区。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
除非另外定义，本发明实施例使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明实施例中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数 量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“上”、“下”、“左”、“右”、“行”、“列”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了清楚地描述，本发明实施例中利用阵列基板作为“基板”的示例，并利用显示装置作为“电子设备”的示例。本领域技术人员能够理解，诸如显示装置的电子设备中的基板(例如阵列基板和触控基板)都可以采用相同的焊盘构造。
本发明实施例提供一种显示装置，包括阵列基板(如图1所示)和覆晶薄膜(如图2所示)；其中，阵列基板具有用于显示的显示区Q1，以位于显示区Q1周边的结合区Q2。在结合区Q2设置有多个第一焊盘1，多个第一焊盘1沿第一方向并排设置。每个第一焊盘1均包括沿着所述第一方向相对设置的第一侧边和第二侧边，以及沿着与所述第一方向垂直的第二方向相对设置的第三侧边和第四侧边。每个所述第一焊盘1的第一侧边和第二侧边非平行设置。可以理解的是，覆晶薄膜上的第二焊盘2的形状是与阵列基板上的第一焊盘1上的形状相匹配的。也就是说，所述覆晶薄膜包括多个沿着第三方向并排设置的第二焊盘2，每个所述第二焊盘2均具有沿着所述第三方向相对设置的第一侧边和第二侧边，以及沿着与所述第三方向垂直的第四方向相对设置的第三侧边和第四侧边，每个所述第二焊盘2的第一侧边和第二侧边非平行设置。
在此需要说明的是，每个第一焊盘1的第一侧边、第二侧边、第三侧边、第四侧边分别是指图中所示的左侧边、右侧边、上侧边、下侧边。
本实施例中的各个第一焊盘1的第一侧边与第二侧边是相对倾斜，非平行设置的。也就是说，每个第一焊盘1的形状是沿从其第三侧边到第四侧边的方向(即，沿着远离所述显示区01的方向)逐渐变宽或者变窄的形状。以下，以每个第一焊盘1的形状是沿从其第三侧边到第四侧边的方向逐渐变宽为例进行说明。
具体的，如图4所示，各个第一焊盘1的形状是沿从其第三侧边到第四侧边的方向(也即图中沿Y方向从上到下)逐渐变宽的形状， 第二焊盘2与第一焊盘1形状相同。当阵列基板在制备过程中发生沿X方向向外延展的变形时，此时阵列基板的沿Y方向上发生内向收缩的变形。此时，在将阵列基板上的第一焊盘1与覆晶薄膜上的第二焊盘2结合在一起时，由于前述的变形阵列基板上的第一焊盘1相对于覆晶薄膜的第二焊盘2的位置发生了沿Y方向向上移动。不难看出的是，第一焊盘1较宽的位置恰好与第二焊盘2上较窄的位置结合在一起，因此二者仍然会很好的结合在一起。
同理，如图5所示，当阵列基板在制备过程中发生沿X方向向内收缩的变形时，此时阵列基板的沿Y方向上发生向外延展的变形。此时，在将阵列基板上的第一焊盘1与覆晶薄膜上的第二焊盘2结合在一起时，由于前述的变形阵列基板上的第一焊盘1相对于覆晶薄膜的第二焊盘2的位置发生了沿Y方向向下移动。不难看出的是，第一焊盘1较窄的位置恰好与第二焊盘2上较宽的位置结合在一起，因此二者仍然会很好的结合在一起。
如图3所示，在本实施例显示装置中，可选的，各个第一焊盘1的第二侧边与其相邻的第一焊盘1的第一侧边是相互平行的。因此，各个第一焊盘1之间在阵列基板发生上述形变时，不会发生短接。同样的可选的将各个第二焊盘2的第二侧边与其相邻的第二焊盘2的第一侧边设置为相互平行的，此时将第二焊盘2与其对应的第一焊盘1结合在一起，各个第二焊盘2之间也不会发生短接。而且，当阵列基板沿X方向发生了向外延展的变形，势必会导致相邻第一焊盘1之间的间距会被拉大。此时，由于第一焊盘1与第二焊盘2的形状是相同的，即第一焊盘1的第二侧边与第二焊盘2的第一侧边是相互平行的，因此，第二焊盘2不会与其相邻的第一焊盘1之间发生短接。当阵列基板沿X方向发生向内收缩的变形，势必会导致相邻第一焊盘1之间的间距变小(排除相邻第一焊盘1之间的零间距的情况)，此时，由于第一焊盘1与第二焊盘2的形状是相同的，即第一焊盘1的第二侧边与第二焊盘2的第一侧边是相互平行的，因此，第二焊盘2不会与其相邻的第一焊盘1之间发生短接。
其中，阵列基板上的每个第一焊盘1的第三侧边和第四侧边相互平行设置。相应的覆晶薄膜上的每个第二焊盘2的第三侧边和第四侧边相互平行设置。此时，在两相邻的第一焊盘1之间限定出的形状为 平行四边形，在两相邻的第二焊盘2之间限定出的形状为平行四边形。该种设置方式更方便制备。当然，每个第一焊盘1的第三侧边和第四侧边也可以非平行设置；覆晶薄膜上的每个第二焊盘2的第三侧边和第四侧边也可以非平行设置。
其中，阵列基板上各个所述第一焊盘1的第三侧边位于一直线上，各个所述第一焊盘1的第四侧边位于另一直线上。相应的覆晶薄膜上各个所述第二焊盘2的第三侧边位于一直线上，各个所述第一焊盘1的第四侧边位于另一直线上。该种设置方式，第一焊盘1和第二焊盘2均排列整齐，特别是，第一焊盘1设置在阵列基板上的结合区02，也就是设置在边框区，因此有助于实现显示装置的窄边框。当然，也可以根据阵列基板的形状具体设置各个第一焊盘1，同时可以相应的改变第二焊盘2的排布方式。
其中，阵列基板的基底采用柔性基底，也就说本实施例的阵列基板和覆晶薄膜适用于柔性显示中，因为柔性基底更容易发生变形。
其中，本实施例的显示装置可以为液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本发明实施例还提供了一种电子设备，包括如上所述的基板和如上所述的覆晶薄膜；所述基板通过所述第一焊盘与所述覆晶薄膜的所述第二焊盘结合在一起；所述多个第一焊盘的形状和分布分别与所述多个第二焊盘的形状和分布相同。
可选的是，所述第一方向和所述第三方向相同；所述第二方向和所述第四方向相同。
可选的是，所述基板是阵列基板或触控基板。
上述构造的优点已经在先前的实施例中详细地介绍过，因此此处不再重复。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (18)

  1. 一种基板，包括多个沿着第一方向并排设置的第一焊盘；每个所述第一焊盘均具有沿着所述第一方向相对设置的第一侧边和第二侧边，以及沿着与所述第一方向垂直的第二方向相对设置的第三侧边和第四侧边；每个所述第一焊盘的第一侧边和第二侧边非平行设置。
  2. 根据权利要求1所述的基板，其中，相邻的两个第一焊盘的直接相邻的第一侧边和第二侧边相互平行设置。
  3. 根据权利要求1或2所述的基板，其中，每个所述第一焊盘的形状为沿所述第二方向逐渐变宽的形状。
  4. 根据权利要求1或2所述的基板，其中，每个所述第一焊盘的形状为沿所述第二方向逐渐变窄的形状。
  5. 根据权利要求1所述的基板，其中，每个所述第一焊盘的第三侧边和第四侧边相互平行设置。
  6. 根据权利要求1所述的基板，其中，各个所述第一焊盘的第三侧边位于一直线上，各个所述第一焊盘的第四侧边位于另一直线上。
  7. 根据权利要求1所述的基板，其中，所述基板的基底为柔性基底。
  8. 根据权利要求1所述的基板，其中，所述基板是阵列基板。
  9. 根据权利要求1所述的基板，其中，所述基板是触控基板。
  10. 一种覆晶薄膜，包括多个沿着第三方向并排设置的第二焊盘，每个所述第二焊盘均具有沿着所述第三方向相对设置的第一侧边和第二侧边，以及沿着与所述第三方向垂直的第四方向相对设置的第三侧边和第四侧边，每个所述第二焊盘的第一侧边和第二侧边非平行设置。
  11. 根据权利要求10所述的覆晶薄膜，其中，相邻的两个第二焊盘的直接相邻的第一侧边和第二侧边相互平行设置。
  12. 根据权利要求10或11所述的基板，其中，每个所述第二焊盘的形状为沿所述第四方向逐渐变宽的形状。
  13. 根据权利要求10或11所述的基板，其中，每个所述第二焊盘的形状为沿所述第四方向逐渐变窄的形状。
  14. 根据权利要求10所述的覆晶薄膜，其中，每个所述第二焊盘的第三侧边和第四侧边相互平行设置。
  15. 根据权利要求10所述的覆晶薄膜，其中，所述多个第二焊盘的第三侧边均位于一直线上，所述多个第二焊盘的第四侧边均位于另一直线上。
  16. 一种电子设备，包括如权利要求1-9之一所述的基板和如权利要求10-15之一所述的覆晶薄膜；所述基板通过所述第一焊盘与所述覆晶薄膜的所述第二焊盘结合在一起；所述多个第一焊盘的形状和分布分别与所述多个第二焊盘的形状和分布相同。
  17. 如权利要求16所述的电子设备，其中，所述第一方向和所述第三方向相同；所述第二方向和所述第四方向相同。
  18. 如权利要求16所述的电子设备，其中，所述基板是阵列基板或触控基板。
PCT/CN2016/082420 2016-02-17 2016-05-18 基板、覆晶薄膜及电子设备 WO2017140055A1 (zh)

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