CN105529339A - 阵列基板、覆晶薄膜及显示装置 - Google Patents

阵列基板、覆晶薄膜及显示装置 Download PDF

Info

Publication number
CN105529339A
CN105529339A CN201610090050.2A CN201610090050A CN105529339A CN 105529339 A CN105529339 A CN 105529339A CN 201610090050 A CN201610090050 A CN 201610090050A CN 105529339 A CN105529339 A CN 105529339A
Authority
CN
China
Prior art keywords
pad
array base
base palte
brilliant film
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201610090050.2A
Other languages
English (en)
Other versions
CN105529339B (zh
Inventor
李红
陈立强
周伟峰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201610090050.2A priority Critical patent/CN105529339B/zh
Publication of CN105529339A publication Critical patent/CN105529339A/zh
Priority to PCT/CN2016/082420 priority patent/WO2017140055A1/zh
Priority to US15/504,628 priority patent/US10622386B2/en
Application granted granted Critical
Publication of CN105529339B publication Critical patent/CN105529339B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04102—Flexible digitiser, i.e. constructional details for allowing the whole digitising part of a device to be flexed or rolled like a sheet of paper
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/0905—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/091—Disposition
    • H01L2224/0912—Layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch, thickness; Using different connections on the pads

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Geometry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Wire Bonding (AREA)

Abstract

本发明提供一种阵列基板、覆晶薄膜及显示装置，属于显示技术领域。本发明的显示装置，包括阵列基板和覆晶薄膜，所述阵列基板包括多个并排设置的第一焊盘，所述覆晶薄膜包括多个并排设置的第二焊盘，所述阵列基板通过所述第一焊盘与所述覆晶薄膜的所述第二焊盘绑定在一起，每个所述第一焊盘均具有在行方向上相对设置的第一侧边和第二侧边，以及在列方向上相对设置的第三侧边和第四侧边，每个所述第一焊盘的第一侧边和第二侧边非平行设置，每个所述第二焊盘与其进行绑定的第一焊盘具有相同的结构。本发明可用于柔性显示面板中。

Description

阵列基板、覆晶薄膜及显示装置
技术领域
本发明属于显示技术领域，具体涉及一种阵列基板、覆晶薄膜及显示装置。
背景技术
平板显示器为目前主要流行的显示器，其因为具有外形轻薄、省电以及无辐射等特点而被广泛地应用于电脑屏幕、移动电话等电子产品上。
显示装置主要包括彩膜基板、阵列基板、覆晶薄膜(COF，ChipOnFilm)；其中，阵列基板具有用于进行显示的显示区和位于显示区外围的绑定区(Bonding区)，显示区中引线的端头(也即焊盘)位于连接区中；覆晶薄膜一面设有引线和芯片，覆晶薄膜上的引线一端与芯片连接，另一端上同样具有焊盘，用于与阵列基板上绑定区的焊盘进行绑定，将芯片所提供的信号通过引线传输给阵列基板上的引线，以使显示区进行显示。
发明人发现现有技术中至少存在如下问题：当阵列基板为柔性阵列基板时，即阵列基板的基底常采用柔性材料，例如PI、PET等有机材料制成时，在其上形成其他膜层，以及刻蚀过孔时，会导致柔性基底变形，此时将覆晶薄膜上的焊盘与阵列基板上的焊盘进行绑定时，容易造成对位不准以及错位，致使两者绑定不牢固或者相邻焊盘之间发生短路的现象。
发明内容
本发明所要解决的技术问题包括，针对现有的显示装置存在的上述问题，提供一种兼容阵列基板膨胀和收缩变化的阵列基板、覆晶薄膜及显示装置。
解决本发明技术问题所采用的技术方案是一种阵列基板，包括多个并排设置的第一焊盘，每个所述第一焊盘均具有在行方向上相对设置的第一侧边和第二侧边，以及在列方向上相对设置的第三侧边和第四侧边，每个所述第一焊盘的第一侧边和第二侧边非平行设置。
优选的是，每个所述第一焊盘的第二侧边与其相邻的所述第一焊盘的第一侧边相互平行设置。
优选的是，每个所述第一焊盘的第三侧边和第四侧边相互平行设置。
优选的是，各个所述第一焊盘的第三侧边位于同一水平线上，各个所述第一焊盘的第四侧边位于同一水平线上。
优选的是，所述阵列基板的基底为柔性基底。
解决本发明技术问题所采用的技术方案是一种覆晶薄膜，包括多个并排设置的第二焊盘，每个所述第二焊盘均具有在行方向上相对设置的第一侧边和第二侧边，以及在列方向上相对设置的第三侧边和第四侧边，每个所述第二焊盘的第一侧边和第二侧边非平行设置。
优选的是，每个所述第二焊盘的第二侧边与其相邻的所述第二焊盘的第一侧边相互平行设置。
优选的是，每个所述第二焊盘的第三侧边和第四侧边相互平行设置。
优选的是，各个所述第二焊盘的第三侧边位于同一水平线上，各个所述第二焊盘的第四侧边位于同一水平线上。
解决本发明技术问题所采用的技术方案是一种显示装置，包括阵列基板和覆晶薄膜，所述阵列基板包括多个并排设置的第一焊盘，所述覆晶薄膜包括多个并排设置的第二焊盘，所述阵列基板通过所述第一焊盘与所述覆晶薄膜的所述第二焊盘绑定在一起，每个所述第一焊盘均具有在行方向上相对设置的第一侧边和第二侧边，以及在列方向上相对设置的第三侧边和第四侧边，每个所述第一焊盘的第一侧边和第二侧边非平行设置，每个所述第二焊盘与其进行绑定的第一焊盘具有相同的结构。
本发明具有如下有益效果：
由于本发明的阵列基板上的各个第一焊盘的第一侧边与第二侧边是相对倾斜，非平行设置的，也就是每个第一焊盘的形状是沿其第三侧边到第四侧边所在方向上逐渐变宽或者变窄的形状，因此，假若第一焊盘的形状为从其第三侧边到其第四侧边方向上逐渐变宽的形状，第二焊盘与第一焊盘相同，阵列基板在沿X方向上发生向外延展的变形，此时阵列基板的Y方向长度相当于变短，相对于覆晶薄膜上的第一焊盘发生了沿Y方向向上的移动，而第一焊盘的形状为从其第三侧边到其第四侧边方向上逐渐变宽的形状，故第一焊盘与覆晶薄膜的第二焊盘仍然可以很好的绑定在一起。同理，阵列基板在发生沿X方向向内收缩，此时阵列基板的Y方向长度相当于被拉长，相对于覆晶薄膜上的第一焊盘发生了沿Y方向向下的移动，而第二焊盘的形状为从其第三侧边到其第四侧边方向上逐渐变宽的形状，故第一焊盘与覆晶薄膜的第二焊盘仍然可以很好的绑定在一起。
附图说明
图1为本发明的实施例1的阵列基板的示意图；
图2为本发明的实施例1的覆晶薄膜的示意图；
图3为本发明的实施例1的阵列基板的第一焊盘的排列示意图；
图4为本发明的实施例1的阵列基板向外延展的示意图；
图5为本发明的实施例1的阵列基板向内收缩的示意图。
其中附图标记为：1、第一焊盘；2、第二焊盘；Q1、显示区；Q2、绑定区。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
除非另外定义，本发明使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“上”、“下”、“左”、“右”、“行”、“列”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
实施例1：
结合图1和2所示，本实施例提供一种显示装置，包括阵列基板和覆晶薄膜；其中，阵列基板具有用于显示的显示区Q1，以位于显示区Q1周边的绑定区Q2，在绑定区Q2设置有多个第一焊盘1，多个第一焊盘1并排设置。每个第一焊盘1均包括在行方向上相对设置的第一侧边和第二侧边，以及在列方向上相对设置的第三侧边和第四侧边，其中，第一侧边和第二侧边非平行设置。可以理解的是，覆晶薄膜上的第二焊盘2的形状是与阵列基板上的第一焊盘1上的形状相匹配的。也就是说，每个第二焊盘2同样包括在行方向上相对设置的第一侧边和第二侧边，以及在列方向上相对设置的第三侧边和第四侧边，且第一侧边和第二侧边非平行设置。
在此需要说明的是，每个第一焊盘1的第一侧边、第二侧边、第三侧边、第四侧边分别是指图中所示的左侧边、右侧边、上侧边、下侧边。
本实施例中的各个第一焊盘1的第一侧边与第二侧边是相对倾斜，非平行设置的，也就是每个第一焊盘1的形状是沿其第三侧边到第四侧边所在方向上逐渐变宽或者变窄的形状。以下，以每个第一焊盘1的形状是沿其第三侧边到第四侧边所在方向上逐渐变宽为例进行说明。
具体的，如图4所示，各个第一焊盘1的形状是沿其第三侧边到第四侧边方向上(也即图中沿Y方向从上到下)逐渐变宽的形状，第二焊盘2与第一焊盘1形状相同。当阵列基板在制备过程中发生沿X方向(行方向)向外延展的变形时，此时阵列基板的沿Y方向上发生内向收缩的变形，此时，在将阵列基板上的第一焊盘1与覆晶薄膜上的第二焊盘2绑定在一起时，由于前述的变形阵列基板上的第一焊盘1相对于覆晶薄膜的第二焊盘2的位置发生了沿Y方向(列方向)向上移动，不难看出的是，第一焊盘1较宽的位置恰好与第二焊盘2上较窄的位置绑定在一起，因此二者仍然会很好的绑定在一起。
同理，如图5所示，当阵列基板在制备过程中发生沿X方向(行方向)向内收缩的变形时，此时阵列基板的沿Y方向上发生向外延展的变形，此时，在将阵列基板上的第一焊盘1与覆晶薄膜上的第二焊盘2绑定在一起时，由于前述的变形阵列基板上的第一焊盘1相对于覆晶薄膜的第二焊盘2的位置发生了沿Y方向(列方向)向下移动，不难看出的是，第一焊盘1较窄的位置恰好与第二焊盘2上较宽的位置绑定在一起，因此二者仍然会很好的绑定在一起。
如图3所示，在本实施例显示装置中，优选的，各个第一焊盘1的第二侧边与其相邻的第一焊盘1的第一侧边是相互平行的，故各个第一焊盘1之间在阵列基板发生上述形变时，不会发生短接。同样的优选的将各个第二焊盘2的第二侧边与其相邻的第二焊盘2的第一侧边设置为相互平行的，此时将第二焊盘2与其对应的第一焊盘1绑定在一起，各个第二焊盘2之间也不会发生短接。而且，当阵列基板沿X方向发生了向外延展的变形，势必会导致相邻第一焊盘1之间的间距会被拉大，此时，由于第一焊盘1与第二焊盘2的形状是相同的，即第一焊盘1的第二侧边与第二焊盘2的第一侧边是相互平行的，因此，第二焊盘2不会与其相邻的第一焊盘1之间发生短接。当阵列基板沿X方向发生向内收缩的变形，势必会导致相邻第一焊盘1之间的间距变小(排除相邻第一焊盘1之间的零间距的情况)，此时，由于第一焊盘1与第二焊盘2的形状是相同的，即第一焊盘1的第二侧边与第二焊盘2的第一侧边是相互平行的，因此，第二焊盘2不会与其相邻的第一焊盘1之间发生短接。
其中，阵列基板上的每个第一焊盘1的第三侧边和第四侧边相互平行设置。相应的覆晶薄膜上的每个第二焊盘2的第三侧边和第四侧边相互平行设置。此时，在两相邻的第一焊盘1之间限定出的形状为平行四边形，在两相邻的第二焊盘2之间限定出的形状为平行四边形。该种设置方式更方便制备。当然，每个第一焊盘1的第三侧边和第四侧边也可以不平行设置；覆晶薄膜上的每个第二焊盘2的第三侧边和第四侧边也可以不平行设置。
其中，阵列基板上各个所述第一焊盘1的第三侧边位于同一水平线上，各个所述第一焊盘1的第四侧边位于同一水平线上。相应的覆晶薄膜上各个所述第二焊盘2的第三侧边位于同一水平线上，各个所述第一焊盘1的第四侧边位于同一水平线上。该种设置方式，第一焊盘1和第二焊盘2均排列整齐，特别是，第一焊盘1设置在阵列基板上的绑定区Q2，也就是设置在边框区，因此有助于实现显示装置的窄边框。当然，也可以根据阵列基板的形状具体设置各个第一焊盘1，同时可以相应的改变第二焊盘2的排布方式。
其中，阵列基板的基底采用柔性基底，也就说本实施例的阵列基板和覆晶薄膜特别适用于柔性显示中。因为，柔性基底更容易发生变形。
其中，本实施例的显示装置可以为液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (10)

1.一种阵列基板，包括多个并排设置的第一焊盘，每个所述第一焊盘均具有在行方向上相对设置的第一侧边和第二侧边，以及在列方向上相对设置的第三侧边和第四侧边，其特征在于，每个所述第一焊盘的第一侧边和第二侧边非平行设置。
2.根据权利要求1所述的阵列基板，其特征在于，每个所述第一焊盘的第二侧边与其相邻的所述第一焊盘的第一侧边相互平行设置。
3.根据权利要求1所述的阵列基板，其特征在于，每个所述第一焊盘的第三侧边和第四侧边相互平行设置。
4.根据权利要求1所述的阵列基板，其特征在于，各个所述第一焊盘的第三侧边位于同一水平线上，各个所述第一焊盘的第四侧边位于同一水平线上。
5.根据权利要求1所述的阵列基板，其特征在于，所述阵列基板的基底为柔性基底。
6.一种覆晶薄膜，包括多个并排设置的第二焊盘，每个所述第二焊盘均具有在行方向上相对设置的第一侧边和第二侧边，以及在列方向上相对设置的第三侧边和第四侧边，其特征在于，每个所述第二焊盘的第一侧边和第二侧边非平行设置。
7.根据权利要求6所述的覆晶薄膜，其特征在于，每个所述第二焊盘的第二侧边与其相邻的所述第二焊盘的第一侧边相互平行设置。
8.根据权利要求6所述的覆晶薄膜，其特征在于，每个所述第二焊盘的第三侧边和第四侧边相互平行设置。
9.根据权利要求6所述的覆晶薄膜，其特征在于，各个所述第二焊盘的第三侧边位于同一水平线上，各个所述第二焊盘的第四侧边位于同一水平线上。
10.一种显示装置，包括阵列基板和覆晶薄膜，所述阵列基板包括多个并排设置的第一焊盘，所述覆晶薄膜包括多个并排设置的第二焊盘，所述阵列基板通过所述第一焊盘与所述覆晶薄膜的所述第二焊盘绑定在一起，其特征在于，每个所述第一焊盘均具有在行方向上相对设置的第一侧边和第二侧边，以及在列方向上相对设置的第三侧边和第四侧边，每个所述第一焊盘的第一侧边和第二侧边非平行设置，每个所述第二焊盘与其进行绑定的第一焊盘具有相同的结构。
CN201610090050.2A 2016-02-17 2016-02-17 阵列基板、覆晶薄膜及显示装置 Active CN105529339B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201610090050.2A CN105529339B (zh) 2016-02-17 2016-02-17 阵列基板、覆晶薄膜及显示装置
PCT/CN2016/082420 WO2017140055A1 (zh) 2016-02-17 2016-05-18 基板、覆晶薄膜及电子设备
US15/504,628 US10622386B2 (en) 2016-02-17 2016-05-18 Substrate, chip on film and electronic equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610090050.2A CN105529339B (zh) 2016-02-17 2016-02-17 阵列基板、覆晶薄膜及显示装置

Publications (2)

Publication Number Publication Date
CN105529339A true CN105529339A (zh) 2016-04-27
CN105529339B CN105529339B (zh) 2018-12-28

Family

ID=55771459

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610090050.2A Active CN105529339B (zh) 2016-02-17 2016-02-17 阵列基板、覆晶薄膜及显示装置

Country Status (3)

Country Link
US (1) US10622386B2 (zh)
CN (1) CN105529339B (zh)
WO (1) WO2017140055A1 (zh)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106449713A (zh) * 2016-11-08 2017-02-22 武汉华星光电技术有限公司 一种oled显示屏幕及显示装置
CN106782243A (zh) * 2016-12-30 2017-05-31 上海天马微电子有限公司 一种显示基板、显示面板及显示装置
WO2017140055A1 (zh) * 2016-02-17 2017-08-24 京东方科技集团股份有限公司 基板、覆晶薄膜及电子设备
CN107300792A (zh) * 2017-07-24 2017-10-27 武汉华星光电技术有限公司 表面贴装方法
CN107591424A (zh) * 2016-07-08 2018-01-16 三星显示有限公司 显示装置
CN107809843A (zh) * 2017-11-30 2018-03-16 武汉天马微电子有限公司 一种绑定部件、显示基板及显示面板
CN108470727A (zh) * 2018-03-03 2018-08-31 昆山国显光电有限公司 电子组件及显示装置
CN108663865A (zh) * 2018-07-24 2018-10-16 武汉华星光电技术有限公司 Tft阵列基板及其制造方法与柔性液晶显示面板
CN109087589A (zh) * 2018-10-22 2018-12-25 惠科股份有限公司 阵列基板、显示面板及显示装置
WO2019114089A1 (zh) * 2017-12-14 2019-06-20 武汉华星光电半导体显示技术有限公司 柔性显示器及其驱动元件
CN109935169A (zh) * 2019-04-26 2019-06-25 武汉天马微电子有限公司 一种显示面板及显示装置
CN111681538A (zh) * 2020-06-24 2020-09-18 武汉华星光电技术有限公司 显示面板及显示装置
CN112133241A (zh) * 2020-10-29 2020-12-25 上海天马有机发光显示技术有限公司 覆晶薄膜、显示面板及显示装置
CN113421494A (zh) * 2021-06-22 2021-09-21 合肥维信诺科技有限公司 覆晶薄膜、显示面板及显示装置
CN113421491A (zh) * 2021-06-17 2021-09-21 合肥维信诺科技有限公司 覆晶薄膜、显示面板和显示装置
CN114973995A (zh) * 2022-05-27 2022-08-30 福州京东方光电科技有限公司 显示面板、显示装置及其绑定方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170338204A1 (en) * 2016-05-17 2017-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Device and Method for UBM/RDL Routing
KR102519126B1 (ko) * 2018-03-30 2023-04-06 삼성디스플레이 주식회사 표시 장치
US11800642B2 (en) * 2020-12-01 2023-10-24 Tpk Advanced Solutions Inc. Bonding pad structure for electronic device and manufacturing method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5951304A (en) * 1997-05-21 1999-09-14 General Electric Company Fanout interconnection pad arrays
CN101510383A (zh) * 2009-03-26 2009-08-19 友达光电股份有限公司 平面显示面板
US20140198462A1 (en) * 2009-11-13 2014-07-17 Innolux Corporation Display panel integrating a driving circuit
CN105301851A (zh) * 2014-06-17 2016-02-03 三星显示有限公司 阵列基底和使用该阵列基底安装集成电路的方法
CN205376526U (zh) * 2016-02-17 2016-07-06 京东方科技集团股份有限公司 阵列基板、覆晶薄膜及显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3437477B2 (ja) * 1999-02-10 2003-08-18 シャープ株式会社 配線基板および半導体装置
JP2001284784A (ja) * 2000-03-30 2001-10-12 Toshiba Corp 配線基板
JP4701069B2 (ja) * 2005-10-21 2011-06-15 キヤノン株式会社 表示一体型位置検出装置
JP4254883B2 (ja) * 2006-05-29 2009-04-15 エプソンイメージングデバイス株式会社 配線基板、実装構造体及びその製造方法
KR102047068B1 (ko) * 2013-04-29 2019-11-21 삼성디스플레이 주식회사 표시패널, 전자기기 및 전자기기의 본딩 방법
CN105529339B (zh) 2016-02-17 2018-12-28 京东方科技集团股份有限公司 阵列基板、覆晶薄膜及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5951304A (en) * 1997-05-21 1999-09-14 General Electric Company Fanout interconnection pad arrays
CN101510383A (zh) * 2009-03-26 2009-08-19 友达光电股份有限公司 平面显示面板
US20140198462A1 (en) * 2009-11-13 2014-07-17 Innolux Corporation Display panel integrating a driving circuit
CN105301851A (zh) * 2014-06-17 2016-02-03 三星显示有限公司 阵列基底和使用该阵列基底安装集成电路的方法
CN205376526U (zh) * 2016-02-17 2016-07-06 京东方科技集团股份有限公司 阵列基板、覆晶薄膜及显示装置

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10622386B2 (en) 2016-02-17 2020-04-14 Boe Technology Group Co., Ltd. Substrate, chip on film and electronic equipment
WO2017140055A1 (zh) * 2016-02-17 2017-08-24 京东方科技集团股份有限公司 基板、覆晶薄膜及电子设备
CN107591424A (zh) * 2016-07-08 2018-01-16 三星显示有限公司 显示装置
CN107591424B (zh) * 2016-07-08 2023-06-20 三星显示有限公司 显示装置
CN106449713A (zh) * 2016-11-08 2017-02-22 武汉华星光电技术有限公司 一种oled显示屏幕及显示装置
CN106782243A (zh) * 2016-12-30 2017-05-31 上海天马微电子有限公司 一种显示基板、显示面板及显示装置
CN107300792A (zh) * 2017-07-24 2017-10-27 武汉华星光电技术有限公司 表面贴装方法
CN107809843A (zh) * 2017-11-30 2018-03-16 武汉天马微电子有限公司 一种绑定部件、显示基板及显示面板
CN107809843B (zh) * 2017-11-30 2019-12-20 武汉天马微电子有限公司 一种绑定部件、显示基板及显示面板
WO2019114089A1 (zh) * 2017-12-14 2019-06-20 武汉华星光电半导体显示技术有限公司 柔性显示器及其驱动元件
CN108470727A (zh) * 2018-03-03 2018-08-31 昆山国显光电有限公司 电子组件及显示装置
CN108663865A (zh) * 2018-07-24 2018-10-16 武汉华星光电技术有限公司 Tft阵列基板及其制造方法与柔性液晶显示面板
CN109087589B (zh) * 2018-10-22 2021-06-18 惠科股份有限公司 阵列基板、显示面板及显示装置
US11355523B2 (en) 2018-10-22 2022-06-07 HKC Corporation Limited Array substrate, display panel, and display device
CN109087589A (zh) * 2018-10-22 2018-12-25 惠科股份有限公司 阵列基板、显示面板及显示装置
CN109935169A (zh) * 2019-04-26 2019-06-25 武汉天马微电子有限公司 一种显示面板及显示装置
CN109935169B (zh) * 2019-04-26 2021-07-06 武汉天马微电子有限公司 一种显示面板及显示装置
CN111681538A (zh) * 2020-06-24 2020-09-18 武汉华星光电技术有限公司 显示面板及显示装置
CN112133241A (zh) * 2020-10-29 2020-12-25 上海天马有机发光显示技术有限公司 覆晶薄膜、显示面板及显示装置
CN113421491A (zh) * 2021-06-17 2021-09-21 合肥维信诺科技有限公司 覆晶薄膜、显示面板和显示装置
CN113421494A (zh) * 2021-06-22 2021-09-21 合肥维信诺科技有限公司 覆晶薄膜、显示面板及显示装置
CN114973995A (zh) * 2022-05-27 2022-08-30 福州京东方光电科技有限公司 显示面板、显示装置及其绑定方法
CN114973995B (zh) * 2022-05-27 2024-03-26 福州京东方光电科技有限公司 显示面板、显示装置及其绑定方法

Also Published As

Publication number Publication date
WO2017140055A1 (zh) 2017-08-24
US10622386B2 (en) 2020-04-14
CN105529339B (zh) 2018-12-28
US20180108682A1 (en) 2018-04-19

Similar Documents

Publication Publication Date Title
CN105529339A (zh) 阵列基板、覆晶薄膜及显示装置
EP3244385B1 (en) Display substrate, display panel, and display device
CN109212852B (zh) 显示面板及显示装置
CN205376526U (zh) 阵列基板、覆晶薄膜及显示装置
US20170147123A1 (en) Touch display panel, manufacturing method for the same, driving method for the same, and display device
CN105529338A (zh) 阵列基板、覆晶薄膜、显示面板及显示装置
CN103217845B (zh) 下基板及其制造方法、液晶显示面板和液晶显示器
EP3196941A1 (en) Array substrate and display device thereof
CN105182646B (zh) 阵列基板、显示装置
WO2018006231A1 (en) Touch substrate, touch display panel and touch display apparatus having the same, and fabricating method thereof
CN106530972B (zh) 柔性阵列基板的制作方法
CN103744557A (zh) 触控显示装置
CN104808885A (zh) 阵列基板及触控显示装置
CN104716148A (zh) 柔性基板及其制造方法、柔性显示面板、柔性显示装置
CN106952583A (zh) 柔性阵列基板的制作方法
US20170329455A1 (en) Touch panel and touch display screen
CN104035248A (zh) 一种阵列基板及液晶显示装置
CN104714327A (zh) 一种触控液晶显示面板及触控液晶显示装置
CN104216159B (zh) 一种显示面板及其制备方法、显示装置
CN105117069A (zh) 一种阵列基板、触控显示面板及触控显示装置
CN104597668A (zh) 液晶显示面板及液晶显示装置
CN105093729A (zh) 阵列基板及其制作方法、显示装置
CN111552401B (zh) 触控显示装置
CN101726874B (zh) 显示面板与软性电路板的接合结构
US10256257B2 (en) Display panel, pixel array substrate and line array structure

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant