CN109087589A - 阵列基板、显示面板及显示装置 - Google Patents
阵列基板、显示面板及显示装置 Download PDFInfo
- Publication number
- CN109087589A CN109087589A CN201811230980.9A CN201811230980A CN109087589A CN 109087589 A CN109087589 A CN 109087589A CN 201811230980 A CN201811230980 A CN 201811230980A CN 109087589 A CN109087589 A CN 109087589A
- Authority
- CN
- China
- Prior art keywords
- golden finger
- bonding area
- array substrate
- liner
- spacing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 82
- 238000005452 bending Methods 0.000 claims abstract description 34
- 239000012528 membrane Substances 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims 1
- 230000002159 abnormal effect Effects 0.000 abstract description 11
- 239000010408 film Substances 0.000 description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13458—Terminal pads
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0616—Random array, i.e. array with no symmetry
- H01L2224/06164—Random array, i.e. array with no symmetry covering only portions of the surface to be connected
- H01L2224/06165—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Nonlinear Science (AREA)
- Theoretical Computer Science (AREA)
- Optics & Photonics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Mathematical Physics (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
本发明涉及一种阵列基板,包括显示区以及围绕所述显示区设置的邦定区;所述阵列基板的邦定区设有至少一个衬垫,所述衬垫包括若干个间隔平行排列的第一金手指;同一所述衬垫中,相邻所述第一金手指的间距不完全相等。上述阵列基板,同一衬垫中,相邻第一金手指的间距不完全相同,以使得邦定区弯折后,第一金手指与覆晶薄膜上的第二金手指匹配,以保证第一金手指和第二金手指的接触面积,从而保证覆晶薄膜与阵列基板信号接触良好,即有效避免显示面板显示异常。本发明还涉及一种显示面板和一种显示装置。
Description
技术领域
本发明涉及显示领域,特别是涉及一种阵列基板、一种显示面板及一种显示装置。
背景技术
传统的,显示面板包括阵列基板,阵列基板包括显示区和围绕显示区设置的邦定区,驱动电路芯片(driver integrated circuit)通过与阵列基板的邦定区邦定。因覆晶薄膜(chip on film,COF)的成本较低,故通常使用覆晶薄膜实现驱动电路芯片与阵列基板的邦定。
随着技术的发展,包含曲面显示面板的显示装置越来越受到使用者的青睐。然而,阵列基板的邦定区在弯折后,显示面板容易出现显示不稳定的现象。
发明内容
基于此,有必要提供一种有效避免显示面板显示异常的阵列基板。
一种阵列基板,包括:
显示区;
以及邦定区,围绕所述显示区设置;所述阵列基板的邦定区设有至少一个衬垫,所述衬垫包括若干个间隔平行排列的第一金手指;同一所述衬垫中,相邻所述第一金手指的间距不完全相等。
上述阵列基板,同一衬垫中,相邻第一金手指的间距不完全相同,以使得邦定区弯折后,第一金手指与覆晶薄膜上的第二金手指匹配,以保证第一金手指和第二金手指的接触面积,从而保证覆晶薄膜与阵列基板信号接触良好,即有效避免显示面板显示异常。
在其中一个实施例中,所述邦定区弯折后,所述衬垫位于所述邦定区的凹面侧;同一所述衬垫中,所述邦定区弯折后的曲率越大,相邻所述第一金手指的间距越大;同一所述衬垫中,所述邦定区弯折后的曲率越小,相邻所述第一金手指的间距越小。
在其中一个实施例中,所述邦定区弯折后,所述衬垫位于所述邦定区的凸面侧;同一所述衬垫中,所述邦定区弯折后的曲率越大,相邻所述第一金手指的间距越小;同一所述衬垫中,所述邦定区弯折后的曲率越小,相邻所述第一金手指的间距越大。
在其中一个实施例中,所述第一金手指具有用以与覆晶薄膜的第二金手指电连接固定的表面,所述表面设有凹槽。
在其中一个实施例中,所述邦定区围绕所述显示区的相邻的两个侧边设置。
在其中一个实施例中,还包括设于所述邦定区的驱动电路芯片,所述驱动电路芯片通过覆晶薄膜与所述邦定区邦定;所述覆晶薄膜的远离所述驱动电路芯片的一侧设有若干个间隔平行排列的第二金手指,所述第二金手指均匀的设于所述覆晶薄膜上,若干个所述第一金手指与分别与若干个所述第二金手指电连接。
在其中一个实施例中,所述第一金手指沿垂直于所述阵列基板厚度方向的截面积,大于所述第二金手指沿垂直于所述阵列基板厚度方向的截面积。
本发明还提供一种阵列基板。
一种阵列基板,包括:
显示区;
邦定区,围绕所述显示区设置;所述阵列基板的邦定区设有至少一个衬垫,所述衬垫包括若干个间隔平行排列的第一金手指;所述邦定区弯折后,所述衬垫位于所述邦定区的凹面侧;同一所述衬垫中,所述邦定区弯折后的曲率越大,相邻所述第一金手指的间距越大;同一所述衬垫中,所述邦定区弯折后的曲率越小,相邻所述第一金手指的间距越小;
驱动电路芯片,设于所述阵列基板的邦定区,所述驱动电路芯片通过覆晶薄膜与所述邦定区邦定;所述覆晶薄膜的远离所述驱动电路芯片的一侧设有若干个间隔平行排列的第二金手指,所述第二金手指均匀的设于所述覆晶薄膜上,若干个所述第一金手指分别与若干个所述第二金手指电连接。
上述阵列基板,同一衬垫中,相邻两个第一金手指的间距缩小,即通过增大相邻两个第一金手指的间距,使得相邻两个第一金手指151缩小后的间距与覆晶薄膜的第二金手指匹配,以保证第一金手指和第二金手指的接触面积,从而保证覆晶薄膜与阵列基板信号接触良好,即有效避免显示面板显示异常。
本发明还提供一种显示面板。
一种显示面板,包括本发明提供的阵列基板以及与所述阵列基板对盒设置的彩膜基板。
上述显示面板包括本发明提供的阵列基板,同一衬垫中,相邻第一金手指的间距不完全相同,以使得邦定区弯折后,第一金手指与覆晶薄膜上的第二金手指匹配,以保证第一金手指和第二金手指的接触面积,从而保证覆晶薄膜与阵列基板信号接触良好,即有效避免显示面板显示异常。
本发明还提供一种显示装置。
一种显示装置,包括本发明提供的显示面板。
上述显示装置包括本发明提供的显示面板,同一衬垫中,相邻第一金手指的间距不完全相同,以使得邦定区弯折后,第一金手指与覆晶薄膜上的第二金手指匹配,以保证第一金手指和第二金手指的接触面积,从而保证覆晶薄膜与阵列基板信号接触良好,即有效避免显示面板显示异常。
附图说明
图1为本发明一实施例提供的阵列基板的结构示意图;
图2为图1所示阵列基板的M-M向视图;
图3为图2所示阵列基板弯折后的截面示意图;
图4为图1的P的局部放大图;
图5本发明另一实施例提供的阵列基板的截面示意图;
图6为图5所示阵列基板弯折后的截面示意图;
图7为本发明再一实施例提供的阵列基板弯折后的截面示意图。
具体实施方式
驱动电路芯片(driver integrated circuit)通过与阵列基板的邦定区邦定。具体地,邦定区设有衬垫,衬垫包括若干个间隔排列的第一金手指,覆晶膜膜上同样设有若干个间隔排列的第二金手指。衬垫上的第一金手指分别与覆晶薄膜上的第二金手指通过异方性导电胶膜(Anisotropic Conductive Film,ACF)粘接。
发明人经研究发现,邦定区弯折后,位于邦定区上的相邻的第一金手指的间距具有变大或变小的趋势;而相应的覆晶薄膜上,相邻的第二金手指的间距具有沿相反的方向变化的趋势。因此,在邦定区弯折后,第一金手指和第二金手指具有错位的趋势,严重的,可能导致出现第一金手指和第二金手指错位的现象,进而导致阵列基板上的金手指和覆晶薄膜上的金手指接触不良,导致显示面板显示异常。
针对上述问题,本发明提供一种阵列基板,其包括显示区以及围绕所述显示区设置的邦定区;所述阵列基板的邦定区设有至少一个衬垫,所述衬垫包括若干个间隔平行排列的第一金手指;同一所述衬垫中,相邻所述第一金手指的间距不完全相等。
同一衬垫中,相邻第一金手指的间距不完全相同,以使得邦定区弯折后,第一金手指与覆晶薄膜上的第二金手指匹配,避免第一金手指和第二金手指具有发生错位的趋势,以保证第一金手指和第二金手指的接触面积,从而保证覆晶薄膜与阵列基板信号接触良好,即有效避免显示面板显示异常。
为使本发明的上述目的、特征和优点能够更加明显易懂,下面结合附图对本发明的具体实施方式做详细的说明。在下面的描述中阐述了很多具体细节以便于充分理解本发明。但是本发明能够以很多不同于在此描述的其它方式来实施,本领域技术人员可以在不违背本发明内涵的情况下做类似改进,因此本发明不受下面公开的具体实施例的限制。
需要说明的是,当元件被称为“固定于”另一个元件,它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件,它可以是直接连接到另一个元件或者可能同时存在居中元件。
除非另有定义,本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的,不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
如图1至图4所示,本发明一实施例提供的阵列基板100,其包括显示区110以及围绕显示区110设置的邦定区130。阵列基板100的邦定区130设有四个衬垫150。
具体地,衬垫150包括若干个间隔平行排列的第一金手指151。同一衬垫150中,相邻第一金手指151的间距不完全相等。
需要说明的是,本申请中,相邻第一金手指151的间距均指邦定区130未弯折时的间距。
同一衬垫150中,相邻第一金手指151的间距不完全相同,以使得邦定区130弯折后,第一金手指151与覆晶薄膜上的第二金手指匹配,以保证第一金手指151和第二金手指的接触面积,从而保证覆晶薄膜与阵列基板100信号接触良好,即有效避免显示面板显示异常。
在本实施例中,邦定区130弯折后,衬垫150位于邦定区130的凹面侧,详参图3。同一衬垫150中,邦定区130弯折后的曲率越大,相邻第一金手指151的间距越大。同一衬垫150中,邦定区130弯折后的曲率越小,相邻第一金手指151的间距越小。
具体到本实施例中,参图2和图3所示,以左侧的衬垫150为例,邦定区130弯折后,邦定区130的与左侧的衬垫150对应部分的曲率由左至右逐渐减小。设定左侧第一个第一金手指151与第二个第一金手指151的间距为A,设定左侧第二个第一金手指151与第三个金手指151的间距为B,A>B,依此类推。
更具体地,邦定区130弯曲时,同一衬垫150中,相邻两个第一金手指151的间距缩小。本实施例通过增大相邻两个第一金手指151的间距,使得相邻两个第一金手指151缩小后的间距与覆晶薄膜的第二金手指匹配。
当然,在另外的实施例中,若衬垫的部分或全部区域对应的邦定区的曲率相同,则衬垫相应区域的相邻第一金手指151的间距相同。例如,本实施例中,位于显示区110的第二侧边113外围的邦定区130不弯折,则位于该区域内的统一衬垫150中,相邻第一金手指151的间距相同。
详参图4,本实施例中,第一金手指151具有用以与覆晶薄膜的第二金手指电连接固定的表面1511,表面1511设有凹槽1513。具体的,第一金手指151与覆晶薄膜的第二金手指之间通过异方性导电胶膜(Anisotropic Conductive Film,ACF)粘结。在覆晶薄膜与阵列基板100邦定过程中,凹槽1513的设置,可以排除AFC与第一金手指151之间的气体,从而减少覆晶薄膜与阵列基板100邦定过程中产生的气泡,进而提高第一金手指151与ACF之间的粘结力,从而有效防止第一金手指151与第二金手指发生错位。
另外的,本实施例中,凹槽1513的设置,可以有有效减少第一金手指151上的弯折应力,从而有效避免相邻第一金手指151的间距在邦定区130的弯折带动下过多的减小。
本实施例中,邦定区130围绕显示区110的相邻的两个侧边设置。具体的,邦定区130围绕显示区110的第一侧边111和第二侧边113设置。当然,在另外的实施例中,邦定区还可以进围绕显示区111的任意一个侧边或任意两个或多于两个侧边设置。
本实施例中,阵列基板100为薄膜晶体管阵列基板。当然,在另外的实施例中,阵列基板还可以是其它类型的阵列基板。
如图5和图6所示,本发明另一实施例提供的阵列基板200,其与阵列基板100不同的是,邦定区230弯折后,衬垫250位于邦定区230的凸面侧。具体地,同一衬垫250中,邦定区230弯折后的曲率越大,相邻第一金手指251的间距越小。同一衬垫250中,邦定区230弯折后的曲率越小,相邻第一金手指251的间距越大。
具体到本实施例中,以左侧的衬垫250为例,邦定区230弯折后,邦定区230的与左侧的衬垫250对应的部分的曲率由左至右逐渐减小。设定右侧第一个第一金手指251与第二个金手指251的间距为C,设定右侧第二个第一金手指251与第三个金手指251的间距为D,C>D,依此类推。
更具体地,邦定区230弯曲时,同一衬垫250中,相邻两个第一金手指251的间距增大。本实施例通过减小相邻两个第一金手指251之间的间距,使得相邻两个第一金手指251增大后的间距与覆晶薄膜的第二金手指匹配。
需要说明的是,阵列基板100邦定区130和阵列基板200的邦定区均只朝一个方向弯曲。在另外的实施例中,阵列基板的邦定区还可以朝多个方向弯曲,即阵列基板的邦定区还可以呈波浪状等其它规则或不规则的形状。相应的,每个衬垫中相邻第一金手指之间的间距根据对应区域的邦定区的弯折方向和曲率进行设定。
如图7所示,本发明再一实施例提供的阵列基板300,其与阵列基板100不同的是,阵列基板300还包括设于邦定区330的驱动电路芯片370。驱动电路芯片370通过覆晶薄膜390与邦定区330邦定。覆晶薄膜390的远离驱动电路芯片370的一侧设有若干个间隔平行排列的第二金手指391,第二金手指391均匀的设于覆晶薄膜390上。若干个第一金手指351与分别与若干个第二金手指391电连接。
在一个可行的实施例中,第一金手指沿垂直于阵列基板厚度方向的截面积,大于第二金手指沿垂直于阵列基板厚度方向的截面积。使得第一金手指和第二金手指即使发生微小的错位,也能保证第一金手指和第二金手指的接触面积,从而保证覆晶薄膜与阵列基板信号接触良好,即有效避免显示面板显示异常。
本发明一实施例还提供一种显示面板,其包括本发明提供的阵列基板以及与所述阵列基板对盒设置的彩膜基板。
上述显示面板包括本发明提供的阵列基板,同一衬垫中,相邻第一金手指的间距不完全相同,以使得邦定区弯折后,第一金手指与覆晶薄膜上的第二金手指匹配,以保证第一金手指和第二金手指的接触面积,从而保证覆晶薄膜与阵列基板信号接触良好,即有效避免显示面板显示异常。
本发明一实施例还提供一种显示装置,其包括本发明提供的显示面板。
上述显示装置包括本发明提供的显示面板,同一衬垫中,相邻第一金手指的间距不完全相同,以使得邦定区弯折后,第一金手指与覆晶薄膜上的第二金手指匹配,以保证第一金手指和第二金手指的接触面积,从而保证覆晶薄膜与阵列基板信号接触良好,即有效避免显示面板显示异常。
以上所述实施例的各技术特征可以进行任意的组合,为使描述简洁,未对上述实施例中的各个技术特征所有可能的组合都进行描述,然而,只要这些技术特征的组合不存在矛盾,都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式,其描述较为具体和详细,但并不能因此而理解为对发明专利范围的限制。应当指出的是,对于本领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干变形和改进,这些都属于本发明的保护范围。因此,本发明专利的保护范围应以所附权利要求为准。
Claims (10)
1.一种阵列基板,其特征在于,包括:
显示区;
以及邦定区,围绕所述显示区设置;所述阵列基板的邦定区设有至少一个衬垫,所述衬垫包括若干个间隔平行排列的第一金手指;同一所述衬垫中,相邻所述第一金手指的间距不完全相等。
2.根据权利要求1所述的阵列基板,其特征在于,所述邦定区弯折后,所述衬垫位于所述邦定区的凹面侧;同一所述衬垫中,所述邦定区弯折后的曲率越大,相邻所述第一金手指的间距越大;同一所述衬垫中,所述邦定区弯折后的曲率越小,相邻所述第一金手指的间距越小。
3.根据权利要求1所述的阵列基板,其特征在于,所述邦定区弯折后,所述衬垫位于所述邦定区的凸面侧;同一所述衬垫中,所述邦定区弯折后的曲率越大,相邻所述第一金手指的间距越小;同一所述衬垫中,所述邦定区弯折后的曲率越小,相邻所述第一金手指的间距越大。
4.根据权利要求1所述的阵列基板,其特征在于,所述第一金手指具有用以与覆晶薄膜的第二金手指电连接固定的表面,所述表面设有凹槽。
5.根据权利要求1所述的阵列基板,其特征在于,所述邦定区围绕所述显示区的相邻的两个侧边设置。
6.根据权利要求1所述的阵列基板,其特征在于,还包括设于所述邦定区的驱动电路芯片,所述驱动电路芯片通过覆晶薄膜与所述邦定区邦定;所述覆晶薄膜的远离所述驱动电路芯片的一侧设有若干个间隔平行排列的第二金手指,所述第二金手指均匀的设于所述覆晶薄膜上,若干个所述第一金手指分别与若干个所述第二金手指电连接。
7.根据权利要求6所述的阵列基板,其特征在于,所述第一金手指沿垂直于所述阵列基板厚度方向的截面积,大于所述第二金手指沿垂直于所述阵列基板厚度方向的截面积。
8.一种阵列基板,其特征在于,包括:
显示区;
邦定区,围绕所述显示区设置;所述阵列基板的邦定区设有至少一个衬垫,所述衬垫包括若干个间隔平行排列的第一金手指;所述邦定区弯折后,所述衬垫位于所述邦定区的凹面侧;同一所述衬垫中,所述邦定区弯折后的曲率越大,相邻所述第一金手指的间距越大;同一所述衬垫中,所述邦定区弯折后的曲率越小,相邻所述第一金手指的间距越小;
以及驱动电路芯片,设于所述阵列基板的邦定区,所述驱动电路芯片通过覆晶薄膜与所述邦定区邦定;所述覆晶薄膜的远离所述驱动电路芯片的一侧设有若干个间隔平行排列的第二金手指,所述第二金手指均匀的设于所述覆晶薄膜上,若干个所述第一金手指分别与若干个所述第二金手指电连接。
9.一种显示面板,其特征在于,包括权利要求1至8任一项所述的阵列基板以及与所述阵列基板对盒设置的彩膜基板。
10.一种显示装置,其特征在于,包括权利要求9所述的显示面板。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201811230980.9A CN109087589B (zh) | 2018-10-22 | 2018-10-22 | 阵列基板、显示面板及显示装置 |
US17/042,312 US11355523B2 (en) | 2018-10-22 | 2018-11-15 | Array substrate, display panel, and display device |
PCT/CN2018/115699 WO2020082461A1 (zh) | 2018-10-22 | 2018-11-15 | 阵列基板、显示面板及显示装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201811230980.9A CN109087589B (zh) | 2018-10-22 | 2018-10-22 | 阵列基板、显示面板及显示装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN109087589A true CN109087589A (zh) | 2018-12-25 |
CN109087589B CN109087589B (zh) | 2021-06-18 |
Family
ID=64844104
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201811230980.9A Active CN109087589B (zh) | 2018-10-22 | 2018-10-22 | 阵列基板、显示面板及显示装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US11355523B2 (zh) |
CN (1) | CN109087589B (zh) |
WO (1) | WO2020082461A1 (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109976577A (zh) * | 2019-03-22 | 2019-07-05 | 江西合力泰科技有限公司 | 一种带指纹识别触显功能的模组 |
CN115798375A (zh) * | 2022-11-14 | 2023-03-14 | 惠科股份有限公司 | 覆晶薄膜、显示面板及显示装置 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101510383A (zh) * | 2009-03-26 | 2009-08-19 | 友达光电股份有限公司 | 平面显示面板 |
CN105529338A (zh) * | 2016-02-06 | 2016-04-27 | 京东方科技集团股份有限公司 | 阵列基板、覆晶薄膜、显示面板及显示装置 |
CN105529339A (zh) * | 2016-02-17 | 2016-04-27 | 京东方科技集团股份有限公司 | 阵列基板、覆晶薄膜及显示装置 |
US20170221845A1 (en) * | 2013-03-11 | 2017-08-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging Devices and Methods of Manufacture Thereof |
CN107703664A (zh) * | 2017-09-27 | 2018-02-16 | 武汉华星光电技术有限公司 | 内嵌式触控面板 |
CN107749239A (zh) * | 2017-10-31 | 2018-03-02 | 武汉天马微电子有限公司 | 显示面板、显示装置及显示面板的制作方法 |
CN108391373A (zh) * | 2018-02-28 | 2018-08-10 | 武汉华星光电半导体显示技术有限公司 | 一种电路基板及显示设备 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20090058987A (ko) * | 2007-12-05 | 2009-06-10 | 엘지디스플레이 주식회사 | 액정표시장치의 제조방법 및 액정표시장치의 필름 캐리어테이프 제조방법 |
US8803839B2 (en) | 2010-10-31 | 2014-08-12 | Pixart Imaging Inc. | Capacitive coupling of a capacitive touchscreen to a printed circuit and controller |
KR102330882B1 (ko) * | 2014-10-13 | 2021-11-25 | 삼성디스플레이 주식회사 | 표시 장치 |
US9679862B2 (en) * | 2014-11-28 | 2017-06-13 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device having conductive bumps of varying heights |
CN104540315B (zh) * | 2014-12-31 | 2018-01-30 | 深圳市华星光电技术有限公司 | 软性印刷电路板和液晶显示器 |
CN205912332U (zh) * | 2016-08-28 | 2017-01-25 | 江西合力泰科技有限公司 | 一种显示模组上的fpc板 |
CN206620358U (zh) * | 2017-04-10 | 2017-11-07 | 创维液晶器件(深圳)有限公司 | 一种双过孔fpc金手指结构 |
CN108668426A (zh) * | 2018-04-18 | 2018-10-16 | 武汉天马微电子有限公司 | 一种电路板及显示装置 |
-
2018
- 2018-10-22 CN CN201811230980.9A patent/CN109087589B/zh active Active
- 2018-11-15 WO PCT/CN2018/115699 patent/WO2020082461A1/zh active Application Filing
- 2018-11-15 US US17/042,312 patent/US11355523B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101510383A (zh) * | 2009-03-26 | 2009-08-19 | 友达光电股份有限公司 | 平面显示面板 |
US20170221845A1 (en) * | 2013-03-11 | 2017-08-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging Devices and Methods of Manufacture Thereof |
CN105529338A (zh) * | 2016-02-06 | 2016-04-27 | 京东方科技集团股份有限公司 | 阵列基板、覆晶薄膜、显示面板及显示装置 |
CN105529339A (zh) * | 2016-02-17 | 2016-04-27 | 京东方科技集团股份有限公司 | 阵列基板、覆晶薄膜及显示装置 |
CN107703664A (zh) * | 2017-09-27 | 2018-02-16 | 武汉华星光电技术有限公司 | 内嵌式触控面板 |
CN107749239A (zh) * | 2017-10-31 | 2018-03-02 | 武汉天马微电子有限公司 | 显示面板、显示装置及显示面板的制作方法 |
CN108391373A (zh) * | 2018-02-28 | 2018-08-10 | 武汉华星光电半导体显示技术有限公司 | 一种电路基板及显示设备 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109976577A (zh) * | 2019-03-22 | 2019-07-05 | 江西合力泰科技有限公司 | 一种带指纹识别触显功能的模组 |
CN109976577B (zh) * | 2019-03-22 | 2024-04-12 | 江西合力泰科技有限公司 | 一种带指纹识别触显功能的模组 |
CN115798375A (zh) * | 2022-11-14 | 2023-03-14 | 惠科股份有限公司 | 覆晶薄膜、显示面板及显示装置 |
Also Published As
Publication number | Publication date |
---|---|
US20210043659A1 (en) | 2021-02-11 |
CN109087589B (zh) | 2021-06-18 |
US11355523B2 (en) | 2022-06-07 |
WO2020082461A1 (zh) | 2020-04-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6411353B1 (en) | Liquid crystal display device with its upper and lower cases clamped by crimping portions thereof | |
WO2020249009A1 (zh) | 显示面板及显示装置 | |
TW200540509A (en) | Display device | |
KR102424969B1 (ko) | 표시장치 및 그 제조방법 | |
JP2001154178A (ja) | 積層型表示装置 | |
EP3037875B1 (en) | Array substrate for display device and display device | |
JP2019124829A (ja) | 表示装置 | |
WO2019228342A1 (zh) | 柔性显示装置和异形双面胶带 | |
US10917970B2 (en) | Display panel and display | |
CN110161763A (zh) | 显示面板及显示装置 | |
CN108388046A (zh) | 背光模组、显示模组和显示装置 | |
CN109144320A (zh) | 显示面板和显示装置 | |
US20210037646A1 (en) | Flexible printed circuit board and display device | |
CN110299073A (zh) | 一种显示面板、柔性连接件和显示装置 | |
US20190243187A1 (en) | Display module | |
CN109087589A (zh) | 阵列基板、显示面板及显示装置 | |
US5563619A (en) | Liquid crystal display with integrated electronics | |
US20080252805A1 (en) | Liquid crystal panel with anti-ESD conductive leads and liquid crystal display with same | |
TWI696867B (zh) | 膠帶結構及使用其之顯示面板和顯示裝置 | |
JP3254230B2 (ja) | 液晶ディスプレイパネルの配線構造 | |
CN111007674A (zh) | 背光式弯曲显示装置 | |
JP2007178668A (ja) | 平面表示装置及びその製造方法 | |
US9477123B2 (en) | Liquid crystal display device and production method thereof | |
CN109061962A (zh) | 显示面板及其制造方法、显示装置 | |
US11654670B2 (en) | Lamination apparatus and method for manufacturing display device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |