CN203894515U - 一种阵列基板及显示装置 - Google Patents
一种阵列基板及显示装置 Download PDFInfo
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- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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- G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136218—Shield electrodes
Abstract
本实用新型公开了一种阵列基板及显示装置,将与栅线延伸方向相同的公共电极线设置在靠近薄膜晶体管的一端,且与薄膜晶体管的漏极形成存储电容,相较于现有技术中将阵列基板中的公共电极线与薄膜晶体管分别设置在像素的两端,需要单独设置存储电容电极与公共电极线形成存储电容,可以有效地减少薄膜晶体管与公共电极线占用的像素区域,增大开口率,提高了IPS液晶显示装置的显示亮度。
Description
技术领域
本实用新型涉及显示技术领域,尤其涉及一种阵列基板及显示装置。
背景技术
目前,液晶显示技术被广泛应用于电视、手机以及公共信息的显示,其画面质量是这些产品成功的重要条件,而决定画面质量的众多参数里,液晶显示亮度是一个重要的参数标准。
在现有技术中,平面转换(IPS,In Plane Switching)的液晶显示模式的显示装置的阵列基板的最大特点就是它的像素电极与公共电极都在同一个平面上,即公共电极和像素电极同层设置,现有IPS模式液晶显示装置的阵列基板的结构,如图1所示,主要包括:栅线1、数据线2、薄膜晶体管3、像素电极连接部4、像素电极5、公共电极6、公共电极连接部7及公共电极线8;其中,相邻栅线与相邻数据线定义的区域为一个像素区域;像素电极与公共电极在像素区域内同层且间隔设置;薄膜晶体管3的栅极与栅线1相连、源极与数据线2相连、漏极9与像素电极连接部4相连;公共电极线8通过过孔与公共电极连接部7相连,为了保证像素电极在一帧画面的时间内电压相对恒定,且因为像素电极5与公共电极连接部7为同层设置,它们之间不能设置存储电容,需要一个单独的区域设置存储电容,比如在靠近薄膜晶体管3的一端设置存储电容电极91,并将公共电极线8的一个分支81引入到薄膜晶体管3附近,这样公共电极线8与该存储电容电极91形成存储电容。这样的结构造成公共电极线8与薄膜晶体管3所占区域过多的占用了像素区域,使开口率降低,减少了透光率,影响了液晶显示装置的显示亮度。
因此,如何提高IPS模式液晶显示装置的开口率,是本领域技术人员亟待解决的问题。
实用新型内容
本实用新型实施例提供了一种阵列基板及显示装置,用以解决现有技术中存在的IPS液晶显示装置开口率小的问题。
本实用新型实施例提供了一种阵列基板,包括栅线、数据线和公共电极线,相邻的所述栅线和相邻的所述数据线定义的区域为一像素;所述像素包括:位于所述栅线和所述数据线的交叉区域且与所述栅线和所述数据线分别电性相连的薄膜晶体管,多个像素电极,连接多个所述像素电极的像素电极连接部,多个与所述像素电极同层设置且间隔设置的公共电极,以及连接多个所述公共电极的公共电极连接部;
所述公共电极线与所述栅线的延伸方向相同,且位于靠近所述薄膜晶体管的一端,与所述薄膜晶体管的漏极形成存储电容;
所述像素还包括:用于电性连接所述公共电极线与各所述公共电极的导线。
本实用新型实施例提供的上述阵列基板中,将与栅线延伸方向相同的公共电极线设置在靠近薄膜晶体管的一端,且与薄膜晶体管的漏极形成存储电容,相较于现有技术中将阵列基板中的公共电极线与薄膜晶体管分别设置在像素的两端,需要单独设置存储电容电极与公共电极线形成存储电容,可以有效地减少薄膜晶体管与公共电极线占用的像素区域,增大开口率,提高了IPS液晶显示装置的显示亮度。
在一种可能的实施方式中,本实用新型实施例提供的上述阵列基板中,所述导线通过所述公共电极连接部与所述公共电极电性相连。
在一种可能的实施方式中,本实用新型实施例提供的上述阵列基板中,所述导线在所述阵列基板上的正投影位于所述数据线所在区域内。
在一种可能的实施方式中,本实用新型实施例提供的上述阵列基板中,所述导线与所述数据线的延伸方向相同,且所述导线在所述阵列基板上的正投影位于所述数据线与相邻的所述像素电极之间。
在一种可能的实施方式中,本实用新型实施例提供的上述阵列基板中,所述导线在所述阵列基板上的正投影部分位于所述数据线所在区域内。
在一种可能的实施方式中,本实用新型实施例提供的上述阵列基板中,所述导线为一个,且位于靠近所述薄膜晶体管的一端。
在一种可能的实施方式中,本实用新型实施例提供的上述阵列基板中,所述像素还包括:位于远离所述薄膜晶体管的一端的屏蔽电极线;
所述屏蔽电极线与所述数据线的延伸方向相同;
所述屏蔽电极线在所述阵列基板上的正投影位于所述数据线与相邻的所述像素电极之间,或所述屏蔽电极线在所述阵列基板上的正投影位于所述数据线所在区域内,或所述屏蔽电极线在所述阵列基板上的正投影部分位于所述数据线所在区域内。
在一种可能的实施方式中,本实用新型实施例提供的上述阵列基板中,所述屏蔽电极线的一端与所述公共电极线电性相连;或,
所述屏蔽电极线的另一端与所述公共电极连接部电性相连;或,
所述屏蔽电极线的两端悬空设置。
在一种可能的实施方式中,本实用新型实施例提供的上述阵列基板中,所述屏蔽电极线和所述导线与公共电极线同层设置。
本实用新型实施例提供了一种显示装置,包括本实用新型实施例提供的所述的阵列基板。
附图说明
图1为现有技术中IPS液晶显示装置阵列基板结构示意图;
图2为本实用新型提供的阵列基板结构示意图;
图3为本实用新型提供的阵列基板详细结构示意图;
图4为本实用新型提供的阵列基板详细结构示意图沿B-B剖面结构示意图;
图5为本实用新型提供的阵列基板详细结构示意图沿A-A剖面结构示意图;
图6为本实用新型提供的阵列基板详细结构示意图沿C-C剖面结构示意图。
具体实施方式
下面结合附图,对本实用新型实施例提供的阵列基板及显示装置的具体实施方式进行详细地说明。
附图中各膜层的厚度和区域的大小形状不反映阵列基板各部件的真实比例,目的只是示意说明本实用新型的内容。
本实用新型提供了一种阵列基板,如图2所示,包括栅线01、数据线02和公共电极线03,相邻的栅线01和相邻的数据线02定义的区域为一像素;
像素包括:位于栅线01和数据线02的交叉区域且与栅线01和数据线02分别电性相连的薄膜晶体管04,多个像素电极05,连接多个所述像素电极的像素电极连接部06,多个与像素电极05同层设置且间隔设置的公共电极07,以及连接多个公共电极07的公共电极连接部08;
公共电极线03与栅线01的延伸方向相同,且位于靠近薄膜晶体管的一端,与薄膜晶体管04的漏极09形成存储电容,一般地,薄膜晶体管04的漏极09通过过孔18与像素电极连接部06相连;
像素还包括:用于电性连接公共电极线03与各公共电极07的导线10,一般地,导线10通过过孔19与公共电极连接部08相连。
本实用新型实施例提供的上述阵列基板中,将与栅线01延伸方向相同的公共电极线03设置在靠近薄膜晶体管的一端,且与薄膜晶体管04的漏极09形成存储电容,相较于现有技术中将阵列基板中的公共电极线03与薄膜晶体管04分别设置在像素的两端,需要单独设置存储电容电极与公共电极线03形成存储电容,可以有效地减少薄膜晶体管04与公共电极线03占用的像素区域,增大开口率,提高了IPS液晶显示装置的显示亮度,且公共电极线03与薄膜晶体管04的漏极09形成存储电容,可以保证像素电极05在一帧画面期间的电压相对恒定,保证了IPS液晶显示装置显示的画面质量。
在具体实施时,本实用新型实施例提供的上述阵列基板中,公共电极线03可以通过导线10与公共电极连接部08电性相连,如图2所示;公共电极线03还可以直接通过导线10与公共电极07相连,即公共电极线03不通过公共电极连接部08,在与各公共电极07相对应的地方引出导线10直接与各公共电极07相连;其中,公共电极线03通过导线10与公共电极连接部08相连,可以在信号传输时将信号直接传输到公共电极连接部08,进而传输到各公共电极07;若公共电极线03与各公共电极07直接相连,则可以在信号传输时将信号直接传输给公共电极07,此种方式信号传输线比较短,信号传输较快。在实际应用时,可以根据需要设置导线的连接关系,在此不做限定。
以下都是以导线10与公共电极连接部08电性相连为例进行说明。一般地,将导线10设置为与数据线02的延伸方向相同。
具体地,本实用新型实施例提供的上述阵列基板中,数据线02会与像素电极05处于相邻的关系,如图3和图4所示,这样数据线02的电压变化会对相邻的像素电极05的电压造成干扰,因此,为了解决该问题,在具体实施时,可以利用导线10来屏蔽数据线02的电压变化对相邻像素电极05的干扰。
具体地,可以将导线10设置为在阵列基板上的正投影位于数据线02所在区域内,即导线10在阵列基板的正投影完全落入数据线02在阵列基板的正投影区域内;或者,将导线10设置为在阵列基板上的正投影位于数据线02与相邻的像素电极05之间;或者,将导线10设置在阵列基板上的正投影部分位于数据线02所在区域内,在此不作限定。在具体实施时,在导线10设置在阵列基板的方式为上述任一种方式时,导线10不但可以作为连接公共电极线03和公共电极的导线,从而进行公共电极信号的传输;还可以作为屏蔽数据线02的电压变化对像素电极05的电压干扰的屏蔽电极,保证了IPS液晶显示装置显示的画面质量。
在具体实施时,本实用新型提供的上述阵列基板中,导线10的个数可以为一个,也可以为多个,具体地,当设置的导线10为两个时,可以将两个导线10分别设置在靠近两个数据线02的一端,这样两个导线10可以分别屏蔽两个数据线02对相邻像素电极05的信号干扰。
当设置的导线10为一个时,可以将导线10设置为位于靠近薄膜晶体管的一端,这样可以在将公共电极线03的公共电极信号传递到公共电极07的基础上,尽量减少导线10占用像素域的区面积。
进一步地,在导线10为一个时,为了避免另一端的数据线02对相邻的像素电极05产生信号干扰,在具体实施时,如图3和图4所示,像素还可以包括位于远离薄膜晶体管04的一端的屏蔽电极线11;该屏蔽电极线11与数据线02的延伸方向相同;且屏蔽电极线11在阵列基板上的正投影可以位于数据线02与相邻的像素电极05之间,屏蔽电极线11在阵列基板上的正投影还可以位于数据线02所在区域内,屏蔽电极线11在阵列基板上的正投影还可以部分位于数据线02所在区域内。增加的屏蔽电极线11也可以起到屏蔽数据线02的电压变化对相邻像素电极05信号干扰的作用。
在具体实施时,本实用新型提供的上述阵列基板中,如图3所示,屏蔽电极线11的一端可以与公共电极线03电性相连,或者,屏蔽电极线11的另一端可以与公共电极连接部08电性相连,或者,屏蔽电极线11的两端还可以悬空设置,在此不做限定。在具体实施时,本实用新型实施例提供的上述阵列基板中,屏蔽电极线11可以采用上述任一种方式进行设置,在此不作限定。这样,屏蔽电极线11可以屏蔽数据线02的电压变化对像素电极05的电压造成的干扰,保证了IPS液晶显示装置显示画面的质量。
在具体实施时,本实用新型提供的上述阵列基板中,屏蔽电极线11和导线10可以与公共电极线03同层设置,在阵列基板制备过程中,可以简化制作工艺,采用一步工艺即可形成屏蔽电极线11、导线10和公共电极线03的图形。
下面以上述阵列基板的结构为例,对其制备过程进行详细说明:
步骤一:沉积金属层,涂覆光刻胶,曝光显影,刻蚀,形成栅线01,薄膜晶体管的栅极12、公共电极线03,导线10,屏蔽电极线11,如图5所示;其中,栅线01和公共电极线03可以采用铜、铝、钼等金属材料制备,也可以采用合金材料制备;栅线01可以采用单层结构,也可以采用多层结构,在此不作限定。
步骤二:沉积栅绝缘层13,其中栅绝缘层13可以采用氮化硅或氧化硅材料制备;栅绝缘层13可以采用单层结构,也可以采用多层结构,栅绝缘层13在阵列基板中的结构,如图5所示。
步骤三:沉积半导体层,即有源层14,有源层14可以采用非晶硅,或铟镓锌氧化物等氧化物半导体材料制备;制备过程为涂覆光刻胶、曝光显影、刻蚀,形成有源层14的图形,有源层14在阵列基板中的结构,如图5所示。
步骤四:沉积金属层,涂覆光刻胶,曝光显影,刻蚀,形成数据线02,薄膜晶体管04的源极15和漏极09,同时还形成了存储电容电极16,存储电容电极16与薄膜晶体管04的漏极09为一体结构,如图5所示。
步骤五:沉积钝化层17,钝化层17可以采用无机物如氮化硅,或有机物如树脂进行制备;其制备过程为涂覆光刻胶,曝光显影,刻蚀,并形成第一过孔18和第二过孔19,如图5和图6所示。
步骤六:沉积金属材料或透明金属氧化物导电材料层,涂覆光刻胶,曝光显影,刻蚀,形成像素电极05、像素电极连接部06、公共电极07和公共电极连接部08;存储电容电极16通过第一过孔18与像素电极连接部06相连,如图5所示;导线10通过第二过孔19与公共电极连接部08相连,如图6所示。
在具体实施时,本实用新型实施例提供的上述阵列基板可以应用于液晶显示面板,也可以应用于有机电致发光显示面板,在此不做限定。
基于同一实用新型构思,本实用新型实施例还提供了一种显示装置,包括本实用新型实施例提供的上述阵列基板,该显示装置可以是显示器、手机、电视、笔记本、一体机等,对于显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的,在此不做赘述,也不应作为对本实用新型的限制。
本实用新型实施例提供了一种阵列基板及显示装置,将阵列基板中与栅线延伸方向相同的公共电极线设置在靠近薄膜晶体管的一端,且与薄膜晶体管的漏极形成存储电容,相较于现有技术中将阵列基板中的公共电极线与薄膜晶体管分别设置在像素的两端,需要单独设置存储电容电极与公共电极线形成存储电容,可以有效地减少薄膜晶体管与公共电极线占用的像素区域,增大开口率,提高了IPS液晶显示装置的显示亮度。
显然,本领域的技术人员可以对本实用新型进行各种改动和变型而不脱离本实用新型的精神和范围。这样,倘若本实用新型的这些修改和变型属于本实用新型权利要求及其等同技术的范围之内,则本实用新型也意图包含这些改动和变型在内。
Claims (10)
1.一种阵列基板,包括栅线、数据线和公共电极线,相邻的所述栅线和相邻的所述数据线定义的区域为一像素;所述像素包括:位于所述栅线和所述数据线的交叉区域且与所述栅线和所述数据线分别电性相连的薄膜晶体管,多个像素电极,连接多个所述像素电极的像素电极连接部,多个与所述像素电极同层设置且间隔设置的公共电极,以及连接多个所述公共电极的公共电极连接部,其特征在于:
所述公共电极线与所述栅线的延伸方向相同,且位于靠近所述薄膜晶体管的一端,与所述薄膜晶体管的漏极形成存储电容;
所述像素还包括:用于电性连接所述公共电极线与各所述公共电极的导线。
2.如权利要求1所述的阵列基板,其特征在于,所述导线通过所述公共电极连接部与所述公共电极电性相连。
3.如权利要求2所述的阵列基板,其特征在于,所述导线在所述阵列基板上的正投影位于所述数据线所在区域内。
4.如权利要求2所述的阵列基板,其特征在于,所述导线与所述数据线的延伸方向相同,且所述导线在所述阵列基板上的正投影位于所述数据线与相邻的所述像素电极之间。
5.如权利要求2所述的阵列基板,其特征在于,所述导线在所述阵列基板上的正投影部分位于所述数据线所在区域内。
6.如权利要求2-5任一项所述的阵列基板,其特征在于,所述导线为一个,且位于靠近所述薄膜晶体管的一端。
7.如权利要求6所述的阵列基板,其特征在于,所述像素还包括:位于远离所述薄膜晶体管的一端的屏蔽电极线;
所述屏蔽电极线与所述数据线的延伸方向相同;
所述屏蔽电极线在所述阵列基板上的正投影位于所述数据线与相邻的所述像素电极之间,或所述屏蔽电极线在所述阵列基板上的正投影位于所述数据线所在区域内,或所述屏蔽电极线在所述阵列基板上的正投影部分位于所述数据线所在区域内。
8.如权利要求7所述的阵列基板,其特征在于,所述屏蔽电极线的一端与所述公共电极线电性相连;或,
所述屏蔽电极线的另一端与所述公共电极连接部电性相连;或,
所述屏蔽电极线的两端悬空设置。
9.如权利要求8所述的阵列基板,其特征在于,所述屏蔽电极线和所述导线与公共电极线同层设置。
10.一种显示装置,其特征在于,包括如权利要求1-9任一项所述的阵列基板。
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