WO2018161549A1 - 显示基板的制作方法、显示基板和显示装置 - Google Patents

显示基板的制作方法、显示基板和显示装置 Download PDF

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Publication number
WO2018161549A1
WO2018161549A1 PCT/CN2017/104432 CN2017104432W WO2018161549A1 WO 2018161549 A1 WO2018161549 A1 WO 2018161549A1 CN 2017104432 W CN2017104432 W CN 2017104432W WO 2018161549 A1 WO2018161549 A1 WO 2018161549A1
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Prior art keywords
layer
thickness
insulating layer
conductive unit
display
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PCT/CN2017/104432
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English (en)
French (fr)
Inventor
王小元
方琰
张逵
许志财
邓鸣
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京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Priority to US15/767,883 priority Critical patent/US10444579B2/en
Publication of WO2018161549A1 publication Critical patent/WO2018161549A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133388—Constructional arrangements; Manufacturing methods with constructional differences between the display region and the peripheral region
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • At least one embodiment of the present disclosure is directed to a method of fabricating a display substrate, a display substrate, and a display device.
  • planarization In Thin-Film-Transistor Liquid Crystal Display (TFT-LCD) products, planarization (PLN) is often used to flatten the film layer and reduce the load.
  • the PLN includes, for example, an organic layer (ORG).
  • At least one embodiment of the present disclosure relates to a method of fabricating a display substrate, a display substrate, and a display device, which are advantageous for reducing the thickness of a flat layer of a peripheral region or removing a flat layer of a peripheral region, facilitating the first conductive unit and the second conductive unit
  • the connection between the second conductive unit and the driving circuit is large, the contact area is large, the contact resistance is small, and the connectivity is good.
  • At least one embodiment of the present disclosure provides a method of fabricating a display substrate, including:
  • the substrate substrate including a display area and a peripheral area;
  • Performing a patterning process on the flat film forming a flat layer of a first thickness in the display region, forming a flat layer of a second thickness in the peripheral region, and forming a first layer in the flat layer of the second thickness a via, the second thickness being less than the first thickness;
  • At least one embodiment of the present disclosure also provides a display substrate, including:
  • a base substrate including a display area and a peripheral area
  • the flat layer including a display region flat layer disposed in the display region and a peripheral region flat layer disposed in the peripheral region, the peripheral region flat layer having a thickness less than The thickness of the flat layer of the display region is provided, and a via hole penetrating the flat layer and the insulating layer is provided in the peripheral region.
  • At least one embodiment of the present disclosure also provides a display substrate, including:
  • a base substrate including a display area and a peripheral area
  • a gate insulating layer disposed on the base substrate
  • a passivation layer disposed on the gate insulating layer, the passivation layer including a passivation layer disposed at a first thickness of the display region and a passivation layer disposed at a second thickness of the peripheral region
  • the second thickness is smaller than the first thickness
  • a via hole is disposed in the gate insulating layer and the passivation layer of the second thickness, or is disposed in the passivation layer of the second thickness Through hole.
  • At least one embodiment of the present disclosure also provides a display device including any of the display substrates described in the embodiments of the present disclosure.
  • 1 is a schematic plan view of a display substrate
  • FIG. 2 is a schematic plan view showing a wiring of a peripheral area of a display substrate
  • Figure 3 is a cross-sectional view taken along line A-B of Figure 1;
  • FIG. 4 is a top plan view showing a peripheral region of a display substrate
  • Figure 5 is a cross-sectional view of Figure 4 taken along line C-D;
  • FIG. 6 is a schematic cross-sectional view of the second conductive unit connected to the first conductive unit when the flat layer of the second thickness is completely removed when thinning is provided in an embodiment of the present disclosure. );
  • FIG. 7 is a top plan view showing a peripheral region of a display substrate
  • Figure 8 is a cross-sectional view of Figure 7 taken along E-F;
  • FIG. 9A is a schematic diagram of forming a first conductive unit, a gate insulating layer, and a passivation layer in a peripheral region/Pad region according to an embodiment of the present disclosure
  • FIG. 9B is a schematic diagram of forming a flat film in a peripheral region/Pad region according to an embodiment of the present disclosure.
  • FIG. 9C is a schematic diagram of forming a flat layer of a second thickness in a peripheral region/Pad region according to an embodiment of the present disclosure
  • 9D is a schematic diagram of forming a second via hole in a first via hole in a planar layer corresponding to a second thickness in a gate insulating layer and a passivation layer in a peripheral region/Pad region according to an embodiment of the present disclosure
  • 9E is a schematic diagram of forming a second conductive unit in a peripheral region/Pad region according to an embodiment of the present disclosure.
  • 9F is a schematic diagram of forming a second conductive unit and a driving circuit in a peripheral area/Pad area according to an embodiment of the present disclosure
  • FIG. 10 is a schematic diagram showing a thickness of a second layer of a planarization layer being completely removed and a passivation layer (insulating layer) being etched in a peripheral region/Pad region etching process according to an embodiment of the present disclosure
  • FIG. 11 is a second conductive unit and a first conductive layer in a peripheral/Pad region etching process, in which a second layer of a flat layer is completely removed and a passivation layer (insulating layer) is etched by a portion of the thickness of the first conductive layer according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of a second conductive unit being connected to a first conductive unit through a second via hole when a first conductive unit is disposed between a gate insulating layer and a passivation layer according to an embodiment of the present disclosure
  • FIG. 13 is a schematic diagram of a second conductive unit connected to a first conductive unit through a second via hole when a first conductive unit is disposed between a gate insulating layer and a passivation layer according to an embodiment of the present disclosure.
  • ORG flat sub-pixel for example, RGB
  • the ORG is located above the RGB color resistance.
  • ORG is often used to reduce the load, thereby reducing product power consumption.
  • the array substrate includes a base substrate 101 including a display area 10 and a peripheral area 01.
  • a plurality of gate lines 1021 and a plurality of data lines 1041 are further disposed on the base substrate 101.
  • the plurality of gate lines 1021 are insulated from the plurality of data lines 1041, and the plurality of gate lines 1021 intersect the plurality of data lines 1041 to define a plurality of sub-pixel units 24.
  • the peripheral area 01 is disposed on at least one side of the display area 10.
  • the peripheral area 01 is disposed around the display area 10.
  • the display area 10 is located in the middle of the display substrate.
  • the display area 10 includes a plurality of sub-pixel units arranged in an array, each of the sub-pixel units including a Thin Film Transistor (TFT) 121 as a switching element.
  • the thin film transistor 121 includes, for example, a gate electrode, a gate insulating layer, an active layer, and a source and drain.
  • the peripheral area 01 includes a wiring area (Pad area) 011 and a fan-out area (Fanout area) 012.
  • the first conductive unit 0102 in the wiring area 011 is electrically connected to the connecting line 01020 in the fan-out area 012.
  • the connection line 01020 of the first conductive unit 0102 and the fan-out area 012 may be integrally formed, but is not limited thereto.
  • the first conductive unit 0102 may be connected to an anisotropic conductive paste (not shown) via a via (not shown) via a second conductive unit (for example, ITO or metal, not shown), and then A driving circuit (for example, a COF or an IC, not shown) is connected, and the signal of the driving circuit sequentially enters the display panel through the second conductive unit, the first conductive unit 0102, and the fan-out area 012 connecting line 01020, thereby implementing signal writing.
  • a driving circuit for example, a COF or an IC, not shown
  • the display substrate includes a base substrate 101 and a gate insulating layer (GI) 103, a data line 1041, and a passivation layer (Passivation) which are sequentially disposed on the base substrate 101.
  • the flat layer 108 and the pixel electrode 1091 can be electrically connected to the drain of the TFT.
  • the thickness of the flat layer 108 of the first thickness of the display region 10 is T0. In the embodiment of the present disclosure, the thickness refers to, for example, a height in a direction perpendicular to the substrate.
  • the second conductive unit 0109 is electrically connected to the first conductive unit 0102 through the flat layer via 0133.
  • the planar vias 0133 extend through the gate insulating layer 103, the passivation layer 105, and the planarization layer 108 of the first thickness.
  • the flat layer 108 of the first thickness is a flat layer of initial thickness.
  • the via hole is large (generally larger than 20 ⁇ m), as shown in FIG.
  • the via hole is deep, and the portion of the second conductive unit 0109 located in the via hole cannot be in effective contact with the driving circuit, so that the contact area of the second conductive unit 0109 with the driving circuit is small, the contact resistance is large, and the connectivity is not good.
  • the Pad area 011 is generally designed in the following two ways.
  • PVX Mask a passivation mask
  • the flat film of the Pad region is removed, and a passivation layer mask is used to obtain a via hole for connecting the pad region, and the portion of the pad region 011 is exposed by the via hole through the passivation layer via hole 0134.
  • the passivation layer via 0134 extends through the passivation layer 105 and the gate insulating layer 103, as shown in FIGS. 4 and 6. This design can avoid the oxidation of the wiring of the Pad area 011, but need to add a PVX Mask, the cost increases, and affects the production capacity.
  • the flat film of the entire Pad region is removed, and then the insulating layer (PVX/GI) is etched, and the first conductive unit 0102 of the Pad region is completely exposed, and then directly with the second Conductive units 0109 are connected as shown in Figures 7 and 8. Because there is no insulation layer in the Pad area, the wiring is easy to oxidize and corrode in the environment, which affects the product yield and service life.
  • PVX/GI insulating layer
  • the Pad area design of the product without the flat layer may also be as shown in FIG. 6, the first conductive unit 0102 being connected to the second conductive unit 0109 through the PVX via 0134.
  • the second conductive unit 0109 generally completely covers the portion of the first conductive unit 0102 that is exposed by the via hole, and the first conductive unit 0102 of the Pad region has GI and PVX insulation protection except for the via.
  • GI and PVX film thicknesses are typically in the order of kilo angstroms (eg, film thickness is ), because the insulating layer is thin, the via hole is small (generally less than 10 ⁇ m), and the via hole is shallow, and the second conductive unit 0109 in the via hole can also be in contact with the anisotropic conductive paste, so that the driving circuit can be almost
  • the second conductive unit 0109 of the entire wiring area is in contact with a large contact area, small resistance, and good connectivity.
  • At least one embodiment of the present disclosure provides a method of fabricating a display substrate, including:
  • the base substrate including a display area and a peripheral area;
  • Forming a flat film forming a flat layer of a first thickness in the display region, forming a flat layer of a second thickness in the peripheral region, and forming a first via hole in the flat layer of the second thickness, the second thickness being less than a thickness
  • the peripheral region is etched so that the flat layer of the second thickness is thinned or removed, and a second via corresponding to the first via is formed in the insulating layer.
  • a planarization layer of a first thickness is formed in the display region while a flat layer of a second thickness is formed in the display region, thereby forming a flat layer of a second thickness in the peripheral region.
  • a planarization layer of a first thickness is formed in the display region while a flat layer of a second thickness is formed in the display region, thereby forming a flat layer of a second thickness in the peripheral region.
  • This embodiment provides a method for fabricating a display substrate. As shown in FIG. 1 and FIG. 9A to FIG. 9E, the following steps are included.
  • Step S1 As shown in FIGS. 1 and 9A, a base substrate 101 is provided.
  • the base substrate 101 includes a display area 10 and a peripheral area 01.
  • the peripheral area 01 includes a Pad area 011.
  • the Pad area 011 of the peripheral area 01 is provided.
  • a first conductive unit 0102 is formed on the Pad region 011 of the base substrate 101, and an insulating layer 135 is formed on the first conductive unit 0102.
  • the insulating layer 135 includes a gate insulating layer 103 and a passivation layer 105, and the gate insulating layer 103 is formed.
  • the passivation layer 105 is closer to the base substrate 101.
  • Step S2 As shown in FIG. 9B, a flat film 1080 is formed on the insulating layer 135; the thickness of the flat film 1080 is T0.
  • the material of the flat film 1080 includes, for example, an organic material. In the present embodiment, the material of the flat film 1080 is taken as an organic material as an example.
  • Step S3 as shown in FIG. 9C, a planarization process is performed on the flat film 1080, a flat layer 108 of a first thickness is formed in the display region 10 (see FIG. 3), and a flat layer 0108 having a second thickness is formed in the peripheral region 01. And forming a first via 0131 in the second layer of the flat layer 0108, the second thickness T1 Less than the first thickness T0.
  • the first thickness is the initial thickness of the flat film.
  • Step S4 As shown in FIG. 9D, the peripheral region 01 is etched so that the flat layer 0108 of the second thickness is thinned, and the thickness of the thinned flat layer 01081 is T2, and T2 is smaller than T1. And a second via hole 0132 corresponding to the first via hole 0131 is formed in the insulating layer 135. Since the second via hole 0132 corresponds to the position of the first via hole 0131, the second via hole 0132 penetrates the thinned flat layer 01081 and the insulating layer 135.
  • Step S5 As shown in FIG. 9E, a second conductive unit 0109 is formed in the peripheral region 01, and the second conductive unit is electrically connected to the first conductive unit 0102 through the second via 0132.
  • the same mask may be employed, for example, a multi-tone mask is used to form a flat layer of the first thickness in the display region while forming a flat layer of the second thickness in the peripheral region, thereby Compared with the second method generally adopted to enhance the contact between the driving circuit and the second conductive unit 0109, a mask (PVX mask) can be omitted, the cost is reduced, the productivity is improved, and the method can be beneficial. Reducing the thickness of the flat layer of the Pad region facilitates the connection between the first conductive unit 0102 and the second conductive unit 0109, and facilitates the connection of the second conductive unit 0109 with the driving circuit 151 (shown in FIG. 9F), and the contact area is large. The contact resistance is small and the connectivity is good, thereby facilitating the improvement of product yield and service life.
  • an anisotropic conductive paste 141 including a conductive portion 1411 between the connection electrode 1511 and the second conductive unit 0109 of the drive circuit 151 and a non-conductive portion 1412 located in the remaining region.
  • the manner in which the second conductive unit 0109 is connected to the drive circuit 151 is not limited to that shown in FIG. 9F.
  • the conductive portion 1411 is electrically conductive in a direction perpendicular to the base substrate 101, non-conductive in a direction parallel to the base substrate 101, and the non-conductive portion 1412 is in a direction perpendicular to the base substrate 101 and parallel to the base substrate.
  • the direction of 101 is not conductive.
  • the patterning process includes an exposure process and a development process.
  • the flat film can be exposed using a multi-tone mask.
  • the multi-tone mask may include a halftone mask, and a flat half film may be exposed by a halftone mask while obtaining a flat layer of a first thickness and a flat layer of a second thickness.
  • the vias (including the vias of the display area and the vias of the peripheral area) are all-transmissive areas, and the other areas of the peripheral area except the vias are semi-transmissive areas, except for the display area. Other areas outside the hole are opaque areas.
  • a via hole is formed corresponding to the fully transparent region, corresponding to the semi-transparent
  • the region leaves a flat layer of a second thickness (thin flat layer), and a flat layer of a first thickness is formed corresponding to the opaque region.
  • etching is directly performed.
  • the insulating layer under the first via hole in the flat layer of the second thickness is etched, and the other regions are preserved by the protection of the flat layer having the second thickness.
  • the design can realize the formation of a flat layer with a small thickness above the wiring portion of the Pad region, and it is easy to form a small via hole in the Pad region, and at the same time realize effective protection of the connection of the Pad region, and can enhance the connection between the second conductive unit and the driving circuit.
  • the etching process uses a dry engraving process.
  • the thickness of the flat layer 0108 of the second thickness is less than or equal to the thickness of the insulating layer 135.
  • the material of the flat film 1080 includes an organic material, and the organic material includes, for example, an acrylic resin or a polyimide resin, but the embodiment is not limited thereto.
  • the first conductive unit 0102 may be a metal or a conductive metal oxide
  • the second conductive unit 0109 may be a metal or a conductive metal oxide
  • the conductive metal oxide includes, for example, indium tin oxide (ITO), but the embodiment is not limited thereto. this.
  • the first conductive unit 0102 of the peripheral region 01 may be disposed between the base substrate 101 and the gate insulating layer 103, and may be connected to a gate (not shown) or a gate line 1021 (refer to FIG. 1).
  • the same layer is formed.
  • the insulating layer 135 includes the gate insulating layer 103 and the passivation layer 105, and the gate insulating layer 103 is closer to the base substrate 101 than the passivation layer 105, as shown in FIG. 9E.
  • the gate and gate lines 1021 may also be formed in the same layer.
  • the gate and gate lines 1021 may be integrally formed.
  • the first conductive unit 0102 of the peripheral region 01 may be disposed between the gate insulating layer 103 and the passivation layer 105, and may be connected to a source/drain (not shown) or a data line 1041 (refer to the figure) 1 and Figure 3) are formed in the same layer.
  • the insulating layer 135 includes a passivation layer 105 as shown in FIG.
  • the source/drain and data lines 1041 may also be formed in the same layer.
  • a color filter layer 107 is also formed in the display region 10 (see FIG. 3).
  • the method of fabricating the display substrate includes the following steps.
  • Step S11 A first conductive unit 0102 is formed in the peripheral region 01/Pad region 011 of the base substrate 101, and a gate and a gate line 1021 are formed in the display region 10.
  • the first conductive unit can be formed in the same layer by coating, exposure, development, and etching. 0102, gate and gate line 1021.
  • Step S12 forming the gate insulating layer 103.
  • Step S13 forming an active layer (semiconductor layer) and a source drain in the display region, and an active layer and a source drain are not disposed in the peripheral region/Pad region.
  • Step S14 forming a passivation layer 105 (protective layer, for example, the thickness may be about).
  • Step S15 forming a color film layer (R/G/B film layer) in the display area, and no color film layer is disposed in the peripheral area/Pad area.
  • Step S16 A flat film 1080 is formed on the passivation layer 105, and the thickness of the flat film 1080 is T0.
  • Step S17 The flat film 1080 is exposed by a halftone mask and developed to obtain a flat layer 108 of a first thickness of the display region 10 and a flat layer 0108 of a second thickness of the Pad region 011.
  • the flat film at the via of the display area and the peripheral area is completely exposed, and the area other than the via area of the peripheral area is partially exposed, and the area other than the via area of the display area is not exposed.
  • the flat film at the via is completely removed to form the first via 0131, leaving a thin flat film (flat layer 0108 of the second thickness) at the other semi-transparent, and forming a flat first thickness without being exposed.
  • the passivation layer 105 and the gate insulating layer 103 under the first via 0131 of the Pad region 011 are etched away, and the flat layer 0108 of the second thickness is partially removed by dry etching to obtain a second Via 0132.
  • the formation of a small via hole at the wiring of the Pad region is similar to that of the Pad region of a product in which no flat film is provided.
  • Step S18 using the same patterning process, forming a second conductive unit 0109 in the peripheral area/Pad area, forming a pixel electrode 1091 in the display area, and electrically connecting the second conductive unit 0109 to the first conductive unit 0102 through the second via 0132, the pixel The electrode 1091 is electrically connected to the drain of the TFT through the via.
  • the flat layer 0108 of the second thickness happens to be completely thinned when thinning.
  • the second via 0132 corresponding to the first via 0131 is formed in the insulating layer 135.
  • the second via 0132 penetrates the insulating layer 135, and the second conductive unit 0109 is electrically connected to the first conductive unit 0102 through the second via 0132. connection.
  • the display substrate produced by the manufacturing method provided by the embodiment has the same effect as the Pad region of the product in which the flat film is not provided.
  • the insulating layer Since the insulating layer is dry-etched, it has a damage effect on the flat layer. Therefore, by adjusting the semi-transparency and the dry-cutting parameters, the flat layer of the peripheral region (corresponding to the semi-transmissive region of the mask) has no residue.
  • a cross-sectional view of the formed display substrate can be referred to FIG.
  • step S4 in the method for fabricating the display substrate provided in this embodiment, in step S4, as shown in FIG. 10, during the etching process on the peripheral region 01, the second thickness is thinned during the thinning process.
  • the flat layer 0108 is completely removed, and the passivation layer 105 (insulating layer 135) is removed by a partial thickness, and formed in the passivation layer 0105 (thickness T11, the remaining insulating layer after thinning) whose thickness is thinned.
  • a via 01320 corresponding to the via 0131.
  • the second conductive unit 0109 is electrically connected to the first conductive unit 0102 through the via 01320.
  • the thickness of the insulating layer 105 before being thinned is T00.
  • T11 is smaller than T00.
  • a cross-sectional view of the formed display substrate can be referred to FIG.
  • the first conductive unit 012 is formed between the gate insulating layer 103 and the passivation layer 105, and the second via 0132 is penetrated through the thinned layer.
  • a cross-sectional view of the formed display substrate can be referred to FIG.
  • the first conductive unit 012 is formed between the gate insulating layer 103 and the passivation layer 105, and the second via 0132 is penetrated through the passivation layer 105.
  • the first conductive unit 012 is formed between the gate insulating layer 103 and the passivation layer 105, and the second via 0132 is penetrated through the thinned portion.
  • Passivation layer passivation layer 0105 of the second thickness.
  • a cross-sectional view of the formed display substrate can be referred to FIG.
  • This embodiment provides a display substrate, as shown in FIGS. 1 and 9E, including:
  • Substrate substrate 101 the substrate substrate 101 includes a display area 10 and a peripheral area 01, the peripheral area 01 includes a Pad area 011;
  • the insulating layer 135 is disposed on the base substrate 101;
  • a first via hole 0131 (see FIG. 9C) is provided in the flat layer of the peripheral region, and a second via hole 0132 corresponding to the first via hole 0131 is provided in the insulating layer 135 (refer to FIG. 9D).
  • the display substrate further includes a first conductive unit 0102 and a second conductive unit 0109 disposed in the peripheral region 01, and the first conductive unit 0102 is disposed between the base substrate 101 and the insulating layer 135.
  • the second conductive unit 0109 is disposed on the flat layer of the peripheral region, and the second conductive unit 0109 is electrically connected to the first conductive unit 0102 through the second via 0132.
  • the insulating layer 135 includes a gate insulating layer 103 and a passivation layer 105 which is closer to the base substrate 101 than the passivation layer 105.
  • the display substrate provided in this embodiment can be formed by any of the methods of the first embodiment.
  • the insulating layer 135 includes a passivation layer 105.
  • the display substrate provided by this example can be formed by the method of Embodiment 4.
  • the flat area of the display area in the present embodiment corresponds to the flat layer 108 of the first thickness in the method of fabricating the display substrate
  • the flat area of the peripheral area corresponds to the thinned flat layer 01081 in the method of fabricating the display substrate.
  • the display substrate provided in this embodiment, as shown in FIG. 11, includes:
  • Substrate substrate 101 the substrate substrate 101 includes a display area 10 and a peripheral area 01;
  • a gate insulating layer 103 disposed on the substrate substrate 101;
  • a passivation layer disposed on the gate insulating layer 103, the passivation layer including a passivation layer 105 disposed at a first thickness of the display region 10 and a passivation layer 0105 disposed at a second thickness of the peripheral region 01, a second thickness Less than the first thickness, a via hole 01320 is provided in the gate insulating layer 103 and the passivation layer 0105 of the second thickness.
  • FIG. 11 further comprising a first conductive unit 0102 and a second conductive unit 0109 disposed in the peripheral region 01, the first conductive unit 0102 being disposed between the base substrate 101 and the gate insulating layer 103,
  • the second conductive unit 0109 is disposed on the passivation layer 0105 of the second thickness, the via 01320 penetrates the passivation layer 0105 of the second thickness and the gate insulating layer 103, and the second conductive unit 0109 passes through the via 01320 and the first conductive unit 0102 is electrically connected.
  • the display substrate provided by this example can adopt the embodiment The three methods are formed. In one example, as shown in FIG.
  • the first conductive unit 0102 is disposed between the gate insulating layer 103 and the passivation layer 0105 of the second thickness
  • the second conductive unit 0109 is disposed on the passivation layer 0105 of the second thickness.
  • the via 01320 may be disposed in the passivation layer 0105 of the second thickness.
  • the display substrate provided by this example can be formed by the method of Embodiment 6.
  • This embodiment provides a display device including any of the display substrates described in the above embodiments.
  • the COA array substrate in the TN mode liquid crystal display device is described as an example.
  • the display substrate is not limited to the above description, and the display substrate can also be used in other modes of the liquid crystal display device, and is not limited to the liquid crystal display device. Used in LED display devices.
  • the first conductive unit is connected to the second conductive unit, so that the second conductive unit can be connected to the driving circuit.
  • the first conductive unit 0102 may be disposed in the same layer as the gate, source drain or pixel electrode of the display area, and the second conductive unit 0109 may be connected to the gate, source drain or pixel of the display area.
  • the electrodes are set in the same layer.
  • the common electrode is disposed on the display substrate, one of the first conductive unit 0102 and the second conductive unit 0109 may be disposed in the same layer as the common electrode.
  • “same layer” refers to a layer structure formed by forming a film layer for forming a specific pattern by the same film forming process, and then forming the pattern by one patterning process using the same mask.
  • a patterning process may include multiple exposure, development, or etching processes, and the particular pattern in the resulting layer structure may be continuous or discontinuous, and these particular patterns may also be at different heights. Or have different thicknesses.

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Abstract

提供一种显示基板的制作方法、显示基板和显示装置。该显示基板的制作方法，包括：在衬底基板（101）上形成绝缘层（135），衬底基板（101）包括显示区（10）和周边区（01）；在绝缘层（135）上形成平坦膜（1080）；对平坦膜（1080）进行图案化工艺，在显示区（10）形成第一厚度的平坦层（108），在周边区（01）形成第二厚度的平坦层（0108），且在第二厚度的平坦层（0108）中形成第一过孔（0131），第二厚度小于第一厚度；对周边区（01）进行刻蚀处理，以使第二厚度的平坦层（0108）被减薄或去除，且在绝缘层（135）中形成与第一过孔（0131）对应的第二过孔（0132）。该显示基板的制作方法，利于减小周边区的平坦层的厚度，利于第一导电单元和第二导电单元之间的连接，并利于第二导电单元与驱动电路连接，接触面积大，接触电阻小，连接性好。

Description

显示基板的制作方法、显示基板和显示装置
相关申请的交叉引用
本专利申请要求于2017年3月10日递交的中国专利申请第201710142159.0号的优先权，在此全文引用上述中国专利申请公开的内容以作为本公开的示例的一部分。
技术领域
本公开至少一实施例涉及一种显示基板的制作方法、显示基板和显示装置。
背景技术
在薄膜晶体管液晶显示器(Thin-Film-Transistor Liquid Crystal Display，TFT-LCD)产品中，常采用平坦层(planarization,PLN)来平坦膜层和降低负载。PLN例如包括有机层(Organic layer，ORG)。
发明内容
本公开的至少一实施例涉及一种显示基板的制作方法、显示基板和显示装置，利于减小周边区的平坦层的厚度或去除周边区的平坦层，利于第一导电单元和第二导电单元之间的连接，并利于第二导电单元与驱动电路连接，接触面积大，接触电阻小，连接性好。
本公开的至少一实施例提供一种显示基板的制作方法，包括：
在衬底基板上形成绝缘层，所述衬底基板包括显示区和周边区；
在所述绝缘层上形成平坦膜；
对所述平坦膜进行图案化工艺，在所述显示区形成第一厚度的平坦层，在所述周边区形成第二厚度的平坦层，且在所述第二厚度的平坦层中形成第一过孔，所述第二厚度小于所述第一厚度；
对所述周边区进行刻蚀处理，以使所述第二厚度的平坦层被减薄或去除，且在所述绝缘层中形成与所述第一过孔对应的第二过孔。
本公开的至少一实施例还提供一种显示基板，包括：
衬底基板，所述衬底基板包括显示区和周边区；
绝缘层，设置在所述衬底基板上；
平坦层，设置在所述绝缘层上，所述平坦层包括设置在所述显示区的显示区平坦层和设置在所述周边区的周边区平坦层，所述周边区平坦层的厚度小于所述显示区平坦层的厚度，在所述周边区设有贯穿所述平坦层和所述绝缘层的过孔。
本公开的至少一实施例还提供一种显示基板，包括：
衬底基板，所述衬底基板包括显示区和周边区；
栅极绝缘层，设置在所述衬底基板上；
钝化层，设置在所述栅极绝缘层上，所述钝化层包括设置在所述显示区的第一厚度的钝化层和设置在所述周边区的第二厚度的钝化层，所述第二厚度小于所述第一厚度，在所述栅极绝缘层和所述第二厚度的钝化层中设有过孔，或者，在所述第二厚度的钝化层中设有过孔。
本公开的至少一实施例还提供一种显示装置，包括本公开实施例所述的任一显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种显示基板俯视示意图；
图2为一种显示基板的周边区的接线俯视示意图；
图3为图1沿A-B处的剖视示意图；
图4为一种显示基板的周边区的俯视示意图；
图5为图4沿C-D处的一种剖视示意图；
图6为图4沿C-D处的另一种剖视示意图(本公开一实施例提供的在减薄时恰巧第二厚度的平坦层被完全去除时第二导电单元与第一导电单元连接的示意图)；
图7为一种显示基板的周边区的俯视示意图；
图8为图7沿E-F处的剖视示意图；
图9A为本公开一实施例提供的在周边区/Pad区形成第一导电单元、栅极绝缘层和钝化层的示意图；
图9B为本公开一实施例提供的在周边区/Pad区形成平坦膜的示意图；
图9C为本公开一实施例提供的在周边区/Pad区形成第二厚度的平坦层的示意图；
图9D为本公开一实施例提供的在周边区/Pad区在栅极绝缘层和钝化层中对应第二厚度的平坦层中的第一过孔处形成第二过孔的示意图；
图9E为本公开一实施例提供的在周边区/Pad区形成第二导电单元的示意图；
图9F为本公开一实施例提供的在周边区/Pad区形成第二导电单元与驱动电路连接的示意图；
图10为本公开一实施例提供的在周边区/Pad区刻蚀工艺中第二厚度的平坦层被完全去除并且钝化层(绝缘层)被刻蚀部分厚度的示意图；
图11为本公开一实施例提供的在周边区/Pad区刻蚀工艺中第二厚度的平坦层被完全去除并且钝化层(绝缘层)被刻蚀部分厚度时第二导电单元与第一导电单元连接的示意图；
图12为本公开一实施例提供的第一导电单元设置在栅极绝缘层和钝化层之间时第二导电单元通过第二过孔与第一导电单元连接的示意图；
图13为本公开一实施例提供的第一导电单元设置在栅极绝缘层和钝化层之间时第二导电单元通过第二过孔与第一导电单元连接的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来 区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在彩色滤光片整合于阵列基板(Color filter on Array，COA)的产品中，常采用ORG平坦子像素(例如RGB)色阻段差，ORG位于RGB色阻之上。而在低功耗小尺寸移动产品中常采用ORG降低负载，从而降低产品功耗。
以COA液晶显示面板的阵列基板为例，如图1所示，阵列基板包括衬底基板101，衬底基板101包括显示区10和周边区01。如图1所示，衬底基板101上还设置有多条栅线1021和多条数据线1041。例如，多条栅线1021与多条数据线1041相互绝缘，多条栅线1021与多条数据线1041交叉限定多个子像素单元24。
例如，周边区01设置在显示区10的至少一侧。例如，周边区01围绕显示区10设置。例如，显示区10位于显示基板的中部，例如，显示区10包括按阵列排列的多个子像素单元，每个子像素单元包括薄膜晶体管(Thin Film Transistor，TFT)121作为开关元件。薄膜晶体管121例如包括栅极、栅极绝缘层、有源层和源漏极。
如图2所示，周边区01包括接线区(Pad区)011和扇出区(Fanout区)012，接线区011内的第一导电单元0102与扇出区012内连接线01020电连接。例如，第一导电单元0102与扇出区012的连接线01020可一体形成，但不限于此。第一导电单元0102可通过过孔(图中未示出)经第二导电单元(例如ITO或金属，图中未示出)与各向异性导电胶(图中未示出)相连，再与驱动电路(例如COF或者IC，图中未示出)连接，驱动电路的信号依次经第二导电单元、第一导电单元0102以及扇出区012连接线01020进入显示面板，实现信号写入(可参照图9F)。
如图3所示，在显示区10，显示基板包括衬底基板101和依次设置在衬底基板101上的栅极绝缘层(Gate insulating layer，GI)103、数据线1041、钝化层(Passivation layer，PVX)105、黑矩阵106、彩膜层107、第一厚度 的平坦层108和像素电极1091。像素电极1091可与TFT的漏极电连接。显示区10的第一厚度的平坦层108的厚度为T0。本公开的实施例中，厚度例如是指在垂直于衬底基板的方向上的高度。
图4示出了在周边区，第二导电单元0109通过平坦层过孔0133与第一导电单元0102电连接。如图5所示，平坦层过孔0133贯穿栅极绝缘层103、钝化层105和第一厚度的平坦层108。第一厚度的平坦层108即为初始厚度的平坦层。
对于设置了平坦层的产品，因平坦层很厚(一般大于2μm)，若接线区011的接线采用平坦层过孔0133连接，则过孔很大(一般大于20μm)，如图5所示，同时过孔很深，第二导电单元0109位于过孔内的部分不能与驱动电路有效接触，从而，第二导电单元0109与驱动电路的接触面积小，接触电阻大，连接性不好。
采用平坦层的产品，为了增强驱动电路与第二导电单元0109的接触性，Pad区011通常有以下两种方式设计。
一、使用钝化层掩模(PVX Mask)。平坦膜曝光显影完成后，Pad区的平坦膜被去除，经过一道钝化层掩模，得到Pad区连接接线的过孔，Pad区011的接线被过孔暴露的部分通过钝化层过孔0134与第二导电单元0109相连，钝化层过孔0134贯穿钝化层105和栅极绝缘层103，如图4和图6所示。此种设计可避免Pad区011的接线被氧化腐蚀，但需要增加一道PVX Mask，成本上升，同时影响产能。
二、不使用PVX Mask，平坦膜曝光显影完成后，去除整个Pad区的平坦膜，再进行绝缘层(PVX/GI)刻蚀，Pad区的第一导电单元0102完全裸露，再直接与第二导电单元0109相连，如图7和图8所示。因Pad区无绝缘保护层，接线容易在环境中氧化腐蚀，影响产品良率和使用寿命。
不设置平坦层的产品的Pad区设计也可如图6所示，第一导电单元0102通过PVX过孔0134与第二导电单元0109连接。第二导电单元0109一般完全覆盖第一导电单元0102被过孔暴露的部分，Pad区的第一导电单元0102除过孔外其他区域有GI和PVX绝缘保护。GI和PVX膜厚一般为千埃级别(例如，膜厚为
Figure PCTCN2017104432-appb-000001
)，因绝缘层较薄，所以过孔较小(一般小于10μm)，同时过孔较浅，过孔内的第二导电单元0109也能和各向异性导电胶接触，因 而驱动电路几乎能与整个接线区的第二导电单元0109接触，接触面积大，电阻小，连接性好。
本公开至少一实施例提供一种显示基板的制作方法，包括：
在衬底基板上形成绝缘层，衬底基板包括显示区和周边区；
在绝缘层上形成平坦膜；
对平坦膜进行图案化工艺，在显示区形成第一厚度的平坦层，在周边区形成第二厚度的平坦层，且在第二厚度的平坦层中形成第一过孔，第二厚度小于第一厚度；
对周边区进行刻蚀处理，以使第二厚度的平坦层被减薄或去除，且在绝缘层中形成与第一过孔对应的第二过孔。
本公开至少一实施例提供的显示基板的制作方法，在对平坦膜进行图案化工艺时，在显示区形成第一厚度的平坦层的同时，在周边区形成第二厚度的平坦层，从而，利于减小周边区(例如，Pad区)平坦层的厚度或去除周边区(例如，Pad区)平坦层，利于第一导电单元和第二导电单元之间的连接，并利于第二导电单元与驱动电路连接，接触面积大，接触电阻小，连接性好。
实施例一
本实施例提供一种显示基板的制作方法，如图1、图9A-图9E所示，包括如下步骤。
步骤S1：如图1和9A所示，提供衬底基板101，衬底基板101包括显示区10和周边区01，周边区01包括Pad区011，本实施例以周边区01的Pad区011为例进行说明。在衬底基板101的Pad区011上形成第一导电单元0102，在第一导电单元0102上形成绝缘层135，绝缘层135包括栅极绝缘层103和钝化层105，栅极绝缘层103比钝化层105更靠近衬底基板101。
步骤S2：如图9B所示，在绝缘层135上形成平坦膜1080；平坦膜1080的厚度为T0。平坦膜1080的材料例如包括有机材料。本实施例中以平坦膜1080的材料为有机材料为例进行说明。
步骤S3：如图9C所示，对平坦膜1080进行图案化工艺，在显示区10形成第一厚度的平坦层108(可参见图3)，在周边区01形成第二厚度的平坦层0108，且在第二厚度的平坦层0108中形成第一过孔0131，第二厚度T1 小于第一厚度T0。例如，第一厚度即平坦膜的初始厚度。
步骤S4：如图9D所示，对周边区01进行刻蚀处理，以使第二厚度的平坦层0108被减薄，被减薄后的平坦层01081的厚度为T2，T2小于T1。且在绝缘层135中形成与第一过孔0131对应的第二过孔0132。因第二过孔0132与第一过孔0131位置对应，第二过孔0132贯穿被减薄后的平坦层01081和绝缘层135。
步骤S5：如图9E所示，在周边区01形成第二导电单元0109，第二导电单元通过第二过孔0132与第一导电单元0102电连接。
在对平坦膜进行图案化工艺时，可采用同一张掩模板，例如采用多色调掩模板，以在显示区形成第一厚度的平坦层的同时，在周边区形成第二厚度的平坦层，从而，与上述通常的为了增强驱动电路与第二导电单元0109的接触性而采取的第二种方式相比，可省去一张掩模板(PVX掩模板)，降低成本，提升产能，并可利于减小Pad区平坦层的厚度，利于第一导电单元0102和第二导电单元0109之间的连接，并利于第二导电单元0109与驱动电路151(如图9F所示)连接，接触面积大，接触电阻小，连接性好，从而，利于提高产品良率和使用寿命。
图9F中还示出了各向异性导电胶141，各向异性导电胶141包括位于驱动电路151的连接电极1511和第二导电单元0109之间的导电部分1411和位于其余区域的不导电部分1412。第二导电单元0109与驱动电路151的连接方式不限于图9F所示。例如，导电部分1411在垂直于衬底基板101的方向上导电，在平行于衬底基板101的方向上不导电，不导电部分1412在垂直于衬底基板101的方向上和平行于衬底基板101的方向上均不导电。
一个示例中，图案化工艺包括曝光工艺和显影工艺，为了节省掩模板的数量，可采用多色调掩模板对平坦膜进行曝光。
例如，多色调掩模板可以包括半色调掩模板，可以采用一张半色调掩模板，对平坦膜进行曝光，同时得到第一厚度的平坦层和第二厚度的平坦层。半色调掩模板中，过孔处(包括显示区的过孔和周边区的过孔)为全透光区域，周边区的除了过孔外的其他区域为半透光区域，显示区的除了过孔外的其他区域为不透光区域。
例如，平坦膜经曝光、显影后，对应全透光区域形成过孔，对应半透光 区域留下第二厚度的平坦层(薄层平坦层)，对应不透光区域形成第一厚度的平坦层。然后直接进行刻蚀，在周边区，第二厚度的平坦层中的第一过孔下方的绝缘层被刻蚀，而其他区域因有第二厚度的平坦层的保护，绝缘层被保留下来。此设计可实现Pad区接线处上方形成厚度较小的平坦层，易于在Pad区形成小的过孔，同时实现Pad区接线的有效保护，可增强第二导电单元与驱动电路的连接性，在省去一张PVX掩模板的同时确保产品良率和使用寿命。一个示例中，刻蚀处理采用干刻工艺。
例如，为了在步骤S4的刻蚀处理中，部分减薄第二厚度的平坦层0108或去除第二厚度的平坦层0108，第二厚度的平坦层0108的厚度小于或等于绝缘层135的厚度。
例如，平坦膜1080的材质包括有机材料，有机材料例如包括亚克力树脂或聚酰亚胺树脂，但本实施例并不限于此。
例如，第一导电单元0102可采用金属或导电金属氧化物，第二导电单元0109可采用金属或导电金属氧化物，导电金属氧化物例如包括氧化铟锡(ITO)，但本实施例并不限于此。
一个示例中，周边区01的第一导电单元0102可以设置在衬底基板101和栅极绝缘层103之间，可以与栅极(图中未示出)或栅线1021(可参照图1)同层形成。此情况下，绝缘层135包括栅极绝缘层103和钝化层105，栅极绝缘层103比钝化层105更靠近衬底基板101，如图9E所示。例如，栅极和栅线1021也可同层形成。例如，栅极和栅线1021可一体形成。
一个示例中，周边区01的第一导电单元0102可以设置在栅极绝缘层103和钝化层105之间，可以与源/漏极(图中未示出)或数据线1041(可参照图1和图3)同层形成。此情况下，绝缘层135包括钝化层105，如图12所示。例如，源/漏极和数据线1041也可同层形成。
一个示例中，在形成平坦膜1080之前，还包括在显示区10形成彩色滤光层107(可参见图3)。
一个示例中，显示基板的制作方法包括如下步骤。
步骤S11：在衬底基板101的周边区01/Pad区011形成第一导电单元0102，在显示区10形成栅极和栅线1021。
例如，可以通过镀膜、曝光、显影和刻蚀的方法同层形成第一导电单元 0102、栅极和栅线1021。
步骤S12：形成栅极绝缘层103。
步骤S13：在显示区形成有源层(半导体层)、源漏极，周边区/Pad区不设置有源层和源漏极。
步骤S14：形成钝化层105(保护层，例如，厚度可以在
Figure PCTCN2017104432-appb-000002
左右)。
步骤S15：在显示区形成彩膜层(R/G/B膜层)，周边区/Pad区不设置彩膜层。
步骤S16：在钝化层105上形成平坦膜1080，平坦膜1080的厚度为T0。
步骤S17：采用半色调掩模板对平坦膜1080进行曝光，并显影，得到显示区10的第一厚度的平坦层108和Pad区011的第二厚度的平坦层0108。
曝光后，显示区和周边区的过孔处的平坦膜被全部曝光，周边区除了过孔外的其它区域被部分曝光，显示区除了过孔外的其它区域不被曝光。
经显影，过孔处的平坦膜被完全去除，形成第一过孔0131，其它半透处留下薄层平坦膜(第二厚度的平坦层0108)，没被曝光处形成第一厚度的平坦层108。
经干刻工艺，Pad区011的第一过孔0131下方的钝化层105和栅极绝缘层103被刻蚀掉，同时第二厚度的平坦层0108经干刻损伤被部分去除，得到第二过孔0132。最终实现Pad区接线处小过孔的形成，与不设置平坦膜的产品的Pad区效果类似。
步骤S18：采用同一构图工艺，在周边区/Pad区形成第二导电单元0109，在显示区形成像素电极1091，第二导电单元0109通过第二过孔0132与第一导电单元0102电连接，像素电极1091通过过孔与TFT的漏极电连接。
上述示例以形成COA阵列基板为例进行说明，但本实施例不限于此。
实施例二
与实施例一不同的是，本实施例提供的显示基板的制作方法，在步骤S4中，对周边区01进行刻蚀处理的过程中，在减薄时恰巧第二厚度的平坦层0108被完全去除，在绝缘层135中形成与第一过孔0131对应的第二过孔0132，第二过孔0132贯穿绝缘层135，第二导电单元0109通过第二过孔0132与第一导电单元0102电连接。本实施例提供的制作方法制作的显示基板，与不设置平坦膜的产品的Pad区效果一致。
因绝缘层采用干刻工艺，对平坦层有损伤作用，因而可通过调整半透率以及干刻参数，实现周边区的平坦层(对应掩模板的半透光区域)无残留。
形成的显示基板的剖视图可参照图6所示。
实施例三
与实施例一不同的是，本实施例提供的显示基板的制作方法，在步骤S4中，如图10所示，对周边区01进行刻蚀处理的过程中，在减薄时第二厚度的平坦层0108被完全去除，并且，钝化层105(绝缘层135)被去除部分厚度，在厚度被减薄的钝化层0105(厚度为T11，减薄后余下的绝缘层)中形成与第一过孔0131对应的过孔01320。如图11所示，第二导电单元0109通过过孔01320与第一导电单元0102电连接。如图6和图9A所示，绝缘层105在未减薄前的厚度为T00。T11小于T00。
形成的显示基板的剖视图可参照图11所示。
实施例四
与实施例一不同的是，本实施例提供的显示基板的制作方法，第一导电单元012形成在栅极绝缘层103和钝化层105之间，第二过孔0132贯穿被减薄后的平坦层01081和钝化层105。形成的显示基板的剖视图可参照图12所示。
实施例五
与实施例二不同的是，本实施例提供的显示基板的制作方法，第一导电单元012形成在栅极绝缘层103和钝化层105之间，第二过孔0132贯穿钝化层105。
实施例六
与实施例三不同的是，本实施例提供的显示基板的制作方法，第一导电单元012形成在栅极绝缘层103和钝化层105之间，第二过孔0132贯穿被减薄后的钝化层(第二厚度的钝化层0105)。形成的显示基板的剖视图可参照图13所示。
实施例七
本实施例提供一种显示基板，如图1和9E所示，包括：
衬底基板101，衬底基板101包括显示区10和周边区01，周边区01包括Pad区011；
绝缘层135，设置在衬底基板101上；
平坦层，设置在绝缘层135上，平坦层包括设置在显示区10的显示区平坦层和设置在周边区01的周边区平坦层，周边区平坦层的厚度小于显示区平坦层的厚度，在周边区平坦层中设有第一过孔0131(参照图9C)，在绝缘层135中设有与第一过孔0131对应的第二过孔0132(参照图9D)。
一个示例中，如图9E所示，该显示基板还包括设置在周边区01的第一导电单元0102和第二导电单元0109，第一导电单元0102设置在衬底基板101和绝缘层135之间，第二导电单元0109设置在周边区平坦层上，第二导电单元0109通过第二过孔0132与第一导电单元0102电连接。例如，绝缘层135包括栅极绝缘层103和钝化层105，栅极绝缘层103比钝化层105更靠近衬底基板101。
例如，本实施例提供的显示基板可采用实施例一的任一方法形成。
另一个示例中，如图12所示，绝缘层135包括钝化层105。该示例提供的显示基板可采用实施例四的方法形成。
例如，本实施例中的显示区平坦层对应于前述显示基板制作方法中的第一厚度的平坦层108，周边区平坦层对应于前述显示基板制作方法中的被减薄后的平坦层01081。
实施例八
本实施例提供的显示基板，如图11所示，包括：
衬底基板101，衬底基板101包括显示区10和周边区01；
栅极绝缘层103，设置在衬底基板101上；
钝化层，设置在栅极绝缘层103上，钝化层包括设置在显示区10的第一厚度的钝化层105和设置在周边区01的第二厚度的钝化层0105，第二厚度小于第一厚度，在栅极绝缘层103和第二厚度的钝化层0105中设有过孔01320。
一个示例中，如图11所示，还包括设置在周边区01的第一导电单元0102和第二导电单元0109，第一导电单元0102设置在衬底基板101和栅极绝缘层103之间，第二导电单元0109设置在第二厚度的钝化层0105上，过孔01320贯穿第二厚度的钝化层0105和栅极绝缘层103，第二导电单元0109通过过孔01320与第一导电单元0102电连接。该示例提供的显示基板可采用实施例 三的方法形成。一个示例中，如图13所示，第一导电单元0102设置在栅极绝缘层103和第二厚度的钝化层0105之间，第二导电单元0109设置在第二厚度的钝化层0105上，过孔01320可以设在第二厚度的钝化层0105中。该示例提供的显示基板可采用实施例六的方法形成。
实施例九
本实施例提供显示装置，包括上述实施例所述的任一显示基板。
以上以TN模式的液晶显示装置中的COA阵列基板为例进行说明，但并不限于上述描述，显示基板还可以用于其他模式的液晶显示装置中，而且，并不限于液晶显示装置，还可以用于发光二极管显示装置中。只要是能减小Pad区的平坦层或绝缘层(例如钝化层)的厚度，利于第一导电单元与第二导电单元连接，从而利于第二导电单元与驱动电路连接即可。
例如，本公开的实施例中，第一导电单元0102可与显示区的栅极、源漏极或像素电极同层设置，第二导电单元0109可与显示区的栅极、源漏极或像素电极同层设置。当显示基板上设置公共电极时，第一导电单元0102和第二导电单元0109之一可以与公共电极同层设置。
这里应该理解的是，在本公开的实施例中，“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。
有以下几点需要说明：
(1)除非另作定义，本公开实施例以及附图中，同一附图标记代表同一含义。
(2)本公开实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(3)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(4)在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可 以相互组合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种显示基板的制作方法，包括：
    在衬底基板上形成绝缘层，所述衬底基板包括显示区和周边区；
    在所述绝缘层上形成平坦膜；
    对所述平坦膜进行图案化工艺，在所述显示区形成第一厚度的平坦层，在所述周边区形成第二厚度的平坦层，且在所述第二厚度的平坦层中形成第一过孔，所述第二厚度小于所述第一厚度；
    对所述周边区进行刻蚀处理，以使所述第二厚度的平坦层被减薄或去除，且在所述绝缘层中形成与所述第一过孔对应的第二过孔。
  2. 根据权利要求1所述的显示基板的制作方法，其中，所述第二厚度的平坦层小于或等于所述绝缘层的厚度。
  3. 根据权利要求1或2所述的显示基板的制作方法，其中，在所述衬底基板上形成所述绝缘层之前，还包括在所述周边区形成第一导电单元。
  4. 根据权利要求3所述的显示基板的制作方法，其中，在形成所述第二过孔后，还包括在所述周边区形成第二导电单元，所述第二导电单元通过所述第二过孔与所述第一导电单元电连接。
  5. 根据权利要求4所述的显示基板的制作方法，其中，在减薄时所述第二厚度的平坦层被完全去除，并且，所述绝缘层被去除部分厚度，在余下的所述绝缘层中形成与所述第一过孔对应的第二过孔。
  6. 根据权利要求1-5任一项所述的显示基板的制作方法，其中，所述绝缘层包括钝化层，或者，所述绝缘层包括栅极绝缘层和钝化层，其中，所述栅极绝缘层比所述钝化层更靠近所述衬底基板。
  7. 根据权利要求1-5任一项所述的显示基板的制作方法，其中，所述图案化工艺包括曝光工艺和显影工艺，采用多色调掩模板对所述平坦膜进行曝光。
  8. 根据权利要求1-5任一项所述的显示基板的制作方法，在形成所述平坦膜之前，还包括在所述显示区形成彩色滤光层。
  9. 一种显示基板，包括：
    衬底基板，所述衬底基板包括显示区和周边区；
    绝缘层，设置在所述衬底基板上；
    平坦层，设置在所述绝缘层上，所述平坦层包括设置在所述显示区的显示区平坦层和设置在所述周边区的周边区平坦层，所述周边区平坦层的厚度小于所述显示区平坦层的厚度，在所述周边区设有贯穿所述周边区平坦层和所述绝缘层的过孔。
  10. 根据权利要求9所述的显示基板，还包括设置在所述周边区的第一导电单元和第二导电单元，所述第一导电单元设置在所述衬底基板和所述绝缘层之间，所述第二导电单元设置在所述平坦层上，所述第一导电单元和所述第二导电单元通过所述过孔电连接。
  11. 根据权利要求10或11所述的显示基板，其中，所述绝缘层包括钝化层，或者，所述绝缘层包括栅极绝缘层和钝化层，其中，所述栅极绝缘层比所述钝化层更靠近所述衬底基板。
  12. 一种显示基板，包括：
    衬底基板，所述衬底基板包括显示区和周边区；
    栅极绝缘层，设置在所述衬底基板上；
    钝化层，设置在所述栅极绝缘层上，所述钝化层包括设置在所述显示区的第一厚度的钝化层和设置在所述周边区的第二厚度的钝化层，所述第二厚度小于所述第一厚度，在所述栅极绝缘层和所述第二厚度的钝化层中设有过孔，或者，在所述第二厚度的钝化层中设有过孔。
  13. 根据权利要求12所述的显示基板，还包括设置在所述周边区的第一导电单元和第二导电单元，所述第一导电单元设置在所述衬底基板和所述栅极绝缘层之间或者设置在所述栅极绝缘层和所述钝化层之间，所述第二导电单元设置在所述钝化层上，所述第一导电单元和所述第二导电单元通过所述过孔电连接。
  14. 一种显示装置，包括权利要求9-11任一项所述的显示基板。
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