IT201700087309A1 - Dispositivo elettronico integrato con regione di redistribuzione e elevata resistenza agli stress meccanici - Google Patents

Dispositivo elettronico integrato con regione di redistribuzione e elevata resistenza agli stress meccanici

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Publication number
IT201700087309A1
IT201700087309A1 IT102017000087309A IT201700087309A IT201700087309A1 IT 201700087309 A1 IT201700087309 A1 IT 201700087309A1 IT 102017000087309 A IT102017000087309 A IT 102017000087309A IT 201700087309 A IT201700087309 A IT 201700087309A IT 201700087309 A1 IT201700087309 A1 IT 201700087309A1
Authority
IT
Italy
Prior art keywords
redistribution
electronic device
high resistance
mechanical stress
integrated electronic
Prior art date
Application number
IT102017000087309A
Other languages
English (en)
Inventor
Ivan Venegoni
Francesca Milanesi
Francesco Maria Pipia
Samuele Sciarrillo
Paolo Colpani
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT102017000087309A priority Critical patent/IT201700087309A1/it
Priority to US16/044,190 priority patent/US20190035728A1/en
Publication of IT201700087309A1 publication Critical patent/IT201700087309A1/it

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US11289426B2 (en) * 2018-06-15 2022-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US11088068B2 (en) * 2019-04-29 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of manufacturing the same
KR20210046429A (ko) 2019-10-18 2021-04-28 삼성전자주식회사 재배선 기판 및 이를 포함하는 반도체 패키지
US11715756B2 (en) * 2021-04-09 2023-08-01 Taiwan Semiconductor Manufacturing Company, Ltd. Device structure and methods of forming the same
CN113380650A (zh) * 2021-08-12 2021-09-10 颀中科技(苏州)有限公司 一种金属凸块的制造方法及金属凸块结构
IT202100031340A1 (it) * 2021-12-14 2023-06-14 St Microelectronics Srl Metodo di fabbricazione di uno strato di ridistribuzione, strato di ridistribuzione, circuito integrato, e metodi per il test elettrico e la protezione del circuito integrato

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5946590A (en) * 1996-12-10 1999-08-31 Citizen Watch Co., Ltd. Method for making bumps
US20040166661A1 (en) * 2003-02-21 2004-08-26 Aptos Corporation Method for forming copper bump antioxidation surface
US20090152100A1 (en) * 2007-12-14 2009-06-18 Ami Semiconductor, Inc. Thick metal interconnect with metal pad caps at selective sites and process for making the same
US20100109159A1 (en) * 2008-11-03 2010-05-06 Chih-Wen Ho Bumped chip with displacement of gold bumps
US20120007231A1 (en) * 2010-07-08 2012-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming cu pillar capped by barrier layer
US8530344B1 (en) * 2012-03-22 2013-09-10 Chipbond Technology Corporation Method for manufacturing fine-pitch bumps and structure thereof
US20140299990A1 (en) * 2013-04-04 2014-10-09 Rohm Co., Ltd. Semiconductor device
US20140327133A1 (en) * 2013-05-06 2014-11-06 Himax Technologies Limited Metal bump structure for use in driver ic and method for forming the same
CN206293434U (zh) * 2016-02-01 2017-06-30 意法半导体股份有限公司 半导体器件

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3968554B2 (ja) * 2000-05-01 2007-08-29 セイコーエプソン株式会社 バンプの形成方法及び半導体装置の製造方法
JP4327657B2 (ja) * 2004-05-20 2009-09-09 Necエレクトロニクス株式会社 半導体装置
EP3220410A4 (en) * 2014-11-13 2018-07-18 Renesas Electronics Corporation Semiconductor device and manufacturing method for same

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5946590A (en) * 1996-12-10 1999-08-31 Citizen Watch Co., Ltd. Method for making bumps
US20040166661A1 (en) * 2003-02-21 2004-08-26 Aptos Corporation Method for forming copper bump antioxidation surface
US20090152100A1 (en) * 2007-12-14 2009-06-18 Ami Semiconductor, Inc. Thick metal interconnect with metal pad caps at selective sites and process for making the same
US20100109159A1 (en) * 2008-11-03 2010-05-06 Chih-Wen Ho Bumped chip with displacement of gold bumps
US20120007231A1 (en) * 2010-07-08 2012-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming cu pillar capped by barrier layer
US8530344B1 (en) * 2012-03-22 2013-09-10 Chipbond Technology Corporation Method for manufacturing fine-pitch bumps and structure thereof
US20140299990A1 (en) * 2013-04-04 2014-10-09 Rohm Co., Ltd. Semiconductor device
US20140327133A1 (en) * 2013-05-06 2014-11-06 Himax Technologies Limited Metal bump structure for use in driver ic and method for forming the same
CN206293434U (zh) * 2016-02-01 2017-06-30 意法半导体股份有限公司 半导体器件
US20170221840A1 (en) * 2016-02-01 2017-08-03 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices and corresponding device

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