JP6100480B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP6100480B2 JP6100480B2 JP2012158667A JP2012158667A JP6100480B2 JP 6100480 B2 JP6100480 B2 JP 6100480B2 JP 2012158667 A JP2012158667 A JP 2012158667A JP 2012158667 A JP2012158667 A JP 2012158667A JP 6100480 B2 JP6100480 B2 JP 6100480B2
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- film
- semiconductor device
- electrode pad
- bonding wire
- bonding
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Description
C1、C2 Cu膜
CP 半導体チップ
CPa 半導体チップ
DP ダイパッド
LD リード
M1 電極パッド
MP ポリイミド層
MO モールド
N1〜N3 Ni膜
P1 Pd膜
PG ICパッケージ
PR1、PR2 フォトレジスト膜
PV パッシベーション膜
S1 第1シード膜
S2 第2シード膜
SB 半導体基板
SE シード膜
W1 再配線層
W2 再配線層
WP 電極パッド
Claims (9)
- 半導体基板と、
前記半導体基板上に形成された第1配線と、
前記半導体基板および前記第1配線の上に形成され、前記第1配線の上面の一部を露出する開口を有する絶縁膜と、
前記開口において、前記第1配線に接続し、前記絶縁膜上に延在する第2配線と、
前記第2配線に接続しているボンディングワイヤと、
を有し、
前記第2配線は、前記第1配線側から順にCu膜、Ni膜およびPd膜を積層した積層構造を有し、
前記ボンディングワイヤは、前記Pd膜に直接接続されており、その接続部は、平面視において、前記開口の外側であって、前記絶縁膜と重なる箇所に位置しており、
前記Pd膜は前記Ni膜よりも膜厚が小さく、
前記ボンディングワイヤはCuを含む、半導体装置。 - 前記接続部は、平面視において前記第1配線の外側に位置する、請求項1記載の半導体装置。
- 前記絶縁膜は、ポリイミド膜を含み、前記接続部は、前記ポリイミド膜上に位置している、請求項1記載の半導体装置。
- 前記Cu膜、前記Ni膜および前記Pd膜は、平面視において同一のパターン形状を有している、請求項1記載の半導体装置。
- 前記Ni膜は前記Cu膜よりも膜厚が小さい、請求項1記載の半導体装置。
- 前記半導体装置は樹脂により封止されている、請求項1記載の半導体装置。
- (a)電極パッドが上面に露出している半導体基板を用意する工程と、
(b)前記半導体基板上に、前記電極パッドの一部を露出する第1開口を有する絶縁膜を形成する工程と、
(c)前記絶縁膜上に前記電極パッドの上面に接するシード膜を形成する工程と、
(d)前記電極パッド上および前記絶縁膜上の前記シード膜を露出する第2開口を有するレジストパターンを、前記シード膜上に形成する工程と、
(e)前記第2開口内の前記シード膜上に、めっき法を用いてCu膜、Ni膜およびPd膜を順に連続して形成する工程と、
(f)前記(e)工程の後、前記レジストパターンを除去する工程と、
(g)前記Pd膜の上面に、ボンディングワイヤを直接接続する工程と、
を有し、
前記ボンディングワイヤと前記Pd膜との接続部は、平面視において、前記第1開口の外側であって、前記絶縁膜と重なる箇所に位置しており、
前記Pd膜は前記Ni膜よりも膜厚が小さく、
前記ボンディングワイヤはCuを含む、半導体装置の製造方法。 - 前記Cu膜、前記Ni膜および前記Pd膜は、平面視において同一のパターン形状を有している、請求項7記載の半導体装置の製造方法。
- 前記Ni膜は前記Cu膜よりも膜厚が小さい、請求項7記載の半導体装置の製造方法。
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US13/924,938 US9343395B2 (en) | 2012-07-17 | 2013-06-24 | Semiconductor device and manufacturing method of same |
US15/139,825 US9704805B2 (en) | 2012-07-17 | 2016-04-27 | Semiconductor device and manufacturing method of same |
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JP6238121B2 (ja) * | 2013-10-01 | 2017-11-29 | ローム株式会社 | 半導体装置 |
JP6377981B2 (ja) * | 2014-07-11 | 2018-08-22 | ローム株式会社 | 電子装置 |
CN105793964A (zh) * | 2014-11-13 | 2016-07-20 | 瑞萨电子株式会社 | 半导体器件及其制造方法 |
JP6522980B2 (ja) * | 2015-02-18 | 2019-05-29 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP6548187B2 (ja) * | 2015-05-26 | 2019-07-24 | ローム株式会社 | 半導体装置 |
JP2017045865A (ja) | 2015-08-26 | 2017-03-02 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US10453816B2 (en) | 2016-09-28 | 2019-10-22 | Rohm Co., Ltd. | Semiconductor device |
JP2018061018A (ja) * | 2016-09-28 | 2018-04-12 | ローム株式会社 | 半導体装置 |
IT201700061101A1 (it) * | 2017-06-05 | 2018-12-05 | St Microelectronics Srl | Dispositivo a semiconduttore e corrispondente metodo di fabbricazione di dispositivi a semiconduttore |
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US6828660B2 (en) * | 2003-01-17 | 2004-12-07 | Texas Instruments Incorporated | Semiconductor device with double nickel-plated leadframe |
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