JP7245037B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7245037B2 JP7245037B2 JP2018224608A JP2018224608A JP7245037B2 JP 7245037 B2 JP7245037 B2 JP 7245037B2 JP 2018224608 A JP2018224608 A JP 2018224608A JP 2018224608 A JP2018224608 A JP 2018224608A JP 7245037 B2 JP7245037 B2 JP 7245037B2
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
Description
図1~図10に基づき、本発明の第1実施形態にかかる半導体装置A10について説明する。半導体装置A10は、基板11、複数の第1配線12、複数の第2配線13および受動素子41を備える。これらに加え、半導体装置A10は、複数の第1接合層14、保護膜15、複数の端子16、第1封止樹脂31、一対の再配線32、一対の第2接合層33および第2封止樹脂42をさらに備える。これらの図が示す半導体装置A10は、様々な電子機器の配線基板に表面実装される樹脂パッケージ形式によるものである。半導体装置A10が示す例においては、半導体装置A10は、抵抗器およびコンデンサとともにDC/DCコンバータの回路を構成する。ここで、図1は、理解の便宜上、第2封止樹脂42を透過し、かつ透過した第2封止樹脂42を想像線(二点鎖線)で示している。図2は、理解の便宜上、図1に対して一対の第2接合層33、および受動素子41を透過している。図3は、理解の便宜上、半導体素子20、第1封止樹脂31および一対の再配線32を透過し、かつ透過した半導体素子20を想像線で示している。
図28~図32に基づき、本発明の第2実施形態にかかる半導体装置A20について説明する。これらの図において、先述した半導体装置A10と同一または類似の要素には同一の符号を付して、重複する説明を省略する。ここで、図29の断面位置は、先述した半導体装置A10の図7の断面位置と同一である。図30の断面位置は、先述した半導体装置A10の図8の断面位置と同一である。
11:基板
11A:主面
11B:裏面
11C:端面
12:第1配線
12A:下地層
12B:めっき層
121:第1埋込部
121A:第1底面
122:搭載部
13:第2配線
13A:下地層
13B:めっき層
131:第2埋込部
131A:第2底面
132:柱状部
132A:頂面
14:第1接合層
15:保護膜
151:開口
16:端子
161:基部
162:バンプ部
20:半導体素子
20A:素子表面
20B:素子裏面
21:電極
31:第1封止樹脂
31A:外面
31B:内面
31C:側面
32:再配線
32A:下地層
32B:めっき層
33:第2接合層
41:受動素子
411:電極
42:第2封止樹脂
81:基材
811:穴
821:第1下地層
822:第2下地層
831:第1配線層
832:第2配線層
833:第3配線層
834:第4配線層
84:封止樹脂
85:保護膜
851:開口
89:マスク層
891:開口
CL:切断線
z:厚さ方向
x:第1方向
y:第2方向
Claims (11)
- 厚さ方向において互いに反対側を向く主面および裏面を有する基板と、
前記基板に埋め込まれ、かつ前記主面および前記裏面の双方から露出する第1埋込部、および前記主面に接し、かつ前記第1埋込部につながる搭載部を各々が有する複数の第1配線と、
前記主面に対向する素子裏面、および前記素子裏面に設けられた複数の電極を有するとともに、前記複数の電極の各々が前記複数の第1配線の各々の前記搭載部のいずれかに接合された半導体素子と、
前記基板に埋め込まれ、かつ前記主面および前記裏面の双方から露出する第2埋込部、および前記第2埋込部から前記厚さ方向において前記主面が向く側に突出する柱状部を各々が有するとともに、前記厚さ方向に視て前記半導体素子よりも外方に位置する複数の第2配線と、
前記半導体素子よりも前記厚さ方向において前記主面が向く側に位置し、かつ前記複数の第2配線に導通する受動素子と、
前記基板、前記複数の第1配線、前記半導体素子、および前記複数の第2配線のそれぞれ一部ずつを覆う第1封止樹脂と、
前記受動素子を覆う第2封止樹脂と、を備え、
前記厚さ方向に視て、前記受動素子が前記半導体素子に重なっており、
前記受動素子は、前記複数の第2配線の各々の前記柱状部に支持されており、
前記半導体素子は、前記素子裏面とは反対側を向く素子表面を有し、
前記複数の第2配線の各々の前記柱状部は、前記厚さ方向において前記主面と同じ側を向く頂面を有し、
前記第1封止樹脂は、前記厚さ方向において前記主面と同じ側を向く外面と、前記厚さ方向に対して直交する方向を向く第1側面と、を有し
前記第2封止樹脂は、前記厚さ方向に対して直交する方向において前記第1側面と同じ側を向き、かつ前記厚さ方向を面内方向とする第2側面を有し、
前記素子表面および前記頂面の各々は、前記外面と面一であり、
前記第2封止樹脂は、前記外面に接し、かつ前記素子表面を覆っており、
前記厚さ方向に視て、前記第2側面は、前記第1側面よりも前記受動素子が位置する側に離れている、半導体装置。 - 前記受動素子は、インダクタである、請求項1に記載の半導体装置。
- 前記基板は、真性半導体材料からなる、請求項1または2に記載の半導体装置。
- 前記複数の第2配線は、前記厚さ方向に対して直交する第1方向の両側に位置する、請求項1ないし3のいずれかに記載の半導体装置。
- 前記複数の第2配線は、前記厚さ方向および前記第1方向の双方に対して直交する第2方向に沿って配列されている、請求項4に記載の半導体装置。
- 前記第1方向において互いに離れた一対の再配線をさらに備え、
前記一対の再配線の各々は、前記外面と、前記複数の第2配線の各々の前記頂面のいずれかと、に接しており、
前記受動素子は、前記一対の再配線に接合されている、請求項4または5に記載の半導体装置。 - 前記基板は、前記主面および前記裏面につながり、かつ前記厚さ方向に対して直交する方向において前記第1側面と同じ側を向く端面を有し、
前記端面は、前記第1側面と面一である、請求項1ないし6のいずれかに記載の半導体装置。 - 前記複数の第1埋込部の各々は、前記厚さ方向において前記裏面と同じ側を向く第1底面を有し、
前記複数の第2埋込部の各々は、前記厚さ方向において前記裏面と同じ側を向く第2底面を有し、
前記第1底面および前記第2底面の各々は、前記裏面と面一である、請求項1ないし7のいずれかに記載の半導体装置。 - 前記裏面を覆う保護膜をさらに備える、請求項8に記載の半導体装置。
- 複数の端子をさらに備え、
前記複数の端子の各々は、前記第1底面および前記第2底面のいずれかに接している、請求項8または9に記載の半導体装置。 - 前記複数の端子の各々は、前記第1底面および前記第2底面のいずれかに接する基部と、前記基部から前記厚さ方向に突出するバンプ部と、を有し、
前記基部は、金を含み、
前記バンプ部は、錫を含む、請求項10に記載の半導体装置。
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