JP7012489B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7012489B2 JP7012489B2 JP2017174084A JP2017174084A JP7012489B2 JP 7012489 B2 JP7012489 B2 JP 7012489B2 JP 2017174084 A JP2017174084 A JP 2017174084A JP 2017174084 A JP2017174084 A JP 2017174084A JP 7012489 B2 JP7012489 B2 JP 7012489B2
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Description
図1~図13に基づき、本発明の第1実施形態にかかる半導体装置A10について説明する。半導体装置A10は、導電支持体10、半導体素子20、接合層29、封止樹脂30、外部端子40および絶縁膜50を備える。ここで、図1は、理解の便宜上、封止樹脂30および絶縁膜50を透過している。図2は、理解の便宜上、封止樹脂30を透過している。図8は、図2のVIII-VIII線(図2に示す一点鎖線)に沿う断面図である。図11~図13の図示範囲は、図10の図示範囲と同一である。なお、図1において透過した封止樹脂30および絶縁膜50の外形を想像線(二点鎖線)で示している。
図18~図23に基づき、本発明の第2実施形態にかかる半導体装置A20について説明する。これらの図において、先述した半導体装置A10と同一または類似の要素には同一の符号を付して、重複する説明を省略する。ここで、図18は、理解の便宜上、封止樹脂30を透過している。図21は、図18のXXI-XXI線(図18に示す一点鎖線)に沿う断面図である。図23の図示範囲は、図22の図示範囲と同一である。
図24~図33に基づき、本発明の第3実施形態にかかる半導体装置A30について説明する。これらの図において、先述した半導体装置A10と同一または類似の要素には同一の符号を付して、重複する説明を省略する。ここで、図24は、理解の便宜上、封止樹脂30を透過している。図29は、図24のXXIX-XXIX線(図24に示す一点鎖線)に沿う断面図である。図31の図示範囲は、図30の図示範囲と同一である。図32の断面位置は、図28の断面位置と同一である。図33の断面位置は、図29の断面位置と同一である。
図45および図45に基づき、本発明の第4実施形態にかかる半導体装置A40について説明する。これらの図において、先述した半導体装置A30と同一または類似の要素には同一の符号を付して、重複する説明を省略する。図45および図46の断面位置は、ともに図28の断面位置と同一である。
A20,A21:半導体装置
A30,A31,A32:半導体装置
A40,A41:半導体装置
10:導電支持体
101:基板
101A:主面
101B:裏面
101C:外側面
101D:内側面
102:導電層
102A:第1導電層
102B:第2導電層
102C:中間導電層
11:支持面
12:実装面
13:端面
131:外端面
132:内端面
14:陥入部
15:凹部
151:底面
152:中間面
16:貫通孔
19:溝
191:溝内面
20:半導体素子
21:素子主面
22:素子裏面
23:素子絶縁膜
231:開口
24:電極
29:接合層
30:封止樹脂
31:樹脂主面
32:樹脂裏面
33:樹脂側面
331:樹脂外側面
332:樹脂内側面
40:外部端子
50:絶縁膜
51:開口
80:基材
801:主面
802:裏面
81:凹部
811:底面
812:中間面
82:孔
830:下地層
831:中間導電層
832:内部導電層
833:外部導電層
839:接合層
84:半導体素子
841:電極
85:封止樹脂
86:溝
B:境界
W1,W2:幅
CL:切断線
x:第1方向
y:第2方向
z:厚さ方向
Claims (10)
- 厚さ方向において互いに反対側を向く支持面および実装面と、前記実装面に交差し、かつ外側を向く端面と、を有するとともに、金属から構成された導電支持体と、
前記支持面に対向する素子裏面と、前記素子裏面に形成された電極と、を有するとともに、前記電極が前記支持面に接続された半導体素子と、
前記実装面に導通し、かつ外部に露出する外部端子と、
前記実装面と同方向を向く樹脂裏面と、前記樹脂裏面に交差する樹脂側面と、前記樹脂裏面とは反対側を向く樹脂主面と、を有するとともに、前記導電支持体の一部、および前記半導体素子を覆う封止樹脂と、を備え、
前記外部端子は、Pを含有するNi層と、Au層と、を含むとともに、前記樹脂裏面および前記樹脂側面の双方から外部に露出しており、
前記樹脂側面は、前記樹脂主面に交差する樹脂外側面と、前記樹脂外側面から前記封止樹脂の内部に向けて凹み、かつ前記樹脂外側面および前記樹脂裏面の双方に交差する樹脂内側面と、を有し、
前記端面は、前記樹脂内側面と面一であり、
前記外部端子は、前記実装面の少なくとも一部と、前記端面の全部と、に接して積層されている、半導体装置。 - 前記外部端子は、前記実装面と前記端面との境界を跨いで積層されている、請求項1に記載の半導体装置。
- 前記外部端子は、前記実装面および前記端面の双方に接する前記Ni層と、前記Ni層に接する前記Au層から構成される、請求項1または2に記載の半導体装置。
- 前記外部端子は、前記実装面および前記端面の双方に接する前記Ni層と、前記Ni層に接するPd層と、前記Pd層に接する前記Au層から構成される、請求項1または2に記載の半導体装置。
- 前記導電支持体は、Niを含む、請求項1ないし4のいずれかに記載の半導体装置。
- 前記実装面の一部および前記樹脂裏面の双方に接して設けられた絶縁膜をさらに備え、
前記外部端子は、前記絶縁膜から外部に露出している、請求項5に記載の半導体装置。 - 前記導電支持体は、Cuを含むリードフレームから構成される、請求項1ないし4のいずれかに記載の半導体装置。
- 前記導電支持体には、前記実装面から前記厚さ方向に向けて凹む陥入部が形成されており、
前記陥入部に前記封止樹脂が接している、請求項7に記載の半導体装置。 - 前記樹脂裏面に接して設けられた絶縁膜をさらに備え、
前記外部端子は、前記絶縁膜から外部に露出している、請求項8に記載の半導体装置。 - 前記支持面と前記電極との間に介在する接合層をさらに備え、
前記接合層は、Snを含有する合金を含む、請求項1ないし9のいずれかに記載の半導体装置。
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JP2017174084A JP7012489B2 (ja) | 2017-09-11 | 2017-09-11 | 半導体装置 |
US16/042,793 US10832990B2 (en) | 2017-09-11 | 2018-07-23 | Semiconductor device with external terminal |
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JP7084345B2 (ja) | 2019-03-18 | 2022-06-14 | 株式会社デンソー | 結像光学系 |
JP7183964B2 (ja) * | 2019-06-11 | 2022-12-06 | 株式会社デンソー | 半導体装置 |
JP7421877B2 (ja) * | 2019-06-27 | 2024-01-25 | ローム株式会社 | 半導体装置 |
EP4213197A1 (en) * | 2022-01-12 | 2023-07-19 | Nexperia B.V. | A semiconductor package substrate made from non-metallic material and a method of manufacturing thereof |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002270715A (ja) | 2001-03-09 | 2002-09-20 | Sumitomo Bakelite Co Ltd | 半導体装置の製造方法および半導体装置 |
JP2006165411A (ja) | 2004-12-10 | 2006-06-22 | New Japan Radio Co Ltd | 半導体装置およびその製造方法 |
JP2017128791A (ja) | 2016-01-19 | 2017-07-27 | Jx金属株式会社 | 無電解Niめっき皮膜を有する構造物、その製造方法および半導体ウェハ |
JP2017147272A (ja) | 2016-02-15 | 2017-08-24 | ローム株式会社 | 半導体装置およびその製造方法、ならびに、半導体装置の製造に使用されるリードフレーム中間体 |
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JP3891838B2 (ja) * | 2001-12-26 | 2007-03-14 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
US7824937B2 (en) * | 2003-03-10 | 2010-11-02 | Toyoda Gosei Co., Ltd. | Solid element device and method for manufacturing the same |
JP4961887B2 (ja) * | 2005-09-07 | 2012-06-27 | 豊田合成株式会社 | 固体素子デバイス |
US9548261B2 (en) * | 2013-03-05 | 2017-01-17 | Nichia Corporation | Lead frame and semiconductor device |
JP2015053469A (ja) | 2013-08-07 | 2015-03-19 | 日東電工株式会社 | 半導体パッケージの製造方法 |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002270715A (ja) | 2001-03-09 | 2002-09-20 | Sumitomo Bakelite Co Ltd | 半導体装置の製造方法および半導体装置 |
JP2006165411A (ja) | 2004-12-10 | 2006-06-22 | New Japan Radio Co Ltd | 半導体装置およびその製造方法 |
JP2017128791A (ja) | 2016-01-19 | 2017-07-27 | Jx金属株式会社 | 無電解Niめっき皮膜を有する構造物、その製造方法および半導体ウェハ |
JP2017147272A (ja) | 2016-02-15 | 2017-08-24 | ローム株式会社 | 半導体装置およびその製造方法、ならびに、半導体装置の製造に使用されるリードフレーム中間体 |
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