CN106601631A - 先封后蚀电镀铜柱导通一次包封三维封装结构的工艺方法 - Google Patents
先封后蚀电镀铜柱导通一次包封三维封装结构的工艺方法 Download PDFInfo
- Publication number
- CN106601631A CN106601631A CN201611191653.8A CN201611191653A CN106601631A CN 106601631 A CN106601631 A CN 106601631A CN 201611191653 A CN201611191653 A CN 201611191653A CN 106601631 A CN106601631 A CN 106601631A
- Authority
- CN
- China
- Prior art keywords
- metal
- plating
- conducting
- circuit layer
- plastic packaging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 55
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 46
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 46
- 239000010949 copper Substances 0.000 title claims abstract description 46
- 238000000034 method Methods 0.000 title claims abstract description 38
- 238000005530 etching Methods 0.000 title claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims abstract description 82
- 239000002184 metal Substances 0.000 claims abstract description 82
- 239000004033 plastic Substances 0.000 claims abstract description 34
- 239000003822 epoxy resin Substances 0.000 claims abstract description 13
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 13
- 238000005520 cutting process Methods 0.000 claims abstract description 10
- 238000007747 plating Methods 0.000 claims description 45
- 239000000463 material Substances 0.000 claims description 25
- 230000003628 erosive effect Effects 0.000 claims description 21
- 239000005022 packaging material Substances 0.000 claims description 12
- 230000002093 peripheral effect Effects 0.000 claims description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 10
- 239000003963 antioxidant agent Substances 0.000 claims description 10
- 230000003078 antioxidant effect Effects 0.000 claims description 10
- 235000006708 antioxidants Nutrition 0.000 claims description 10
- 239000000047 product Substances 0.000 claims description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 7
- 238000005507 spraying Methods 0.000 claims description 7
- 238000000227 grinding Methods 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 238000005234 chemical deposition Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 238000002360 preparation method Methods 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 238000004220 aggregation Methods 0.000 claims description 3
- 230000002776 aggregation Effects 0.000 claims description 3
- 238000004070 electrodeposition Methods 0.000 claims description 3
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 claims description 3
- 239000011265 semifinished product Substances 0.000 claims description 3
- 239000008199 coating composition Substances 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 3
- 238000009713 electroplating Methods 0.000 abstract 4
- 230000003064 anti-oxidating effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 47
- 229920002120 photoresistant polymer Polymers 0.000 description 26
- 239000002356 single layer Substances 0.000 description 8
- 239000000758 substrate Substances 0.000 description 6
- 238000011161 development Methods 0.000 description 5
- 238000005538 encapsulation Methods 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000003384 imaging method Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 238000005406 washing Methods 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- FBAFATDZDUQKNH-UHFFFAOYSA-M iron chloride Chemical compound [Cl-].[Fe] FBAFATDZDUQKNH-UHFFFAOYSA-M 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- -1 NiPdAu Chemical compound 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009172 bursting Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229920000767 polyaniline Polymers 0.000 description 1
- 229920000128 polypyrrole Polymers 0.000 description 1
- 229920000123 polythiophene Polymers 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
本发明涉及一种先封后蚀电镀铜柱导通一次包封三维封装结构的工艺方法,它包括以下步骤:步骤一、取金属载体;步骤二、金属载体表面预镀铜层;步骤三、电镀金属外引脚;步骤四、环氧树脂塑封;步骤五、电镀金属线路层;步骤六、电镀导电金属柱;步骤七、贴装芯片;步骤八、无源器件贴装;步骤九、塑封;步骤十、载体蚀刻开窗;步骤十一、电镀抗氧化金属层;步骤十二、切割成品。本发明能够解决传统金属引线框或有机载体本身无法埋入元器件而限制整个封装功能集成度的问题,且此工艺方法制备的线路层被包封起来,可以提高产品的可靠性能。
Description
技术领域
本发明涉及一种先封后蚀电镀铜柱导通一次包封三维封装结构的工艺方法,属于半导体封装技术领域。
背景技术
针对半导体封装轻薄短小的要求,现在的金属引线框或者有机基板的封装都在朝两个方向努力:1、降低封装尺寸;2、功能集成。对于降低封装尺寸部分,可以改善的空间有限,所以封装行业内集中于提高功能集成度,就是将部分功能元器件或者其他电子器件以埋入的方式集成于基板内部,以扩大整个封装体的功能集成度,而由于埋入元器件之后的基板层间材料更加复杂多样,并且不同材料的热膨胀系数差异很大,导致整个基板的翘曲问题严重、分层加剧,甚至引起爆板的问题。
发明内容
本发明所要解决的技术问题是针对上述现有技术提供一种先封后蚀电镀铜柱导通一次包封三维封装结构的工艺方法,它能够埋入元器件提升整个封装功能集成度,且此工艺方法制备的线路层在金属载体的一侧被包封起来,在工艺流程中金属载体保留,采用一次性包封的制程,降低整体基板的翘曲性。
本发明解决上述问题所采用的技术方案为:一种先封后蚀电镀铜柱导通一次包封三维封装结构的工艺方法,所述方法包括以下步骤:
步骤一、取金属载体
步骤二、金属载体表面预镀铜层
步骤三、电镀金属外引脚
在金属载体正面通过电镀形成金属外引脚;
步骤四、环氧树脂塑封
将金属外引脚外围区域利用环氧树脂材料进行塑封保护,并通过表面研磨使金属外引脚顶端露出塑封料表面;
步骤五、电镀金属线路层
在步骤四的塑封料表面通过电镀形成金属线路层;
步骤六、电镀导电金属柱
在金属线路层表面通过电镀形成导电金属柱;
步骤七、贴装芯片
在金属线路层表面贴装芯片;
步骤八、无源器件贴装
在导电金属柱顶端贴装无源器件;
步骤九、塑封
将金属线路层、导电金属柱、芯片和无源器件外围区域采用塑封料进行塑封;
步骤十、载体蚀刻开窗
在金属载体背面进行蚀刻开窗,使外引脚背面露出;
步骤十一、电镀抗氧化金属层
在露出的金属外引脚背面通过电镀形成抗氧化金属层;
步骤十二、切割成品
将步骤十一完成电镀抗氧化金属层的半成品进行切割作业,使原本以阵列式集合体方式集成在一起的塑封体模块一颗颗切割独立开来,制得先封后蚀电镀铜柱导通一次包封三维封装结构成品。
步骤二中的铜层厚度在2~10微米。
步骤二中铜层的制备方式是化学沉积、电沉积或者气相沉积。
所述金属外引脚和金属线路层的材料是铜、铝或镍,所述抗氧化金属层的材料采用金、镍金、镍钯金或锡。
塑封方式采用模具灌胶方式、喷涂设备喷涂方式、贴膜方式或是刷胶的方式。
步骤十一中的蚀刻方法采用氯化铜或者氯化铁的蚀刻工艺。
一种先封后蚀电镀铜柱导通一次包封三维封装结构,它包括金属线路层,所述金属线路层正面设置有导电金属柱,所述金属线路层背面设置有金属外引脚,所述金属外引脚外围区域包封有预包封料,所述金属线路层上通过金属凸点设置有倒装芯片,所述导电金属柱顶端通过焊料设置有第一无源器件,所述金属线路层、导电金属柱、倒装芯片和第一无源器件的外围区域包封有塑封料。
所述芯片采用正装或倒装。
所述芯片一侧设置有第二无源器件。
所述芯片有多个。
与现有技术相比,本发明的优点在于:
1、本发明的三维封装结构工艺流程,在基板中间的夹层制作过程中埋入对象,可以根据系统或功能需要在需要的位置或是区域埋入主动或被动元器件,封装整合的系统功能多,从而同样功能的元器件模块在PCB板上占用的空间比较少,从而降低成本又提升了封装的集成度;
2、本发明的三维封装结构,引脚线路层全部设计在金属载体的一侧且被包封在产品内部,防止外露在外的氧化,采用一次包封,提高了封装可靠性;
3、本发明的三维封装结构,采用在金属载体一侧封装,利用金属载体在封装的工艺流程中保留,可以在塑封料遇冷收缩的时候起到牵制的作用,可以有效的防止整体封装结构的翘曲,并减少产品破裂。
附图说明
图1~图22为本发明一种先封后蚀电镀铜柱导通一次包封三维封装结构实施例1工艺方法的各工序示意图。
图23为本发明一种先封后蚀电镀铜柱导通一次包封三维封装结构实施例1的示意图。
图24为本发明一种先封后蚀电镀铜柱导通一次包封三维封装结构实施例2的示意图。
图25为本发明一种先封后蚀电镀铜柱导通一次包封三维封装结构实施例3的示意图。
图26为本发明一种先封后蚀电镀铜柱导通一次包封三维封装结构实施例4的示意图。
图27为本发明一种先封后蚀电镀铜柱导通一次包封三维封装结构实施例5的示意图。
图28为本发明一种先封后蚀电镀铜柱导通一次包封三维封装结构实施例6的示意图。
图29为本发明一种先封后蚀电镀铜柱导通一次包封三维封装结构实施例7的示意图。
图30为本发明一种先封后蚀电镀铜柱导通一次包封三维封装结构实施例8的示意图。
其中:
金属载体1
定位孔2
铜层3
预包封料4
金属外引脚5
导电层6
金属线路层7
金属凸点8
导电金属柱9
塑封料10
倒装芯片11
第一无源器件12
正装芯片13
金属线14
第二无源器件15。
具体实施方式
以下结合附图实施例对本发明作进一步详细描述。
实施例1:单层线路单芯片倒装
如图23所示,本实施例中的一种先封后蚀电镀铜柱导通一次包封三维封装结构,它包括金属线路层7,所述金属线路层7正面设置有导电金属柱9,所述金属线路层7背面设置有金属外引脚5,所述金属外引脚5外围区域包封有预包封料4,所述金属线路层7上通过金属凸点8设置有倒装芯片11,所述导电金属柱9顶端通过焊料设置有第一无源器件12,所述金属线路层7、导电金属柱9、倒装芯片11和第一无源器件12的外围区域包封有塑封料10。
其工艺方法如下:
步骤一、取金属载体
参见图1,取一片厚度合适的金属载体,此板材使用的目的是为线路制作及线路层结构提供支撑,此板材的材质主要以金属材料为主,而金属材料的材质可以是铜材,铁材,不锈钢材或其它可导电功能的金属物质;
步骤二、金属载体表面预镀铜层
参见图2,在金属载体表面预镀铜层,铜层厚度在2~10微米,制备方式可以是化学沉积、电沉积或者气相沉积;
步骤三、光刻作业
参见图3,在预镀铜层的金属载体正面及背面贴覆或印刷可进行曝光显影的光阻材料,以保护后续电镀金属层工艺作业,并利用曝光显影设备对金属载体表面的光阻材料进行曝光、显影与去除部分光阻材料,以露出金属载体表面需要进行金属外引脚电镀的图形区域,光阻材料可以是光阻膜,也可以是光刻胶;
步骤四、电镀金属外引脚
参见图4,在步骤四中金属载体正面去除部分光阻材料的区域内电镀上金属外引脚,金属外引脚材料通常是铜、铝、镍等,也可以是其它导电金属物质;
步骤五、去除光阻材料
参见图5,去除金属载体表面的光阻膜,去除光阻膜的方法可以采用化学药水软化并采用高压水冲洗的方法去除光阻膜;
步骤六、环氧树脂塑封
参见图6,在金属载体正面的金属外引脚外围区域利用环氧树脂材料进行塑封保护,环氧树脂材料可以依据产品特性选择有填料或者没有填料的种类,塑封方式可以采用模具灌胶方式、喷涂设备喷涂方式、贴膜方式或是刷胶的方式;
步骤七、表面研磨
参见图7,在完成环氧树脂塑封后进行环氧树脂表面研磨,目的是使金属外引脚顶端露出塑封体表面以及控制环氧树脂的厚度;
步骤八、环氧树脂表面导电层制备
参见图8,在研磨后的环氧树脂表面进行导电层制备;导电层可以是金属类物质,如镍、钛、铜、银等,也可以使非金属导电高分子材料,如聚苯胺、聚吡咯、聚噻吩等。沉积方式通常为化学沉积、气相沉积、溅射等;
步骤九、光刻作业
参见图9,在步骤八金属载体正面贴覆或印刷可进行曝光显影的光阻材料,并利用曝光显影设备对光阻材料进行曝光、显影与去除部分光阻材料,以露出金属载体表面需要进行金属线路层电镀的图形区域,光阻材料可以是光阻膜,也可以是光刻胶;
步骤十、电镀金属线路层
参见图10,在步骤九中金属载体正面去除部分光阻材料的区域内电镀上金属线路层,金属线路层材料通常是铜、铝、镍等,也可以是其它导电金属物质;
步骤十一、光刻作业
参见图11,在步骤十金属载体正面面贴覆或印刷可进行曝光显影的光阻材料,并利用曝光显影设备对光阻材料进行曝光、显影与去除部分光阻材料,以露出金属载体表面需要进行导电金属柱电镀的图形区域,光阻材料可以是光阻膜,也可以是光刻胶;
步骤十二、电镀导电金属柱
参见图12,在步骤十一中金属载体正面去除部分光阻材料的区域内电镀导电金属柱,该导电金属柱用于三维封装结构之间的导通及连接;
步骤十三、去除光阻材料
参见图13,去除金属载体表面的光阻膜,去除光阻膜的方法可以采用化学药水软化并采用高压水冲洗的方法去除光阻膜;
步骤十四、快速蚀刻
参见图14,去除金属载体正面露出的导电层;
步骤十五、芯片倒装
参见图15,在金属线路层上倒装芯片;
步骤十六、无源器件贴装
参见图16,在导电金属柱顶端贴装无源器件;
步骤十七、塑封
参见图17,将步骤十六的金属载体正面采用塑封料进行塑封,塑封方式可以采用模具灌胶方式、压缩灌胶、喷涂方式或是用贴膜方式,所述可以采用有填料物质或是无填料物质的环氧树脂;
步骤十八、光刻作业
参见图18,在金属载体背面贴覆或印刷可进行曝光显影的光阻材料,并利用曝光显影设备对光阻材料进行曝光、显影与去除部分光阻材料,以露出金属载体表面需要进行蚀刻的图形区域,光阻材料可以是光阻膜,也可以是光刻胶。
步骤十九、载体蚀刻
参见图19,在步骤十八中金属载体背面去除部分光阻材料的区域进行化学蚀刻开窗,蚀刻方法可以采用氯化铜或者氯化铁的蚀刻工艺;
步骤二十、去除光阻材料
参见图20,去除金属载体表面的光阻膜,去除光阻膜的方法可以采用化学药水软化并采用高压水冲洗的方法去除光阻膜;
步骤二十一、电镀抗氧化金属层
参见图21,在步骤二十中去除光阻材料后,金属载体表面裸露在外的金属表面进行抗氧化金属层电镀,如金、镍金、镍钯金、锡等;
步骤二十二、切割成品
参见图22,将步骤二十一完成电镀抗氧化金属层的半成品进行切割作业,使原本以阵列式集合体方式集成在一起的塑封体模块一颗颗切割独立开来,制得先封后蚀电镀铜柱导通一次包封芯片倒装三维封装结构成品。
实施例2:单层线路单芯片正装堆叠无源器件
参见图24,实施例2与实施例1的区别在于:金属线路层7正面的倒装芯片11替换为正装芯片13,所述正装芯片13与金属线路层7之间通过金属线14相连接。
实施例3:单层线路单无源器件堆叠无源器件
参见图25,实施例3与实施例1的区别在于:金属线路层7正面的倒装芯片11替换为第二无源器件15。
实施例4:单层线路多芯片倒装堆叠无源器件
参见图26,实施例4与实施例1的区别在于:倒装芯片11有多个。
实施例5:单层线路多芯片正装堆叠无源器件
参见图27,实施例5与实施例2的区别在于:正装芯片13有多个。
实施例6:单层线路正装芯片+无源器件堆叠无源器件
参见图28,实施例6与实施例1的区别在于:倒装芯片11一侧设置有第二无源器件15;
实施例7:单层线路倒装芯片+无源器件堆叠无源器件
参见图29,实施例7与实施例2的区别在于:正装芯片13一侧设置有第二无源器件15;
实施例8:单层线路多无源器件堆叠无源器件
参见图30,实施例8与实施例3的区别在于:第二无源器件15有多个。
除上述实施例外,本发明还包括有其他实施方式,凡采用等同变换或者等效替换方式形成的技术方案,均应落入本发明权利要求的保护范围之内。
Claims (8)
1.一种先封后蚀电镀铜柱导通一次包封三维封装结构的工艺方法,其特征在于所述方法包括以下步骤:
步骤一、取金属载体
步骤二、金属载体表面预镀铜层
步骤三、电镀金属外引脚
在金属载体正面通过电镀形成金属外引脚;
步骤四、环氧树脂塑封
将金属外引脚外围区域利用环氧树脂材料进行塑封保护,并通过表面研磨使金属外引脚顶端露出塑封料表面;
步骤五、电镀金属线路层
在步骤四的塑封料表面通过电镀形成金属线路层;
步骤六、电镀导电金属柱
在金属线路层表面通过电镀形成导电金属柱;
步骤七、贴装芯片
在金属线路层表面贴装芯片;
步骤八、无源器件贴装
在导电金属柱顶端贴装无源器件;
步骤九、塑封
将金属线路层、导电金属柱、芯片和无源器件外围区域采用塑封料进行塑封;
步骤十、载体蚀刻开窗
在金属载体背面进行蚀刻开窗,使外引脚背面露出;
步骤十一、电镀抗氧化金属层
在露出的金属外引脚背面通过电镀形成抗氧化金属层;
步骤十二、切割成品
将步骤十一完成电镀抗氧化金属层的半成品进行切割作业,使原本以阵列式集合体方式集成在一起的塑封体模块一颗颗切割独立开来,制得先封后蚀电镀铜柱导通一次包封三维封装结构成品。
2.根据权利要求1所述的一种先封后蚀电镀铜柱导通一次包封三维封装结构的工艺方法,其特征在于:步骤二中的铜层厚度在2~10微米。
3.根据权利要求1所述的一种先封后蚀电镀铜柱导通一次包封三维封装结构的工艺方法,其特征在于:步骤二中铜层的制备方式是化学沉积、电沉积或者气相沉积。
4.根据权利要求1所述的一种先封后蚀电镀铜柱导通一次包封三维封装结构的工艺方法,其特征在于:所述金属外引脚和金属线路层的材料是铜、铝或镍,所述抗氧化金属层的材料采用金、镍金、镍钯金或锡。
5.根据权利要求1所述的一种先封后蚀电镀铜柱导通一次包封三维封装结构的工艺方法,其特征在于:塑封方式采用模具灌胶方式、喷涂设备喷涂方式、贴膜方式或是刷胶的方式。
6.一种先封后蚀电镀铜柱导通一次包封三维封装结构,其特征在于:它包括金属线路层(7),所述金属线路层(7)正面设置有导电金属柱(9),所述金属线路层(7)背面设置有金属外引脚(5),所述金属外引脚(5)外围区域包封有预包封料(4),所述金属线路层(7)上设置有芯片,所述导电金属柱(9)顶端设置有第一无源器件(12),所述金属线路层(7)、导电金属柱(9)、芯片和第一无源器件(12)的外围区域包封有塑封料(10)。
7.根据权利要求6所述的一种先封后蚀电镀铜柱导通一次包封三维封装结构,其特征在于:所述芯片一侧设置有第二无源器件(15)。
8.根据权利要求6所述的一种先封后蚀电镀铜柱导通一次包封三维封装结构,其特征在于:所述芯片有多个。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201611191653.8A CN106601631A (zh) | 2016-12-21 | 2016-12-21 | 先封后蚀电镀铜柱导通一次包封三维封装结构的工艺方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201611191653.8A CN106601631A (zh) | 2016-12-21 | 2016-12-21 | 先封后蚀电镀铜柱导通一次包封三维封装结构的工艺方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN106601631A true CN106601631A (zh) | 2017-04-26 |
Family
ID=58600403
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201611191653.8A Pending CN106601631A (zh) | 2016-12-21 | 2016-12-21 | 先封后蚀电镀铜柱导通一次包封三维封装结构的工艺方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN106601631A (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018113575A1 (zh) * | 2016-12-21 | 2018-06-28 | 江苏长电科技股份有限公司 | 先封后蚀电镀铜柱导通三维封装结构及其工艺方法 |
CN108974562A (zh) * | 2018-09-04 | 2018-12-11 | 张淼淼 | 一种电子元器件引脚防氧化方法 |
JP2020088306A (ja) * | 2018-11-30 | 2020-06-04 | ローム株式会社 | 半導体装置 |
CN112530907A (zh) * | 2020-12-02 | 2021-03-19 | 中国电子科技集团公司第十四研究所 | 一种无源器件堆叠的多芯片封装结构和方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040058472A1 (en) * | 2002-09-25 | 2004-03-25 | Shim Jong Bo | Area array semiconductor package and 3-dimensional stack thereof |
CN102456677A (zh) * | 2010-10-27 | 2012-05-16 | 三星半导体(中国)研究开发有限公司 | 球栅阵列封装结构及其制造方法 |
CN102593110A (zh) * | 2012-01-05 | 2012-07-18 | 三星半导体(中国)研究开发有限公司 | 超细间距焊盘的叠层倒装芯片封装结构及底填充制造方法 |
CN103400773A (zh) * | 2013-08-06 | 2013-11-20 | 江苏长电科技股份有限公司 | 先封后蚀无源器件三维系统级金属线路板结构及工艺方法 |
-
2016
- 2016-12-21 CN CN201611191653.8A patent/CN106601631A/zh active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040058472A1 (en) * | 2002-09-25 | 2004-03-25 | Shim Jong Bo | Area array semiconductor package and 3-dimensional stack thereof |
CN102456677A (zh) * | 2010-10-27 | 2012-05-16 | 三星半导体(中国)研究开发有限公司 | 球栅阵列封装结构及其制造方法 |
CN102593110A (zh) * | 2012-01-05 | 2012-07-18 | 三星半导体(中国)研究开发有限公司 | 超细间距焊盘的叠层倒装芯片封装结构及底填充制造方法 |
CN103400773A (zh) * | 2013-08-06 | 2013-11-20 | 江苏长电科技股份有限公司 | 先封后蚀无源器件三维系统级金属线路板结构及工艺方法 |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018113575A1 (zh) * | 2016-12-21 | 2018-06-28 | 江苏长电科技股份有限公司 | 先封后蚀电镀铜柱导通三维封装结构及其工艺方法 |
US11217459B2 (en) | 2016-12-21 | 2022-01-04 | Jiangsu Changjiang Electronics Technology Co., Ltd. | Package-before-etch three-dimensional package structure electrically connected by plated copper pillars and process thereof |
US11823911B2 (en) | 2016-12-21 | 2023-11-21 | Jiangsu Changjiang Electronics Technology Co., Ltd. | Process of package-then-etch three-dimensional package structure electrically connected by plated copper pillars |
CN108974562A (zh) * | 2018-09-04 | 2018-12-11 | 张淼淼 | 一种电子元器件引脚防氧化方法 |
CN108974562B (zh) * | 2018-09-04 | 2019-12-24 | 江苏朗丰科技有限公司 | 一种电子元器件引脚防氧化方法 |
JP2020088306A (ja) * | 2018-11-30 | 2020-06-04 | ローム株式会社 | 半導体装置 |
JP7245037B2 (ja) | 2018-11-30 | 2023-03-23 | ローム株式会社 | 半導体装置 |
CN112530907A (zh) * | 2020-12-02 | 2021-03-19 | 中国电子科技集团公司第十四研究所 | 一种无源器件堆叠的多芯片封装结构和方法 |
CN112530907B (zh) * | 2020-12-02 | 2024-07-23 | 中国电子科技集团公司第十四研究所 | 一种无源器件堆叠的多芯片封装结构和方法 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN106601627A (zh) | 先封后蚀电镀铜柱导通三维封装结构的工艺方法 | |
US9196597B2 (en) | Semiconductor package with single sided substrate design and manufacturing methods thereof | |
US7934313B1 (en) | Package structure fabrication method | |
CN103730429B (zh) | 封装结构 | |
TWI538137B (zh) | 具有單側基板設計的半導體封裝及其製造方法 | |
US20090004774A1 (en) | Method of multi-chip packaging in a tsop package | |
US9177837B2 (en) | Fabrication method of semiconductor package having electrical connecting structures | |
CN103745931B (zh) | 引线框架和封装结构的形成方法 | |
JP4919103B2 (ja) | ランドグリッドアレイ半導体装置パッケージ、同パッケージを含む組み立て体、および製造方法 | |
CN106531645A (zh) | 先封后蚀贴装金属导通三维封装结构的工艺方法 | |
US20090278243A1 (en) | Stacked type chip package structure and method for fabricating the same | |
CN106601631A (zh) | 先封后蚀电镀铜柱导通一次包封三维封装结构的工艺方法 | |
JP6534602B2 (ja) | 配線基板、半導体装置及び配線基板の製造方法 | |
US7101733B2 (en) | Leadframe with a chip pad for two-sided stacking and method for manufacturing the same | |
US20190088506A1 (en) | Semiconductor package and method of manufacturing the same | |
US9153530B2 (en) | Thermal enhanced high density flip chip package | |
US9202712B2 (en) | Lead frame and a method of manufacturing thereof | |
CN106783790A (zh) | 一种具有低电阻损耗三维封装结构及其工艺方法 | |
CN103730378A (zh) | 封装结构的形成方法 | |
WO2013097580A1 (zh) | 一种芯片上芯片封装及制造方法 | |
WO2014114003A1 (en) | Semiconductor device including embedded controller die and method of making same | |
CN103441078B (zh) | 先封后蚀三维系统级芯片正装堆叠封装结构及工艺方法 | |
CN210575932U (zh) | 一种引线框架及封装结构 | |
KR101128999B1 (ko) | 칩 패키지 제조 방법 및 이에 의해 제조된 칩 패키지 | |
CN106981430B (zh) | 一种贴装金属导通三维系统级线路板的工艺方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170426 |
|
RJ01 | Rejection of invention patent application after publication |