JP4919103B2 - ランドグリッドアレイ半導体装置パッケージ、同パッケージを含む組み立て体、および製造方法 - Google Patents
ランドグリッドアレイ半導体装置パッケージ、同パッケージを含む組み立て体、および製造方法 Download PDFInfo
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- JP4919103B2 JP4919103B2 JP2008527946A JP2008527946A JP4919103B2 JP 4919103 B2 JP4919103 B2 JP 4919103B2 JP 2008527946 A JP2008527946 A JP 2008527946A JP 2008527946 A JP2008527946 A JP 2008527946A JP 4919103 B2 JP4919103 B2 JP 4919103B2
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- Wire Bonding (AREA)
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Description
電気部品、またはこの両方が接続されたランドグリッドアレイパッケージを有する半導体装置パッケージをさらに含む。
の同じ側で、インターポーザ基板112のランド列118の間の中央領域にあるパッドアレイ120の導電性パッド120に電気的に接続してもよい。したがって、端子パッド114をランド118に接続すると共にパッド120にも冗長的に接続するか、ランド118のみに接続するか、あるいはパッド120のみに接続することも想定される。したがって、半導体ダイ102および104への電気的アクセスは、インターポーザ基板112に対して選択された設計に応じて、テストパッド120との接触を介して、またはランド118を介して、あるいはこの両方を介して、行いうる。パッド120は、他の部品を最終的に組み付ける前に、ランドグリッドアレイパッケージ100の半導体ダイ102および104の断線/短絡テストおよび機能テストを実施するために、または以下に説明するように他の目的のために、使用しうる。もちろん、ランド118およびパッド120のピンアウトは、さらに以下に説明するように、たとえば印刷回路板などのキャリア基板の導電性パッドまたはリードフレームへの接続用に、さらにはテスト用に、それぞれカスタマイズしうる。ランドグリッドアレイパッケージの寸法およびピンアウトは、あらゆるフラッシュおよびランダムアクセス(RAM)メモリ半導体装置に対応するように選択しうる。
ように、半田マスクまたは他のパターン化された誘電体層121を使用してインターポーザ基板212(および図1のインターポーザ基板112)の両側を覆うことによって、導電的に内張りされた(完全に導電的に充填されていない場合)ビア構造117を充填し、端子パッド114と、ランド118と、パッド120とを露出させてもよい。
に電気的に接続し、最終的には個別導電性素子320を介してより高レベルのパッケージングに機械的およびに電気的に接続しうる。同様に、1つ以上の能動部品(半導体素子)332をパッド120、ひいては半導体ダイ102、104に、接続し、最終的には個別導電性素子320を介してより高レベルのパッケージングに接続しうる。上記のように、図6に示すように能動部品332がフリップチップとして構成されるか、または複数のパッド120と位置合わせされるように配置された個別導電性素子のアレイを他の方法で担持する場合は、これらのパッド120にバンプを設ける必要はなく、能動部品によって担持された個別導電性素子を用いてこれらのパッド120に直接接続してもよい。図6に示すように、受動部品および能動部品の両方をランドグリッドアレイパッケージ100、200に接続してもよい。さらに図6に示すように、リードフレーム300のリードフィンガ304の内端308と個別導電性素子320(または、場合によっては、パッド120に直接)との間にワイヤボンド334を形成しうる。このようなワイヤボンドは、インターポーザ基板112、212内の障害のある信号、接地、バイアス、または給電経路を迂回するため、またはインターポーザ基板112、212の内部および上の導電性経路の設計および製造を簡略化するために使用しうる。
Claims (25)
- 半導体装置パッケージであって、
インターポーザ基板であって、誘電体部材と、前記インターポーザ基板の一方の側に前記インターポーザ基板の少なくとも1つの周縁部に近接し且つ前記周縁部に沿って延在する複数の端子と、前記インターポーザ基板の反対側に前記少なくとも1つの周縁部と同じ周縁部に近接し且つ前記周縁部に沿って延在するランドアレイと、を備え、前記複数の端子がそれぞれ、前記誘電体部材を貫通して延在する導電性ビア構造を介して、前記ランドアレイのランドに電気的に接続され、前記インターポーザ基板は前記インターポーザ基板の前記反対側のほぼ中央に配置された二次元パッドアレイをさらに備え、前記複数の端子がそれぞれ前記二次元パッドアレイのパッドに電気的に接続される、インターポーザ基板と、
少なくとも1つの半導体ダイであって、前記少なくとも1つの半導体ダイは、その裏面が前記インターポーザ基板の前記一方の側に取り付けられ、前記インターポーザ基板の前記少なくとも1つの周縁部に隣接する、前記少なくとも1つの半導体ダイの少なくとも1つの周縁部に近接し且つ前記周縁部に沿って延在する活性面に複数のボンドパッドを有し、前記複数のボンドパッドがそれぞれ前記複数の端子に電気的に接続される、少なくとも1つの半導体ダイと、
前記少なくとも1つの半導体ダイおよび前記インターポーザ基板の前記一方の側の上に配設された封止構造と、
複数のリードフィンガを有するリードフレームであって、前記複数のリードフィンガの内端が、それぞれ前記インターポーザ基板の前記反対側における前記ランドアレイの複数のランド上に配設され、かつ、前記複数のランドに機械的および電気的に接続されている、リードフレームと、
を備える半導体装置パッケージ。 - 前記二次元パッドアレイのパッドを介して前記インターポーザ基板に機械的および電気的に接続された少なくとも1つの電気部品をさらに備える請求項1に記載の半導体装置パッケージ。
- 前記少なくとも1つの電気部品が複数の受動部品と複数の能動部品とから成る群から選択される請求項2に記載の半導体装置パッケージ。
- 前記少なくとも1つの電気部品が誘電材料で覆われている請求項2に記載の半導体装置パッケージ。
- 前記少なくとも1つの電気部品と前記インターポーザ基板の前記反対側との間の空き容積内に配設されたアンダーフィル材料を更に備える請求項2又は4に記載の半導体装置パッケージ。
- 前記二次元パッドアレイの少なくとも一部のパッド上に配設された複数の個別導電性バンプをさらに備える請求項1又は2に記載の半導体装置パッケージ。
- 前記二次元パッドアレイの少なくとも1つのパッドと少なくとも1つのリードフィンガの内端との間に延在するワイヤボンドをさらに備える請求項1又は2に記載の半導体装置パッケージ。
- 少なくとも、前記複数のリードフィンガの前記内端と前記インターポーザ基板の前記反対側とが、誘電材料によって覆われる請求項1又は2に記載の半導体装置パッケージ。
- 前記インターポーザ基板とは反対の側に前記ランドグリッドアレイパッケージが固着されるキャリア基板であって、前記ランドグリッドアレイパッケージが固着される面に複数の導電性パッドを含むキャリア基板と、
前記ランドアレイのランドと前記複数の導電性パッドの導電性パッドとの間に延在するワイヤボンドと、
をさらに備える請求項1又は2に記載の半導体装置パッケージ。 - 前記二次元パッドアレイの少なくとも1つのパッドと前記キャリア基板の前記導電性パッドとの間に延在するワイヤボンドをさらに備える請求項9に記載の半導体装置パッケージ。
- 少なくとも、前記ランドアレイの前記ランドと、前記ワイヤボンドと、前記導電性パッドとが、誘電材料で覆われる請求項9に記載の半導体装置パッケージ。
- 前記少なくとも1つの半導体ダイが2つの半導体ダイからなり、一方の半導体ダイはその裏面が前記インターポーザ基板に取り付けられ、他方の半導体ダイは、その裏面が前記一方の半導体ダイの前記活性面に取り付けられ、かつ、前記第1の半導体ダイの前記複数のボンドパッドを露出させる寸法を有する請求項1又は2に記載の半導体装置パッケージ。
- 半導体装置パッケージの製造方法であって、
インターポーザ基板を設けるステップであって、前記インターポーザ基板は、誘電体部材と、前記インターポーザ基板の一方の側に前記インターポーザ基板の少なくとも1つの周縁部に近接し且つ前記周縁部に沿って延在する複数の端子と、前記インターポーザ基板の反対側に前記少なくとも1つの周縁部と同じ周縁部に近接し且つ前記周縁部に沿って延在するランドのアレイと、を備え、前記複数の端子がそれぞれ前記誘電体部材を貫通して延在する導電性ビア構造を介して前記ランドアレイのランドに電気的に接続され、前記インターポーザ基板は、前記インターポーザ基板の前記反対側のほぼ中央に配置された二次元パッドアレイをさらに備え、前記複数の端子がそれぞれ前記二次元パッドアレイのパッドに電気的に接続される、ステップと、
少なくとも1つの半導体ダイをその裏面を前記インターポーザ基板の前記一方の側に向けて取り付けるステップであって、前記半導体ダイは、前記インターポーザ基板の前記少なくとも1つの周縁部に隣接する前記半導体ダイの少なくとも1つの周縁部に近接し且つ前記周縁部に沿って延在する、前記半導体ダイの活性面上の複数のボンドパッドを有する、ステップと、
前記複数のボンドパッドを前記複数の端子にそれぞれ電気的に接続するステップと、
封止構造を前記インターポーザ基板の前記一方の側および前記少なくとも1つの半導体ダイの上に配設するステップと、
複数のリードフィンガを含むリードフレームを設け、前記複数のリードフィンガの内端をそれぞれ前記インターポーザ基板の前記反対側における前記ランドアレイのランドの上に配設し、前記内端を前記ランドに機械的および電気的に接続するステップと、
を含む方法。 - 少なくとも1つの電気部品を前記二次元パッドアレイのパッドを介して前記インターポーザ基板に機械的および電気的に接続するステップをさらに含む請求項13に記載の方法。
- 前記少なくとも1つの電気部品を複数の受動部品と複数の能動部品とから成る群から選択するステップをさらに含む請求項14に記載の方法。
- 前記少なくとも1つの電気部品を誘電材料で覆うステップをさらに含む請求項14記載の方法。
- 前記少なくとも1つの電気部品と前記インターポーザ基板の前記反対側との間の空き容積内に誘電性アンダーフィル材料を配設するステップを更に備える請求項14又は16に記載の方法。
- 前記二次元パッドアレイの少なくとも1つのパッドと少なくとも1つのリードフィンガの内端との間にワイヤボンドを延在させるステップをさらに含む請求項13又は14に記載の方法。
- 少なくとも前記リードフィンガの前記内端と前記インターポーザ基板の前記反対側とを誘電材料で覆うステップをさらに含む請求項13又は14に記載の方法。
- キャリア基板を前記ランドグリッドアレイパッケージの、前記インターポーザ基板とは反対の側に固着するステップであって、前記キャリア基板は前記ランドグリッドアレイパッケージが固着される表面に複数の導電性パッドを含む、ステップと、
前記ランドアレイのランドと前記複数の導電性パッドの導電性パッドとの間にワイヤボンドを延在させるステップと、
をさらに含む請求項13又は14に記載の方法。 - 前記二次元パッドアレイの少なくとも1つのパッドと前記キャリア基板の導電性パッドとの間にワイヤボンドを延在させるステップをさらに含む請求項20に記載の方法。
- 少なくとも、前記ランドアレイの前記ランドと、前記ワイヤボンドと、前記導電性パッドとを、誘電材料で覆うステップをさらに含む請求項20に記載の方法。
- 2つの半導体ダイを備えるために、前記少なくとも1つの半導体ダイを選択するステップと、
一方の半導体ダイの裏面を前記インターポーザ基板に取り付けるステップと、
他方の半導体ダイの裏面を前記一方の半導体ダイの前記活性面に、前記第1の半導体ダイの前記ボンドパッドが露出されるように、取り付けるステップと、
をさらに含む請求項13又は14に記載の方法。 - 前記一方の半導体ダイおよび前記他方の半導体ダイのそれぞれの前記ボンドパッドを前記複数の端子にワイヤボンドで電気的に接続するステップをさらに含む請求項23に記載の方法。
- 前記インターポーザ基板への前記少なくとも1つの半導体ダイの取り付けおよび前記複数の端子への前記複数のボンドパッドの接続の後であって、追加構造の組み付け前に、前記少なくとも1つの半導体ダイのテストを実施するステップをさらに含む請求項13又は14に記載の方法。
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2005
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- 2006-08-08 KR KR1020087006100A patent/KR100959957B1/ko active IP Right Grant
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TW201110280A (en) | 2011-03-16 |
WO2007086937A3 (en) | 2008-06-19 |
KR100959957B1 (ko) | 2010-05-27 |
EP1929540A2 (en) | 2008-06-11 |
US8796836B2 (en) | 2014-08-05 |
TW200739835A (en) | 2007-10-16 |
US20070045818A1 (en) | 2007-03-01 |
EP1929540B1 (en) | 2014-07-16 |
TWI353656B (en) | 2011-12-01 |
US9355992B2 (en) | 2016-05-31 |
SG130070A1 (en) | 2007-03-20 |
US20140342476A1 (en) | 2014-11-20 |
WO2007086937A2 (en) | 2007-08-02 |
JP2009506534A (ja) | 2009-02-12 |
TWI353046B (en) | 2011-11-21 |
KR20080039986A (ko) | 2008-05-07 |
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