TWI428995B - 板上縮小封裝 - Google Patents

板上縮小封裝 Download PDF

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TWI428995B
TWI428995B TW098135516A TW98135516A TWI428995B TW I428995 B TWI428995 B TW I428995B TW 098135516 A TW098135516 A TW 098135516A TW 98135516 A TW98135516 A TW 98135516A TW I428995 B TWI428995 B TW I428995B
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die
pad
substrate
integrated circuit
circuit package
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TW098135516A
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TW201025464A (en
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Kian Teng Eng
Rodel Manalac
Teck Wah Park
Richard Te Gan
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United Test & Assembly Ct Lt
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Description

板上縮小封裝
板上晶片(COB)封裝一般包括一晶粒，該晶粒被直接安裝於且係電連接至一由印刷電路板材料製成之基板上。較之於四方扁平無引腳(QEN)封裝，該PCB基板之成本將低於該QEN之該銅/合金42引線架基板之成本。
該COB封裝係由一覆頂式材料封止以保護該晶粒及焊線免受環境之影響。為了封止一COB封裝，採取一覆頂式施配製程。例如，該覆頂式被作為一團而施配覆於該封裝上。該覆頂式材料覆蓋該晶粒及佈線內連線。
然而，由於該覆頂式材料之填充物含量低，故而會影響該COB封裝之可靠性。該覆頂式施配製程涉及對該材料進行逐單元地施配，而此施配方式效率不高。該覆頂式施配製程亦導致一封裝產生一彎曲或不平坦表面。
對於習知之COB封裝，由於在該COB封裝被安裝於一板上之後，其無法獲得外部焊盤襯墊來實現至一測試裝置之連接，故無法將之作為一板上位級封裝而加以測試。
自上文論述可以看出，需要改良式封裝及封裝技術。
本發明揭示一種形成一裝置之方法，該方法包括提供一其之一第一表面上具有一晶粒附接區之印刷電路板基板。該方法亦包括將一晶粒附接至該晶粒附接區。該晶粒係電耦合至設置於該晶粒附接區的周邊的該第一表面上之若干第一焊盤襯墊。形成於一目標區域中之蓋罩係藉由頂澆進模口製程而形成以使該蓋罩具有一平整之表面。該蓋罩覆蓋該晶粒且使至少該等第一焊盤襯墊暴露。
在另一實施例中，提供一裝置，該裝置包含一印刷電路板基板，且該基板之一第一表面上具有一晶粒附接區。一晶粒被設置於該晶粒附接區中。該晶粒係電耦合至設置於該晶粒附接區的周邊之該第一表面上之若干第一焊盤襯墊。該裝置亦包含一形成於一目標區域中之蓋罩，該蓋罩係藉由頂澆進模口製程形成以使該蓋罩具有一平整之表面。該蓋罩覆蓋該晶粒且使該等頂部焊盤襯墊暴露。
在又一實施例中，揭示一種形成一裝置之方法，該方法包括提供一其之一第一表面上具有一晶粒附接區之基板。該方法亦包括將若干第一焊盤襯墊設置於該晶粒附接區的周邊之該第一表面上。當一晶粒被附接至該晶粒附接區時，其係電耦合至該等第一焊盤襯墊。當一晶粒被附接至該晶粒附接區時，一頂澆進模口製程在一目標區域中產生一蓋罩。所形成之該蓋罩具有一平整表面。該蓋罩覆蓋該晶粒且使至少該等第一焊盤襯墊暴露。
透過參考下文描述及該等附加圖式，本文所揭示之本發明之此等及其他目的以及優點及特徵將顯而易見。此外，應瞭解，本文所描述之各種實施例之該等特徵並不互斥且可以各種組合及排列之形式而存在。
在該等圖式中，相同的參考字元一般指示貫穿於該等不同視圖中之相同部分。同時，該等圖式未必按實際比例繪製，而是主要在於強調對本發明之一些原則之闡明。在下文描述中，將參考下列圖式來描述本發明之各種實施例。
本文之實施例係一般關於用於晶片或IC(積體電路)之半導體封裝。各種類型之晶片或IC可被封裝。例如，該IC可為一記憶體裝置，例如一動態隨機存取記憶體(DRAM)、一靜態隨機存取記憶體(SRAM)及包括可程式化唯讀記憶體(PROM)及快閃記憶體在內之各種類型之非揮發記憶體、一光電裝置、一邏輯裝置、一通信裝置、一數位信號處理器(DSP)、一微控制器、一系統單晶片以及其他類型之裝置。該IC可被包含於諸如手機、電腦、個人數位助理之各種產品或其他類型之合適的產品中。
圖1a-b顯示一封裝100之一實施例之橫截面圖及俯視圖。該封裝包含一基板120，其具有頂主表面及底主表面123及124。一般地，該基板為矩形以形成一矩形裝置。亦可使用其他形狀。該基板可為一單一層基板或一多層基板。對於一多層基板，不同之層可加以層壓或堆積。可使用各種材料來製作該基板。
在一實施例中，該基板包括一印刷電路板(PCB)基板。該PCB基板包括例如FR-4或FR-5。亦可使用其他類型之PCB材料。或者，亦可使用其他類型之基板。該頂主表面包含一晶粒附接區128。該晶粒附接區之周邊設置有若干結合指狀物132。例如，將該等結合指狀物配置於該晶粒附接區之周圍。該等結合指狀物包括例如銅。亦可使用其他類型之傳導性材料。該等結合指狀物可塗佈有鎳、金、 銀或其等之組合以改良有待形成於該等指狀物上之焊線之可結合性。該等結合指狀物亦可塗佈有一種抗氧化材料，例如有機保焊劑。亦可使用其他類型之抗氧化材料。
在一實施例中，頂部焊盤襯墊144係沿該基板之該頂周邊而形成；而底部焊盤襯墊148係沿該基板之該底部周邊而形成。在一實施例中，該基板之該等側上設置有若干堡狀引線142。該等堡狀引線自該基板之頂面延伸至該基板之底面，以將該等頂部焊盤襯墊電耦合至該等底部焊盤襯墊。該等堡狀引線係可由一種傳導性材料製成。在一實施例中，該等堡狀引線包括銅。亦可使用其他類型之傳導性材料。
該基板之該頂面上設置有若干頂部導電跡線138。該等頂部導電跡線將該等結合指狀物電耦合至該等頂部焊盤襯墊。例如，頂部導電跡線將該等結合指狀物電耦合至個別頂部焊盤襯墊。該等導電跡線係可由一種傳導性材料製成。在一實施例中，該等導電跡線包括銅。亦可使用其他類型的傳導性材料。該等導電跡線係可塗佈有一種絕緣材料，例如，焊錫掩膜。
在該基板的該底面，該等底部焊盤襯墊係沿該基板之該周邊而形成。該等底部焊盤襯墊作為該封裝之外部連接件，以將該封裝電耦合至一外部裝置。在該基板之頂面，該等頂部焊盤襯墊係沿該基板的周邊而形成。該等頂部焊盤襯墊提供至測試裝置之入口(尤其是當該封裝被安裝於一板上時)，以驗證該等線與該晶粒之間的電連接。可藉由將該等底部焊盤襯墊焊接至一板上以將該封裝安裝於該板上。該等頂部焊盤襯墊及底部焊盤襯墊及堡狀引線之另一功能在於，可藉由夾持連接將該封裝安裝於該板上。
提供一半導體晶粒110。該半導體晶粒包括主動主表面及非主動主表面。該主動表面包括(例如)結合墊以提供接達至該晶粒之內部電路。在一實施例中，該非主動表面係安裝於該基板之該晶粒附接區上。在一實施例中，使用一種黏合劑115來附接該晶粒。該黏合劑可(例如)為環氧樹脂。黏性環氧樹脂之實例包括Ablestik 2025D及Yiztech N7728。包括膠帶在內之其他黏合劑也可以是有用的。
在一實施例中，提供焊線152。該等焊線將該等結合指狀物電耦合至該晶粒上之該等結合墊。例如，該等焊線將該等結合指狀物電耦合至該晶粒上個別之結合墊。焊線152較佳包括銅線。使用銅線則有助於使用(例如)小於50um x 50um之較小結合墊。亦可使用其他類型之導線，例如金線或鋁線。
該封裝設有一蓋罩180。在一實施例中，該蓋罩封止該半導體晶粒110及該等焊線152。該蓋罩可(例如)包括一封膠化合物。可使用各種類型之封膠化合物，例如環氧樹脂。如所示，該蓋罩覆蓋該等結合指狀物之設置有該焊線之部分。當該封裝被安裝於板上時，使該等頂部焊盤襯墊暴露則可簡易地對該封裝進行測試。若無需執行該測試，則該蓋罩可覆蓋該基板之整個頂面。
根據一實施例，該蓋罩包括一平坦或平整之表面184。如所示，該蓋罩包括若干側壁182，其等幾乎垂直該蓋罩之該頂面。例如，該等側壁相對於該蓋罩之該水平頂面垂直。或者，如圖2a-b所示，該蓋罩之該等側壁282係傾斜。該等側壁之角度θ可為例如約15°至45°。亦可採取其他側壁角度。提供一平整表面便於對該封裝做標示。
根據一實施例，設置該蓋罩並不會損壞該封裝。例如，該蓋罩係藉由頂澆進模口模製製程形成，在該製程中，該封膠化合物係自該模之頂部而非一側模口而噴射。如若該封膠化合物係藉由一側模口模製製程而噴射，則該封膠化合物將流動至該目標區域之外。例如，該封膠化合物將流過該等導電跡線及頂部焊盤襯墊，而這會對此等組件造成損壞。
在其他實施例中，該晶粒110可包括一倒裝晶片，如圖2c所示。該倒裝晶片包括例如設置於一主動表面上之若干晶粒凸塊154。如所示，該等晶粒凸塊被設置成鄰近該晶粒之周邊。亦可採用其他晶粒凸塊組態。該等晶粒凸塊被耦合至設置於該晶粒區域中之基板上之個別接觸墊。可提供電接觸線來將該等接觸墊電耦合至該基板之該表面上之焊盤襯墊。
圖3a-b及4a-b顯示一封裝100之其他實施例之橫截面圖及俯視圖。該等封裝相似於圖1a-b及圖2a-b中所描述之該等封裝，只不過該基板120有所不同。在一實施例中，該基板包括通孔342而非堡狀引線。該等通孔被設置於該基板內且延伸穿過該底面及頂面123及124。例如，該等通孔被設置近於該基板之周邊。在一實施例中，該等通孔被配置於該基板之周圍。該等通孔使該頂部焊盤襯墊與底部焊盤襯墊電耦合。
參見圖3a-b，該蓋罩180包含一具有若干垂直側壁182之平整頂面。或者，該蓋罩180可包含若干傾斜側壁282，如圖4a-b所示。
在其他實施例中，該等焊盤襯墊可被配置成單列之焊盤襯墊或多列之焊盤襯墊。例如，一基板120可具有被配置成第一列及第二(雙)列之焊盤襯墊。例如，該等焊盤襯墊被設置於該基板之周邊上。將該等焊盤襯墊構形成其他數目之列亦是有用的。在一實施例中，該等焊盤襯墊被耦合至被設置於該晶粒附接區周圍之結合指狀物132。該等結合指狀物被電耦合至一晶粒。該等結合指狀物被配置成一單列之結合指狀物。將該等結合指狀物構形成其他數目之列亦是有用的。導電跡線138將該等頂部焊盤襯墊耦合至該等結合指狀物。
在一實施例中，該等焊盤襯墊被耦合至該等通孔，而該等通孔被耦合至底部焊盤襯墊。將焊盤襯墊耦合至堡狀引線亦是有用的。在如圖4c所示之另一實施例中，該基板120可包含若干圍繞該晶粒附接區128之焊盤襯墊。該等焊盤襯墊係藉由例如導電跡線而耦合至結合指狀物。該等焊盤襯墊被耦合至通孔342及堡狀引線142。例如，一列焊盤襯墊可被耦合至該等通孔，而其他列焊盤襯墊則被耦合至堡狀引線。在一實施例中，該第一列中之最鄰近該晶粒附接區之焊盤襯墊被耦合至該等通孔，而該第二列中之該等焊盤襯墊被耦合至該等堡狀引線。在其他實施例中，在該基板之相對側上之焊盤襯墊列之數目也可不盡相同。例如，該基板之該頂面於該周邊可具有單列焊盤襯墊，而該基板之該底面於該周邊可具有雙列焊盤襯墊。亦可採用其他組態之焊盤襯墊、通孔、堡狀引線及/或結合指狀物。圖5顯示一封裝500之另一實施例。該封裝包含一基板120。如所示，該基板包括複數個通孔342，該等通孔係圍繞該基板之該周邊而設置。該等通孔自該基板之頂面延伸至該基板之該底面124。在一實施例中，該等通孔被圍繞該基板之該周邊而設置。在另一實施例中。設於該基板之該等側處的並非通孔而是堡狀引線。在又一實施例中，該基板可包含堡狀引線與通孔之一組合。該頂面上之頂部導電跡線提供自該等外部焊盤襯墊至該晶粒之內部電路之互連，如上文已述。
該晶粒係可藉由焊線而連接至該等結合指狀物。可以一蓋罩將晶粒及焊線加以封止以保護其等免受環境之影響。在其他實施例中，該晶粒可包括一倒裝晶片，該倒裝晶片係藉由該晶粒的主動表面上之晶粒凸塊而連接至該基板上的基板焊墊。對於此等應用，該晶粒係由一蓋罩所封止以免受環境之影響。例如，該蓋罩包括一具有垂直側壁或傾斜側壁之平坦頂面。
在一實施例中，該基板之該底面包含一散熱片470。例如，該散熱片被設置於該底面上的一對應於該頂面上之該晶粒附接區之區域中。散熱片設置於其中之該區域不存在外部接點。在一實施例中，該散熱片包括一種熱消散材料，例如銅。亦可使用其他類型之熱消散或導熱材料。例如，該散熱片促進熱自該晶粒消散至一外表面黏著技術(SMT)模組。
圖6顯示一封裝600之又一實施例。該封裝包含一基板120，且該基板120之例如周邊設置有複數個通孔342。該等通孔自該基板之該頂面123延伸至該基板之底面。在一實施例中，該等通孔被圍繞該基板之該周邊而設置。在其他實施例中，可以堡狀引線代替通孔而設置於該基板之該等側處。在又一實施例中，該基板可包含堡狀引線與通孔之一組合。該頂面上之頂部導電跡線提供自該等外部焊盤襯墊至該晶粒之內部電路之互連，如上文已述。
該晶粒係可藉由焊線而連接至該等結合指狀物。可以一蓋罩封止該晶粒及焊線，以使其等免受環境之影響。在其他實施例中，該晶粒可包括一倒裝晶片，該晶片係藉由該晶粒的主動表面上之晶粒凸塊而連接至該基板上之基板焊墊。對於此等應用，該晶粒係由一蓋罩所封止，以免受環境之影響。如所示，該蓋罩包括一具有若干傾斜側壁282之平坦之頂面。或者，該蓋罩之一平坦頂面具有若干垂直之側壁。
在一實施例中，該基板之該頂面設有至少一個被動組件675。如所示，該頂面設有兩個被動組件。亦可對該封裝設其他數目之被動元件。例如，該等被動元件可為電阻器、電容器或其等之一組合。可對該等被動元件加以選擇使之可強化該封裝之電氣性能。如所示，該等被動組件被設置於該蓋罩之外側。亦可將該等被動組件設於該蓋罩之內或於該蓋罩之內側及外側兼設。
圖7a-c顯示一封裝之一封止製程。參見圖7a，提供一封裝100。該封裝包含一具有頂面及底面123及124之基板120。在一實施例中，該基板包括一PCB。亦可使用其他類型之基板。一晶粒110被附接至界定於該頂面123上之一晶粒附接區128。該晶粒係使用(例如)一黏合劑而安裝至該晶粒附接區。焊線152將該等晶粒結合墊電耦合至該基板的頂面上之結合指狀物。該頂面上之頂部導電跡線提供自該等外部焊盤襯墊至該等結合指狀物之互連且繼而使該等外部焊盤襯墊與該晶粒之內部電路互連。
在其他實施例中，該封裝可包含一具有若干晶粒凸塊之晶粒，該等晶粒凸塊與該晶粒附接區上之基板焊墊配對。在又一實施例中，該封裝可包含該基板之底面上之一散熱片及/或該基板之該頂面上之若干被動組件。其他類型之封裝也是有用的。
該封裝係設置於一封膠化合物噴射系統中。該噴射系統包括一噴射單元790。在一實施例中，該噴射單元包括一耦合至一模件794之噴射器792。該模件包含該蓋罩之所需形狀。例如，如所示，該模件包含一具有一平坦頂面及若干垂直側面之矩形模件。此一形狀產生一具有一平坦之頂面及若干垂直側壁之蓋罩。其他類型之模件也是有用的。例如，該等側面可相對於該平坦之表面傾斜。
根據一實施例，該噴射器係耦合至該模件之一頂面796。例如，該噴射器被耦合至該模件之該頂面之一中心附近。亦可將該噴射器耦合於該模件之該頂面之其他位置處。將該噴射器耦合於該模件之該頂面會產生一頂澆進模口噴射單元。
參見圖7b，該噴射單元被降低至該封裝上的位置。例如，該噴射器被降低，使得該模件覆蓋該晶粒及焊線且不覆蓋該等焊盤襯墊。當在適當位置時，該噴射單元經致動以使該噴射器將封膠化合物噴射至該模件中。
在圖7c中，上述製程繼續。例如，在該封膠化合物經由冷卻而已充分固化之後，升高該噴射單元。該封膠化合物在晶粒及焊線之上形成一蓋罩，從而完成該封止製程。
可同時執行該封止製程。例如，可一次封止複數個封裝。這可藉由提供一其上裝配有複數個晶粒之載體基板或PCB而達成。該噴射單元一次封止複數個晶粒。隨後，對該載體基板加以處理，以將之切單成若干個別封裝。該切單係可藉由例如鋸切或衝壓切單來達成。
如上所述，該晶粒係使用一改良模件設計而得以封止。在一實施例中，該晶粒係使用一頂澆進模口模製製程而得以封止。頂澆進模口模製製程具有若干優點。例如，該頂澆進模口模製製程使該封止本體之頂面平坦，從而對之進行油墨標記時，油墨標記不會扭曲變形。另一優點在於，較之於習知的用於COB封裝之液體封止技術，諸如覆頂式 施配及印刷/真空印刷封止，頂澆進模口模製法使產出量既高又可靠。例如，一頂澆進模口模製法可同時將多個晶粒封止於一載體基板條上，而覆頂式施配每次僅封止一個晶粒。
此外，使用該封膠化合物比使用液體封止材料可達成更高封裝可靠性及性能。例如，使用封膠化合物轉注成型達到良好蓋罩厚度控制，且減少因封膠化合物之較低收縮程度及吸水量而造成的陣列翹曲。
此外，該封膠化合物之較低CTE(熱膨脹係數)特性使得該封裝可輕易地與銅焊線接合整合，此與當前之COB封裝技術相比，可提供一可能較小的封裝面積、降低成本方案及較高的可靠性能。此外，藉由實施銅焊線接合，本封裝製程可克服細間距接合之困難且亦造成較低的裝配成本。藉由使用該PCB板代替銅/合金42引線架，此將大大降低所需之加工成本及前置時間。此外，亦可節省原物料。本封裝可經鋸切單或衝壓切單，此將給予額外彈性。
在不脫離本發明之精神或主要特性下，可以其他特定形式來具體化本發明。因此，上文之實施例自各方面而言均在於解析而非限制本文所描述之發明。本發明之範圍僅由申請專利範圍而非上文描述所指定，所有屬於申請專利之意義及其等效範圍內之變化係包含於申請專利範圍內。
100‧‧‧封裝
110‧‧‧半導體晶粒
115‧‧‧黏合劑
120‧‧‧基板
123‧‧‧頂主表面
124‧‧‧底主表面
128‧‧‧晶粒附接區
132‧‧‧結合指狀物
138‧‧‧頂部導電跡線
142‧‧‧堡狀引線
144‧‧‧頂部焊盤襯墊
148‧‧‧底部焊盤襯墊
152‧‧‧焊線
154‧‧‧晶粒凸塊
180‧‧‧蓋罩
182‧‧‧側壁
184‧‧‧平整表面
282‧‧‧側壁
342‧‧‧通孔
470‧‧‧散熱片
500‧‧‧封裝
600‧‧‧封裝
675‧‧‧被動組件
790‧‧‧噴射單元
792‧‧‧噴射器
794‧‧‧模件
796‧‧‧頂面
圖1a-b及圖2a-b顯示一封裝之各種實施例之橫截面圖及俯視圖； 圖2c顯示一倒裝晶片；圖3a-b及圖4a-b顯示一封裝之各種實施例之橫截面圖及俯視圖；圖4c顯示一基板之另一實施例；圖5-6顯示一封裝之其他實施例；及圖7a-c顯示形成一封裝之一製程。
100．．．封裝
110．．．半導體晶粒
120．．．基板
123．．．頂主表面
128．．．晶粒附接區
132．．．結合指狀物
138．．．頂部導電跡線
152．．．焊線
180．．．蓋罩

Claims (37)

  1. 一種形成一積體電路封裝之方法，其包括：提供一基板，該基板具有一第一平面主表面、一第二平面主表面以及直接設置於該第一平面主表面上的一晶粒附接區；將一晶粒附接於該晶粒附接區中，其中該晶粒被電耦合至若干第一焊盤襯墊，該等第一焊盤襯墊具有直接設置於該第一平面主表面上並平行於該晶粒附接區之周邊之該基板之該第一平面主表面的一方向的若干底部表面；提供若干外部接點，其具有直接位於該基板之該第二平面主表面上的若干底部表面；於該等第一焊盤襯墊之該等底部表面及該等外部接點之間提供若干互連，其中該等第一焊盤襯墊、該等外部接點以及該等互連係有區別的連接特徵；及在一目標區域中形成一蓋罩，其中該蓋罩覆蓋該晶粒且使至少該等第一焊盤襯墊暴露。
  2. 如請求項1之方法，其中該晶粒係藉由焊線而被電耦合至若干結合指狀物，該等結合指狀物被耦合至該等第一焊盤襯墊。
  3. 如請求項2之方法，其中該蓋罩覆蓋該等焊線及該等結合指狀物之一部分。
  4. 如請求項3之方法，其中該蓋罩係由一頂澆進模口製模製程所形成，該頂澆進模口製模製程防止蓋罩材料流出 該目標區域，該蓋罩材料之流出會損壞該封裝。
  5. 如請求項1之方法，其中該晶粒包括一倒裝晶片。
  6. 如請求項5之方法，其中該蓋罩係由一頂澆進模口製模製程所形成，該頂澆進模口製模製程防止蓋罩材料流出該目標區域，該蓋罩材料之流出會損壞該封裝。
  7. 如請求項1之方法，其中該蓋罩係由一頂澆進模口製模製程所形成，該頂澆進模口製模製程防止蓋罩材料流出該目標區域，該蓋罩材料之流出會損壞該封裝。
  8. 如請求項1之方法，其中：該等互連包括設置於該基板邊緣上的堡狀引線。
  9. 如請求項1之方法，其中：該等互連包括延伸穿過該基板之該第一平面主表面及該第二平面主表面的若干通孔。
  10. 如請求項1之方法，其中：第一焊盤襯墊經組態為圍繞該晶粒附接區之至少第一列及第二列；且該等第一焊盤襯墊被耦合至具有若干通孔或堡狀引線的該等互連。
  11. 如請求項10之方法，其中該等第一焊盤襯墊被耦合至具有若干通孔及堡狀引線的該等互連。
  12. 如請求項10之方法，其中：該第一列之該等焊盤襯墊被耦合至具有若干通孔的該等互連；且該第二列之該等焊盤襯墊被耦合至具有若干堡狀引線 的該等互連。
  13. 如請求項12之方法，其中該第一列較該第二列靠近該晶粒附接區。
  14. 如請求項1之方法，其中若干第二焊盤襯墊被設置於該基板之該第二平面主表面上。
  15. 如請求項14之方法，其中該等第二焊盤襯墊係作為該等外部接點。
  16. 一種積體電路封裝，其包括：一基板，該基板具有一第一平面主表面、一第二平面主表面以及直接置於該第一平面主表面上的一晶粒附接區；一晶粒，設置於該晶粒附接區中，其中該晶粒被電耦合至若干第一焊盤襯墊，該等第一焊盤襯墊具有直接設置於該第一平面主表面上並平行於該晶粒附接區之周邊之該基板之該第一平面主表面的一方向的若干底部表面；若干外部接點，其具有直接設置於該基板之該第二平面主表面上的若干底部表面；若干互連，其係被設置於該第一焊盤襯墊之該等底部表面與該等外部接點之間，其中該等第一焊盤襯墊，該等外部接點以及該等互連係有區別的連接特徵；及一蓋罩，其形成於一目標區域中，其中該蓋罩覆蓋該晶粒且使該等第一焊盤襯墊暴露。
  17. 如請求項16之積體電路封裝，其中該該蓋罩係由一頂澆 進模口製模製程所形成，該頂澆進模口製模製程使該蓋罩之材料保留於該目標區域中以防止損壞該積體電路封裝。
  18. 如請求項16之積體電路封裝，其中該晶粒包括一倒裝晶片晶粒。
  19. 如請求項16之積體電路封裝，其中該晶粒係以焊線經由結合指狀物而被耦合至該等第一焊盤襯墊。
  20. 如請求項19之積體電路封裝，其中該蓋罩覆蓋該等焊線及該等結合指狀物之一部分。
  21. 如請求項20之積體電路封裝，其中該蓋罩係由一頂澆進模口製模製程所形成，該頂澆進模口製模製程使該蓋罩之材料保留於該目標區域中以防止損壞該積體電路封裝。
  22. 如請求項16之積體電路封裝，其中：該等互連包括設置於該基板之邊緣上的若干堡狀引線。
  23. 如請求項16之積體電路封裝，其中：該等互連包括延伸穿過該基板之該第一平面主表面及該第二平面主表面的若干通孔。
  24. 如請求項16之積體電路封裝，其中該第一焊盤襯墊被組態於環繞該晶粒附接區的至少第一列及第二列中；以及該第一焊盤襯墊被耦合具有若干通孔或堡狀引線的該等互連。
  25. 如請求項24之積體電路封裝，其中該第一焊盤襯墊被耦合至具有若干通孔及堡狀引線的該等互連。
  26. 如請求項24之積體電路封裝，其中：該第一列之該等焊盤襯墊被耦合至若干通孔；以及該第二列之該等焊盤襯墊被耦合至若干堡狀引線。
  27. 如請求項26之積體電路封裝，其中該第一列比該第二列更接近該晶粒附接區。
  28. 如請求項16之積體電路封裝，其包括若干第二焊盤襯墊，該等第二焊盤襯墊被設置於該基板之該第二平面主表面上，該等第二焊盤襯墊係作為該等外部接點。
  29. 如請求項16之積體電路封裝，其包括一散熱器，該散熱器係被設置於該基板之該第二平面主表面上。
  30. 如請求項29之積體電路封裝，其中該散熱器係被設置於該第二平面主表面上相對於該晶粒附接區的一區域，且該區域缺乏外部接點。
  31. 如請求項16之積體電路封裝，其包括至少一個位於該第一平面主表面上的被動元件。
  32. 如請求項16之積體電路封裝，其中當該積體電路封裝被安裝於一板之上時，被暴露之該第一焊盤襯墊使該積體電路封裝能夠從該第一平面主表面被測試。
  33. 一種積體電路封裝，其包含：一基板，其具有一第一平面主表面、一第二平面主表面以及直接設於該第一平面主表面上的一晶粒附接區；一晶粒，其被設置於該晶粒附接區中，其中該晶粒係 被電耦合至若干第一焊盤襯墊，該等第一焊盤襯墊僅被直接設置於該第一平面主表面上並平行於該晶粒附接區之周邊之該基板之該第一平面主表面的一方向；以及一蓋罩，其形成於一目標區域中，其中該蓋罩覆蓋該晶粒且使該等第一焊盤襯墊暴露。
  34. 如請求項33之積體電路封裝，其中：該等第一焊盤襯墊被組態於環繞該晶粒附接區的至少第一列及第二列中，其中該等第一焊盤襯墊之該第一列及該第二列係平行於該晶粒附接區之該周邊；以及該等第一焊盤襯墊被耦合至若干互連，該等互連係設置於該等第一焊盤之若干底部表面及若干外部接點之若干底部表面之間，其中該等外部接點係設置於該基板之該第二平面主表面之上，其中該等第一焊盤襯墊、該等互連以及該等外部接點係有區別的連接特徵。
  35. 如請求項34之積體電路封裝，其中該第一列比該第二列更接近該晶粒附接區。
  36. 如請求項33之積體電路封裝，其包括：若干導電跡線，其設置於該基板之該第一平面主表面上，該等導電跡線係用於將若干結合指狀物耦合至該等第一焊盤襯墊，其中該晶粒係利用若干焊線而耦合至該等結合指狀物，且該等導電跡線不被該蓋罩覆蓋。
  37. 如請求項33之積體電路封裝，其中該基板包含一印刷電路板(PCB)基板。
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CN101944492A (zh) 2011-01-12
US20100102436A1 (en) 2010-04-29

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