CN101944492A - 板上收缩封装 - Google Patents

板上收缩封装 Download PDF

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Publication number
CN101944492A
CN101944492A CN2009102530891A CN200910253089A CN101944492A CN 101944492 A CN101944492 A CN 101944492A CN 2009102530891 A CN2009102530891 A CN 2009102530891A CN 200910253089 A CN200910253089 A CN 200910253089A CN 101944492 A CN101944492 A CN 101944492A
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pad
die
pipe cap
tube core
substrate
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黄健庭
R·玛纳拉科
白德华
R·T·甘
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United Test and Assembly Center Ltd
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United Test and Assembly Center Ltd
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Publication of CN101944492A publication Critical patent/CN101944492A/zh
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Abstract

本发明涉及板上收缩封装。公开了一种形成器件的方法。该方法包括一印刷电路板基板,在该基板的第一表面上具有管芯附着区。该方法还包括将管芯附着到该管芯附着区。该管芯电耦合到布置在该管芯附着区外围的第一表面上的第一焊盘。通过顶浇口工艺将一管帽形成在目标区域中以形成具有平坦表面的管帽。该管帽覆盖该管芯并且至少使第一焊盘暴露。

Description

板上收缩封装
背景技术
板上芯片(COB)封装体通常具有直接安装并且电连接于由印刷电路板材料制成的基板上的管芯。当与四方扁平无引线(QFN)封装体相比时,PCB基板的成本低于QFN的铜/合金42引线框基板更低。
COB封装体由圆顶封装体材料密封以保护管芯和接合线免于受到环境的影响。为了密封COB封装体,采用圆顶封装滴涂工艺。例如。圆顶封装体材料被滴涂为在封装上的一个圆珠。圆顶封装材料覆盖管芯和互联引线。
然而,圆顶封装材料由于其低填充剂含量而影响了COB封装体的可靠性。圆顶封装滴涂工艺涉及一个单元接着一个单元地滴涂该材料,效率不高。圆顶封装滴涂工艺还导致封装体具有曲面或者非平直表面。
在COB封装体安装到板上后,由于没有能用于连接连接到测试设备的外部焊盘,传统的COB封装体不提供作为板级上封装体水平的测试。
根据前面的讨论可知,需要改进的封装体以及封装技术。
发明内容
公开了一种形成器件的方法。该方法包括提供一印刷电路板基板,在该基板的第一表面上具有管芯附着区。该方法还包括将管芯附着到该管芯附着区。该管芯电耦合到布置在该管芯附着区外围在该第一表面上的第一焊盘。通过顶浇口工艺将一个管帽形成在目标区域中以形成具有平坦表面的管帽。该管帽覆盖该管芯并且使至少第一焊盘暴露。
在另一实施例中,示出了一种器件。该器件包括一印刷电路板,在该电路板的第一表面上具有管芯附着区。一管芯布置在该管芯附着区。该管芯电耦合到布置在该管芯附着区外围在该第一表面上的第一焊盘。该器件还包括通过顶浇口工艺在目标区域中形成的管帽,以形成具有平坦表面的管帽。该管帽覆盖该管芯并且至少留下暴露的顶部焊盘。
在又一实施例中,公开了一种形成器件的方法。该方法包括提供一衬底,在该衬底的第一表面上具有管芯附着区。该方法还包括在该管芯附着区歪围在该第一表面上布置第一焊盘。当管芯附着到该管芯附着区时,其电耦合到该第一焊盘。当管芯附着到该管芯附着区时,通过顶浇口工艺在目标区域中形成一管帽。形成该管帽制造出具有平坦表面的管帽。该管帽覆盖该管芯并且使至少第一焊盘暴露。
参照下面的说明书及附图,这些和其他目的,连同这里所揭示的本发明的优点和特点,将变得显而易见。而且,应当理解的是这里所讨论的各种实施例不是互斥的,并且可以以各种排列组合形式存在。
附图说明
在附图中,相同的附图标记在不同视图中一直表示相同的部分。而且,附图不一定是成比例的,相反,重点放在强调阐明本发明的原理。在下面的说明书中,将参照下面的附图描述本发明的各个实施例,其中:
图1a-b和图2a-b示出了封装体的各个实施例的截面图和顶视图;
图2c示出了一个倒装芯片;
图3a-b和图4a-b示出了封装体的各个实施例的截面图和顶视图;
图4c示出了基板的另一个实施例;
图5-6示出了封装体的其他实施例;以及
图7a-c示出了形成封装体的工序。
具体实施方式
实施例一般涉及用于芯片或集成电路的半导体封装体。各种类型的芯片或集成电路可以封装。例如,集成电路可以是存储器件,比如动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)以及各种非易失性存储器,包括可编程只读存储器(PROM)和闪存、光电器件、逻辑器件、通信器件、数字信号处理器、微控制器、片上系统、和其他类型的器件。集成电路可以用于各种产品中,如电话、计算机、个人数码助理或其他类型的适合产品。
图1a-b示出了封装体100的一个实施例的截面图和顶视图。该封装体包括具有顶部和底部主表面123和124的基板120。典型地,该基板包括一个矩形形状以形成矩形形状的器件。其他形状也是可以使用的。该基板可以是单层基板或多层基板。对于多层基板,可以将不同的层进行层压或组装。各种材料可以用来形成该基板。
在一个实施例中,基板由一印刷电路板(PCB)基板构成。该PCB基板,例如,由FR-4或FR-5构成。其他类型的PCB材料也是可以使用的。或者,可以使用其他类型的基板。顶部主表面包括一管芯附着区128。接合指132布置在该管芯附着区外围。例如,配置接合指以围绕该管芯附着区。该接合指,例如,由铜构成。其他类型的导电材料也是可以使用的。该接合指可以涂覆镍、金、银或它们的组合,以改善要形成在其上的焊接线的接合性。该接合指可以涂覆抗氧化的材料,例如有机可焊保护层(OSP)。其他类型的抗氧化材料也是可以使用的。
在一个实施例中,顶部焊盘沿着基板的顶部外围形成;底部焊盘沿着基板的底部外围形成。在一个实施例中,雉堞形(castellation)引线142布置在基板的边上。雉堞形引线从基板的顶面延伸到底表面以将顶部焊盘电耦合到底部焊盘。雉堞形引线可以由导电材料形成。在一个实施例中,雉堞形引线由铜构成。其他类型的导电材料也是可以使用的。
顶部导电迹线138布置在基板的顶面上。顶部导电迹线将接合指电耦合到顶部焊盘。例如,顶部导电迹线将接合指电耦合到各自的顶部焊盘。导电迹线可以由导电材料形成。在一个实施例中,导电迹线由铜构成。其他类型的导电材料的使用也是可以的。该导电迹线可以涂覆绝缘材料,例如,焊料掩膜。
在基板的底面上,底部焊盘沿着基板的外围形成。底部焊盘用来作为封装体的外部连接端以将封装体电耦合到外部设备。在基板的顶面上,顶部焊盘沿着基板的外围形成。顶部焊盘向测试设备提供通道,尤其是当封装体安装到电路板上时,以检验引线与管芯之间的电连接。封装体可以通过将底部焊盘焊接到电路板上的方式安装到电路板上。顶部和底部焊盘以及雉堞形引线的另一个功能是能够通过夹紧而使封装体安装到电路板上。
提供一半导体管芯110。半导体管芯包括有源和无源主表面。例如,有源表面包括接合焊盘以向管芯的内部电路提供通道。在一个实施例中,无源表面安装在基板的管芯附着区上。在一个实施例中,管芯是利用粘合剂115附着的。粘合剂可以是例如环氧树脂。粘合剂环氧树脂的例子包括Ablestik 2025D和Yiztech N7728。其他类型的粘合剂,包括胶带,也是可以使用的。
在一个实施例中,提供接合线152。接合线将接合指电耦合到管芯上的接合焊盘。例如,接合线将接合指电耦合到管芯上的各个接合焊盘。接合线152优选由铜构成。铜线的使用可以方便使用较小的焊接焊盘,例如,在50μm×50μm以下。其他类型的导电线,例如金线或铝线,也是可以使用的。
给封装体提供管帽180。在一个实施例中,管帽将半导体管芯110和接合线152密封。例如,管帽由模塑封料构成。可以使用各种类型的塑封材料,例如环氧树脂。如图所示,该管帽覆盖布置了接合线的接合指。使顶部焊盘暴露使得在将其安装到板上时对封装体的测试能够容易地进行。如果测试不需要进行,那么管帽可以覆盖基板的整个顶面。
根据一个实施例,管帽包括一平坦或平滑的表面184。如图所示,管帽包括侧壁182,其大约与管帽的顶面垂直。例如,侧壁相对于管帽的水平顶面是垂直的。或者,如图2a-b中所示,管帽的侧壁182为偏斜或倾斜的。侧壁的角θ,例如是,约15-45°。其他侧壁角也是可以使用的。提供平滑的表面方便封装体的制造。
根据一个实施例,提供管帽而不破坏封装体。例如,通过模塑封材从模具的顶部而不是侧壁注入的顶浇口模制工艺形成管帽。如果模塑封材由侧壁浇口模制工艺注入,那么模塑封材将流出目标区域。例如,模塑材料将流到导电迹线和顶部焊盘上,这可能损坏这些组件。
在其它实施例中,管芯110可以包括一倒装芯片,如图2c中所示。倒装芯片,例如,包括布置在有源表面上的管芯凸块154。如图所示,管芯凸块临近管芯的外围布置。其他凸块构造也是可以使用的。管芯凸块耦合到在基板的管芯区中的各个接触焊盘。可以提供电连接迹线以将接触焊盘电耦合到基板表面上的焊盘。
图3a-b和图4a-b示出了封装体100的其他实施例的截面图和顶视图。除基板120外,该封装体与在图1a b和图2a-b所述的封装体相似。在一个实施例中,基板包括通孔342而不是雉堞形引线。通孔布置在基板内并且延伸贯穿顶部和底面123和124。例如,通孔临近基板的外围布置。在一个实施例中,通孔环绕基板的外围布置。通孔将顶部和底部焊盘电耦合。
参见图3a-b,管帽180包括具有垂直侧壁182的平滑顶面。或者,管帽180可以包括倾斜的侧壁282,如图4a-b中所示。
在其他实施例中,焊盘可以布置为单列焊盘或多列焊盘。例如,基板120可以具有以第一和第二(双)列布置的焊盘。例如,焊盘布置在基板的外围。以其他的列数构建的焊盘也是可以使用的。在一个实施例中,焊盘耦合到布置在管芯附着区歪围的接合指132。接合指电耦合到管芯。接合指布置成单列接合指。以其他的列数构建的接合指也是可以使用的。导电迹线138将顶部焊盘耦合到接合指。
在一个实施例中,焊盘与耦合到底部焊盘的通孔耦合。将焊盘耦合到雉堞形引线也是可以使用的。在一个实施例中,如图4c中所示,基板120可以包括围绕管芯附着区128的焊盘。焊盘通过例如导电迹线耦合到接合指。焊盘耦合到通孔342和雉堞形引线142。例如,一列焊盘可以耦合到通孔而其他列焊盘耦合到雉堞形引线。在一个实施例中,紧邻管芯附着区的第一列焊盘耦合到通孔而其他列焊盘耦合到雉堞形引线。在其它实施例中,在基板背面的焊盘的列数可以不相同。例如,基板的顶面可以具有在外围的单列焊盘,而基板的底面可以具有在外围的双列焊盘。其他的焊盘、通孔、雉堞形引线和/或接合指的构造也是可以使用的。
图5示出了另一个实施例的封装体500。该封装体包括基板120。如图所示,该基板包括多个例如是布置在基板外围的通孔342。通孔从基板的顶面延伸到底面124。在一个实施例中,通孔围绕基板的外围配置。在另一个实施例中,代替通孔,雉堞形引线可以提供于基板的边上。在又一实施例中,基板可以包括雉堞形引线和通孔的组合。在顶面上的顶部导电迹线提供从外部焊盘到管芯的内部电路的互联,如上所述。
管芯可以由接合线连接到接合指。管芯和接合线可以由管帽密封,以保护它们不受环境影响。在其他实施例中,管芯可以包括通过在管芯的有源表面上的管芯凸块连接到基板焊盘的倒装芯片。对于这些应用,管芯由管帽来密封,以使其不受环境的影响。例如,管帽包括具有垂直或倾斜侧壁的平坦顶面。
在一个实施例中,基板的底面包括一散热器470。例如,散热器布置在底面上与顶面上的管芯附着区相对应的一个区域里。布置散热器的区域没有外部接触端。在一个实施例中,散热器由散热材料构成,比如铜。其他类型的散热或导热材料也是可以使用的。例如,散热器能够使热量从管芯散发到外部表面安装技术(SMT)模块。
图6示出了封装体600的又一实施例。该封装体包括具有多个例如布置在基板的外围的多个通孔342的基板120。通孔从基板的顶面123延伸到底面。在一个实施例中,通孔配置在围绕基板的外围。在其他实施例中,代替通孔,雉堞形引线可以提供于基板的边上。在又一实施例中,基板可以包括雉堞形引线和通孔的组合。在顶面上的顶部导电迹线提供从外部焊盘到管芯的内部电路的互联,如上所述。
管芯可以由接合线连接到接合指。管芯和接合线可以由管帽密封,以保护它们不受环境影响。在其他实施例中,管芯可以包括经由管芯的有源表面上的管芯凸块连接到基板焊盘的倒装芯片。针对这些应用,管芯由管帽来密封,以使其不受环境的影响。如图所示,管帽包括具有倾斜侧壁282的平坦顶面。或者,管帽可以是具有垂直侧壁、平坦顶面。
在一个实施例中,基板的顶面具有至少一个无源元件675。如图所示,顶面有两个无源元件。具有其他数目无源元件的封装体也是可以使用的。例如,无源元件可以是电阻器、电容器或它们的组合。如图所示,无源元件布置在管帽之外。无源元件在管帽之内或者是在管帽之内和之外的组合也是可以使用的。
图7a-c示出了密封一个封装体的方法的实施例。参见图7a,提供一封装体100。封装体包括具有顶面和底面123和124的基板120。在一个实施例中,基板包括PCB。其他类型的基板也是可以使用的。管芯110附着到限定在顶面123上的管芯附着区。管芯使用例如粘合剂安装到管芯附着区。接合线152将管芯焊盘电耦合到基板的顶面上的接合指。在顶面上的顶部导电迹线提供从外部焊盘到接合指,进而到管芯的内部电路的互联。
在其他实施例中,封装体可以包括具有管芯凸块的管芯,其中的凸块与芯片附着区上的基板焊盘配成对。在又一实施例中,封装体可以包括在基板的底面上的散热器和/或在基板的顶面上的无源元件。其他类型的封装体也是可以使用的。
该封装体布置在一个模塑封材注入系统中。该注入系统包括一注入单元790。在一个实施例中,该注入单元包括耦合到模具794的注入器792。模具包括管帽所需要的形状。例如,如图所示,模具包括具有平坦顶面和垂直侧壁的矩形模具。这种形状生产出具有平坦顶面和垂直侧壁的管帽。其他形状的模具也是可以使用的。例如,侧面可以相对于平坦表面倾斜。
根据一个实施例,注入器耦合到模具的顶面796。例如,注入耦合到模具的顶面的中心附件。在模具的顶面的其他位置耦合注入器也是可以使用的。在模具的顶面上耦合注入器生产出一顶浇口注入单元。
参见图7b,注入单元被降低位置到封装体上。例如,注入单元被降低以致模具覆盖管芯和接合线而不覆盖焊盘。当在适当的位置时,注入单元被激活以使注入器向模具中注入模塑封材。
在图7c中,该工艺继续。例如,在通过冷却使模塑封材充分固化后,升起注入单元。模塑封材在管芯和接合线上形成管帽,完成密封工艺。
密封工艺可以平行进行。例如,多个封装体可以同时密封。这可以通过提供在其上装配有多个管芯的承载基板或PCB来实现。注入单元一次密封多个管芯。其后,处理该载体基板以将其分割为单个封装体。这种分割可以用例如锯法或冲压分割法实现。
如上所述,管芯可以用修改的模式设计进行密封。在一个实施例中,管芯利用顶浇口模制工艺来密封。顶浇口模制工艺提供几个优点。例如,顶浇口模制工艺使密封体的顶面平坦,从而使油墨盖印可以进行而不会产生扭曲。另外一个优点是,对于COB封装而言,相对于常规的液体密封技术如液滴顶部滴涂和印刷/真空印刷密封,顶浇口模制工艺的产量更高和更可靠。例如,顶浇口模制工艺可以并行密封一个承载基板条带上的多个管芯,而液滴顶部滴涂一次只密封一个管芯。
此外,使用模塑封材比液体密封材料可以达到更高的封装可靠性和性能。例如,具有模塑封材的转移模具实现了优异的管帽厚度控制,并且由于模塑封材的较低缩水性和较低吸水性,减少了阵列的翘曲。
而且,模塑封材的较低的CTE特性使得封装体能够方便地与铜接合线集成,相对于当前的COB封装技术能够提供一个封装印脚可能更小、成本降低的解决方案以及更高的可靠性性能。而且,通过使用铜接合线,本发明的封装工艺可以克服小间距接合的挑战,并得到较低的装配成本。通过使用PCB板代替铜/合金42引线框,这将显著地减少加工成本和所需的生产周期。此外,也节省原材料。本发明的封装体可以被锯成或冲压成单个的,赋之以额外的灵活性。
本发明可以以其他具体形式体现而不脱离本发明的精神和基本特征。因此,在所有方面上,前面的实施例应被认为是说明性的而不是限制在此所描述的本发明。因而,本发明的范围由所附权利要求书,而非前面的说明书部分表明,落在权利要求书的等效方案的意义和保护范围内的所有改变皆应为本发明所涵盖。

Claims (20)

1.一种形成器件的方法,包括:
提供一印刷电路板基板,在其第一表面上具有管芯附着区;
将管芯附着到所述管芯附着区,其中所述管芯电耦合到布置在所述管芯附着区外围的第一表面上的第一焊盘;
通过顶浇口工艺将一管帽形成在目标区域中,以形成具有平坦表面的管帽,其中所述管帽覆盖所述管芯并至少使所述第一焊盘暴露。
2.如权利要求1的方法,其中所述管芯通过接合线电耦合于接合指,所述接合指耦合于所述第一焊盘。
3.如权利要求2所述的方法,其中所述管帽覆盖接合线以及接合指的一部分。
4.如权利要求3所述的方法,其中所述顶浇口工艺避免管帽材料流到目标区域外面而损坏所述封装体。
5.如权利要求1所述的方法,其中所述管芯包括一倒装芯片。
6.如权利要求5所述的方法,其中所述顶浇口工艺避免管帽材料流到目标区域外面而损坏所述封装体。
7.如权利要求1所述的方法,其中所述顶浇口工艺避免管帽材料流到目标区域外面而损坏所述封装体。
8.如权利要求1所述的方法,其中:
所述第一焊盘耦合到布置在所述基板边缘上的雉堞形引线;以及
所述雉堞形引线延伸穿过所述基板的第一和第二表面,所述雉堞形引线耦合到布置在所述基板的第二表面上的外部触点。
9.如权利要求1所述的方法,其中:
所述第一焊盘电耦合到延伸穿过所述基板的第一和第二表面的通孔;以及
所述通孔耦合到布置在所述基板的第二表面上的外部触点。
10.如权利要求1所述的方法,其中:
以至少第一和第二列围绕所述管芯附着区的方式构造第一焊盘;以及
所述第一焊盘耦合到所述通孔或所述雉堞形引线。
11.如权利要求10所述的方法,其中所述第一焊盘耦合到所述通孔和所述雉堞形引线。
12.如权利要求10所述的方法,其中所述第一列的焊盘耦合到所述通孔;以及
所述第二列的焊盘耦合到所述雉堞形引线。
13.如权利要求12所述的方法,其中所述第一列比所述第二列更接近所述管芯附着区。
14.如权利要求1所述的方法,其中所述第二焊盘布置在所述基板的第二表面上。
15.如权利要求14所述的方法,其中第二焊盘用作外部触点。
16.一种器件,包括:
印刷电路板基板,在其第一表面上具有管芯附着区;
布置在所述管芯附着区的管芯,其中所述管芯电耦合到布置在所述管芯附着区外围的第一表面上的第一焊盘;以及
通过顶浇口工艺在目标区域中形成的管帽,所述管帽具有平坦表面;所述管帽覆盖所述管芯而使顶部焊盘暴露。
17.如权利要求16所述的器件,其中所述浇口工艺使管帽的材料包含在目标区域中以避免损坏所述器件。
18.如权利要求16所述的器件,其中所述管芯包括一倒装芯片。
19.如权利要求16所述的器件,其中所述管芯通过接合指将接合线电耦合到所述第一焊盘。
20.一种形成器件的方法,包括:
提供一衬底,在其第一表面上具有管芯附着区;
在所述管芯附着区外围的第一表面上布置第一焊盘,其中当管芯附着到所述管芯附着区时,其电耦合到该第一焊盘;以及
当管芯附着到所述管芯附着区时,通过顶浇口工艺在目标区域中形成管帽,其中形成该管帽产生具有平坦表面的管帽,其中所述管帽覆盖所述管芯而至少使第一焊盘暴露。
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106024647A (zh) * 2016-06-14 2016-10-12 重庆切普电子技术有限公司 一种cob封装器件低成本生产工艺
CN106415825A (zh) * 2014-01-23 2017-02-15 株式会社电装 模塑封装
CN107170719A (zh) * 2017-05-17 2017-09-15 杭州士兰微电子股份有限公司 基板、封装结构及封装结构的制作方法
CN110120376A (zh) * 2019-04-30 2019-08-13 深圳市广和通无线股份有限公司 无针脚模块
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102010027313A1 (de) * 2010-07-16 2012-01-19 Osram Opto Semiconductors Gmbh Trägervorrichtung für einen Halbleiterchip, elektronisches Bauelement mit einer Trägervorrichtung und optoelektronisches Bauelement mit einer Trägervorrichtung
JP2015012158A (ja) * 2013-06-28 2015-01-19 株式会社デンソー 電子装置およびその電子装置の製造方法
US10699970B2 (en) * 2015-06-16 2020-06-30 Psemi Corporation Electrically testable integrated circuit packaging
TWI582905B (zh) * 2016-01-07 2017-05-11 晨星半導體股份有限公司 晶片封裝結構及其製作方法
CN108807198B (zh) * 2018-05-25 2020-07-07 南京恒电电子有限公司 一种实现微波混合集成电路射频裸芯片封装的方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1132462A (zh) * 1994-12-05 1996-10-02 摩托罗拉公司 球网格阵列组装件的多串衬底及其方法
US20010041390A1 (en) * 1998-02-10 2001-11-15 Hyundai Electronics Industries Co., Ltd. Integrated device package and fabrication methods thereof
US20030145461A1 (en) * 2002-02-01 2003-08-07 Norihiko Kasai Semiconductor device and method of manufacturing the same
US6822323B1 (en) * 2003-05-12 2004-11-23 Amkor Technology, Inc. Semiconductor package having more reliable electrical conductive patterns
US20060055026A1 (en) * 2001-12-29 2006-03-16 Wright Lance C Apparatus for and method of packaging semiconductor devices
US20070292990A1 (en) * 2002-09-17 2007-12-20 Marcos Karnezos Semiconductor multi-package module having wire bond interconnect between stacked packages

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5280193A (en) * 1992-05-04 1994-01-18 Lin Paul T Repairable semiconductor multi-package module having individualized package bodies on a PC board substrate
KR100280762B1 (ko) * 1992-11-03 2001-03-02 비센트 비.인그라시아 노출 후부를 갖는 열적 강화된 반도체 장치 및 그 제조방법
US6111306A (en) * 1993-12-06 2000-08-29 Fujitsu Limited Semiconductor device and method of producing the same and semiconductor device unit and method of producing the same
MY123146A (en) * 1996-03-28 2006-05-31 Intel Corp Perimeter matrix ball grid array circuit package with a populated center
JPH1154658A (ja) * 1997-07-30 1999-02-26 Hitachi Ltd 半導体装置及びその製造方法並びにフレーム構造体
US6117708A (en) * 1998-02-05 2000-09-12 Micron Technology, Inc. Use of residual organic compounds to facilitate gate break on a carrier substrate for a semiconductor device
JP3901427B2 (ja) * 1999-05-27 2007-04-04 松下電器産業株式会社 電子装置とその製造方法およびその製造装置
FR2800910B1 (fr) * 1999-11-04 2003-08-22 St Microelectronics Sa Boitier semi-conducteur optique et procede de fabrication d'un tel boitier
JP3866033B2 (ja) * 2000-12-14 2007-01-10 シャープ株式会社 半導体装置の製造方法
US6906414B2 (en) * 2000-12-22 2005-06-14 Broadcom Corporation Ball grid array package with patterned stiffener layer
US6617680B2 (en) * 2001-08-22 2003-09-09 Siliconware Precision Industries Co., Ltd. Chip carrier, semiconductor package and fabricating method thereof
US6692987B2 (en) * 2001-12-12 2004-02-17 Micron Technology, Inc. BOC BGA package for die with I-shaped bond pad layout
US20070200225A1 (en) * 2006-02-28 2007-08-30 Ruzaini Ibrahim Heat sink for semiconductor package

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1132462A (zh) * 1994-12-05 1996-10-02 摩托罗拉公司 球网格阵列组装件的多串衬底及其方法
US20010041390A1 (en) * 1998-02-10 2001-11-15 Hyundai Electronics Industries Co., Ltd. Integrated device package and fabrication methods thereof
US20060055026A1 (en) * 2001-12-29 2006-03-16 Wright Lance C Apparatus for and method of packaging semiconductor devices
US20030145461A1 (en) * 2002-02-01 2003-08-07 Norihiko Kasai Semiconductor device and method of manufacturing the same
US20070292990A1 (en) * 2002-09-17 2007-12-20 Marcos Karnezos Semiconductor multi-package module having wire bond interconnect between stacked packages
US6822323B1 (en) * 2003-05-12 2004-11-23 Amkor Technology, Inc. Semiconductor package having more reliable electrical conductive patterns

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106415825A (zh) * 2014-01-23 2017-02-15 株式会社电装 模塑封装
CN106415825B (zh) * 2014-01-23 2019-04-19 株式会社电装 模塑封装
CN106024647A (zh) * 2016-06-14 2016-10-12 重庆切普电子技术有限公司 一种cob封装器件低成本生产工艺
CN107170719A (zh) * 2017-05-17 2017-09-15 杭州士兰微电子股份有限公司 基板、封装结构及封装结构的制作方法
CN110120376A (zh) * 2019-04-30 2019-08-13 深圳市广和通无线股份有限公司 无针脚模块
CN115241136A (zh) * 2021-04-23 2022-10-25 北京梦之墨科技有限公司 一种晶圆级封装结构及工艺
CN115241135A (zh) * 2021-04-23 2022-10-25 北京梦之墨科技有限公司 一种晶圆级封装结构及工艺

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